Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	791885	1			T3	22053		T7	25956		T14	7793
auto[1]	10212587	1			T2	2577		T3	23463		T4	15865
auto[2]	668218	1			T3	19747		T5	2		T7	23217
auto[3]	10103419	1			T2	2583		T3	21261		T4	15915

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14150778	1			T2	5160		T3	1871		T4	26556
auto[1]	2084554	1			T3	10055		T4	2467		T5	86
auto[2]	2066265	1			T3	12220		T4	2516		T5	96
auto[3]	3474512	1			T3	62378		T4	241		T5	6

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8801329

1

T2

5155

T4

31744

T5

1078

auto[1]

12974780

1

T2

5

T3

86524

T4

36

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	320939	1			T7	21396		T14	6430		T41	1109
auto[0]	auto[0]	auto[1]	33160	1			T7	2157		T14	650		T41	108
auto[0]	auto[0]	auto[2]	33089	1			T7	2166		T14	659		T101	1
auto[0]	auto[0]	auto[3]	9177	1			T7	209		T14	50		T101	4
auto[0]	auto[1]	auto[0]	3284240	1			T2	2575		T4	13227		T5	421
auto[0]	auto[1]	auto[1]	351446	1			T4	1156		T5	40		T17	381
auto[0]	auto[1]	auto[2]	332483	1			T4	1342		T5	53		T16	1
auto[0]	auto[1]	auto[3]	77446	1			T4	119		T5	2		T17	45
auto[0]	auto[2]	auto[0]	287868	1			T5	2		T7	19662		T14	6073
auto[0]	auto[2]	auto[1]	29854	1			T7	1932		T14	613		T41	87
auto[0]	auto[2]	auto[2]	25651	1			T7	1453		T14	456		T41	121
auto[0]	auto[2]	auto[3]	7189	1			T7	144		T14	40		T101	2
auto[0]	auto[3]	auto[0]	3253181	1			T2	2580		T4	13300		T5	468
auto[0]	auto[3]	auto[1]	330001	1			T4	1307		T5	45		T17	410
auto[0]	auto[3]	auto[2]	345701	1			T4	1171		T5	43		T17	409
auto[0]	auto[3]	auto[3]	79904	1			T4	122		T5	4		T17	35
auto[1]	auto[0]	auto[0]	13225	1			T3	712		T7	25		T14	2
auto[1]	auto[0]	auto[1]	58662	1			T3	3349		T7	2		T14	1
auto[1]	auto[0]	auto[2]	58579	1			T3	3355		T7	1		T14	1
auto[1]	auto[0]	auto[3]	265054	1			T3	14637		T101	14576		T130	21479
auto[1]	auto[1]	auto[0]	3490165	1			T2	2		T3	497		T4	18
auto[1]	auto[1]	auto[1]	637359	1			T3	3817		T4	2		T5	1
auto[1]	auto[1]	auto[2]	599730	1			T3	2102		T4	1		T16	6137
auto[1]	auto[1]	auto[3]	1439718	1			T3	17047		T16	590		T6	642
auto[1]	auto[2]	auto[0]	11500	1			T3	437		T7	24		T14	2
auto[1]	auto[2]	auto[1]	50884	1			T3	2038		T7	1		T101	2935
auto[1]	auto[2]	auto[2]	46328	1			T3	3168		T7	1		T101	2159
auto[1]	auto[2]	auto[3]	208944	1			T3	14104		T101	9717		T130	17966
auto[1]	auto[3]	auto[0]	3489660	1			T2	3		T3	225		T4	11
auto[1]	auto[3]	auto[1]	593188	1			T3	851		T4	2		T16	6082
auto[1]	auto[3]	auto[2]	624704	1			T3	3595		T4	2		T16	6124
auto[1]	auto[3]	auto[3]	1387080	1			T3	16590		T16	596		T6	608