SRAM_CTRL/RET Simulation Results

Wednesday December 20 2023 20:02:55 UTC

GitHub Revision: 9601d3bbdd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30104064247514112511662306974640835321092728874679524971043777466318536599043

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.490m 670.541us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.680s 19.506us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.660s 43.616us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.910s 168.456us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 161.728us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.660s 63.749us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.660s 43.616us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 161.728us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 10.310s 597.578us 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.430s 526.621us 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 28.188m 20.075ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.803m 4.403ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.326m 6.144ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 24.886m 20.341ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 19.460s 2.638ms 44 50 88.00
V2 executable sram_ctrl_executable 28.575m 95.649ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.351m 212.253us 50 50 100.00
sram_ctrl_partial_access_b2b 10.907m 31.420ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.019m 279.705us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.518m 306.973us 50 50 100.00
V2 regwen sram_ctrl_regwen 26.568m 14.996ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 1.290s 267.890us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.146h 171.394ms 45 50 90.00
V2 alert_test sram_ctrl_alert_test 0.680s 20.312us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.130s 151.343us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.130s 151.343us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.680s 19.506us 5 5 100.00
sram_ctrl_csr_rw 0.660s 43.616us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 161.728us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.740s 30.149us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.680s 19.506us 5 5 100.00
sram_ctrl_csr_rw 0.660s 43.616us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 161.728us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.740s 30.149us 20 20 100.00
V2 TOTAL 728 740 98.38
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 12.420s 510.541us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.610s 465.673us 5 5 100.00
sram_ctrl_tl_intg_err 2.750s 1.757ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.610s 465.673us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.750s 1.757ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 26.568m 14.996ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.660s 43.616us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 28.575m 95.649ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 28.575m 95.649ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 28.575m 95.649ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 19.460s 2.638ms 44 50 88.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 12.420s 510.541us 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.490m 670.541us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.490m 670.541us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 28.575m 95.649ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.610s 465.673us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 19.460s 2.638ms 44 50 88.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.610s 465.673us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.610s 465.673us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.490m 670.541us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.610s 465.673us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 1.303h 2.871ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1028 1040 98.85

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.65 100.00 98.13 100.00 100.00 99.71 99.70 100.00

Failure Buckets

Past Results