Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13981183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59534031

1

T3

672778

T4

74027

T5

49413

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36640434	1			T3	368248		T4	40549		T5	136517
values[0x0]	17039075	1			T3	177475		T4	19780		T5	45770
values[0x1]	19835705	1			T3	190578		T4	20936		T5	90542

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6967005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66548209

1

T3

704703

T4

77612

T5

161501

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	341184	1			T5	1089		T6	9		T9	23
valid_sources[0x01]	326157	1			T5	1013		T6	11		T7	4
valid_sources[0x02]	265928	1			T3	4755		T5	935		T6	16
valid_sources[0x03]	285955	1			T5	1046		T6	15		T7	20
valid_sources[0x04]	274888	1			T5	1106		T6	20		T7	19
valid_sources[0x05]	268457	1			T5	1105		T6	4		T7	36
valid_sources[0x06]	262895	1			T5	1121		T6	7		T7	2
valid_sources[0x07]	347251	1			T5	919		T6	4		T9	10
valid_sources[0x08]	290446	1			T3	22		T5	1013		T6	5
valid_sources[0x09]	270500	1			T5	1076		T6	13		T7	32
valid_sources[0x0a]	305200	1			T5	1058		T6	12		T7	9
valid_sources[0x0b]	250124	1			T5	992		T6	6		T9	25
valid_sources[0x0c]	274872	1			T5	975		T6	10		T7	4
valid_sources[0x0d]	291879	1			T3	6067		T5	1296		T6	10
valid_sources[0x0e]	271243	1			T3	26449		T5	1047		T6	5
valid_sources[0x0f]	265284	1			T5	991		T6	14		T7	5
valid_sources[0x10]	296375	1			T3	866		T5	998		T6	19
valid_sources[0x11]	280719	1			T3	7207		T5	1006		T6	27
valid_sources[0x12]	239789	1			T5	1075		T6	19		T7	3
valid_sources[0x13]	279982	1			T5	1150		T6	21		T7	2
valid_sources[0x14]	288480	1			T5	1141		T6	9		T7	2
valid_sources[0x15]	298272	1			T5	1022		T6	16		T7	1
valid_sources[0x16]	273011	1			T3	275		T5	910		T6	7
valid_sources[0x17]	250844	1			T5	1093		T6	23		T7	10
valid_sources[0x18]	275102	1			T5	1043		T6	8		T7	7
valid_sources[0x19]	259982	1			T5	1160		T6	30		T7	6
valid_sources[0x1a]	259656	1			T5	1171		T6	36		T9	42
valid_sources[0x1b]	250725	1			T5	1185		T6	4		T9	9
valid_sources[0x1c]	275137	1			T3	4582		T5	1057		T6	18
valid_sources[0x1d]	261746	1			T5	1007		T6	12		T7	1
valid_sources[0x1e]	333454	1			T5	957		T6	9		T7	26
valid_sources[0x1f]	269001	1			T5	1123		T6	18		T7	15
valid_sources[0x20]	331610	1			T3	29		T5	1067		T6	18
valid_sources[0x21]	318822	1			T5	1173		T6	19		T7	6
valid_sources[0x22]	250743	1			T3	4284		T5	1037		T6	8
valid_sources[0x23]	273321	1			T4	12852		T5	1077		T6	4
valid_sources[0x24]	309898	1			T3	48		T4	13940		T5	1054
valid_sources[0x25]	360165	1			T3	6782		T4	718		T5	1076
valid_sources[0x26]	270195	1			T3	6936		T5	1080		T6	19
valid_sources[0x27]	281896	1			T5	1068		T6	13		T7	7
valid_sources[0x28]	243145	1			T5	935		T6	10		T7	4
valid_sources[0x29]	281535	1			T3	2786		T5	1124		T6	8
valid_sources[0x2a]	371582	1			T3	1526		T5	922		T6	13
valid_sources[0x2b]	243563	1			T5	1048		T6	5		T7	11
valid_sources[0x2c]	258836	1			T5	1105		T6	12		T7	12
valid_sources[0x2d]	443475	1			T3	21621		T5	1128		T6	3
valid_sources[0x2e]	239568	1			T3	147		T5	992		T6	9
valid_sources[0x2f]	306447	1			T3	40332		T5	996		T6	13
valid_sources[0x30]	295568	1			T4	4052		T5	1112		T6	7
valid_sources[0x31]	272969	1			T3	42		T5	1115		T6	16
valid_sources[0x32]	250725	1			T5	1083		T6	11		T7	7
valid_sources[0x33]	266298	1			T5	1086		T6	12		T7	1
valid_sources[0x34]	348250	1			T5	940		T6	12		T7	3
valid_sources[0x35]	239902	1			T5	951		T6	20		T7	5
valid_sources[0x36]	301655	1			T3	3772		T4	8628		T5	1161
valid_sources[0x37]	277833	1			T5	1129		T6	17		T7	4
valid_sources[0x38]	240268	1			T5	1005		T6	10		T7	3
valid_sources[0x39]	271053	1			T5	1034		T6	25		T7	4
valid_sources[0x3a]	252811	1			T5	1151		T6	14		T7	20
valid_sources[0x3b]	260664	1			T3	107		T5	1123		T6	7
valid_sources[0x3c]	297855	1			T3	6		T5	1112		T6	13
valid_sources[0x3d]	284908	1			T5	1088		T6	12		T7	9
valid_sources[0x3e]	354832	1			T5	962		T6	7		T7	16
valid_sources[0x3f]	311171	1			T3	4414		T5	985		T6	19
valid_sources[0x40]	256006	1			T3	15481		T5	1111		T6	27
valid_sources[0x41]	331425	1			T3	80		T4	3006		T5	1005
valid_sources[0x42]	264643	1			T3	2939		T5	1016		T6	11
valid_sources[0x43]	297323	1			T3	13		T5	1113		T6	16
valid_sources[0x44]	282736	1			T5	1208		T6	21		T7	6
valid_sources[0x45]	274967	1			T5	1136		T6	28		T7	5
valid_sources[0x46]	279925	1			T3	23		T5	1082		T6	3
valid_sources[0x47]	282843	1			T3	19926		T5	1147		T6	17
valid_sources[0x48]	269511	1			T5	1155		T6	27		T7	3
valid_sources[0x49]	238777	1			T5	1093		T6	35		T9	24
valid_sources[0x4a]	238081	1			T5	1121		T6	17		T7	12
valid_sources[0x4b]	262663	1			T5	958		T6	10		T7	5
valid_sources[0x4c]	287181	1			T5	1057		T6	5		T7	1
valid_sources[0x4d]	326879	1			T5	921		T6	16		T9	7
valid_sources[0x4e]	310070	1			T5	1094		T6	23		T9	24
valid_sources[0x4f]	329759	1			T5	1029		T7	13		T9	23
valid_sources[0x50]	293706	1			T5	1038		T6	20		T7	7
valid_sources[0x51]	301826	1			T3	14369		T5	1041		T6	22
valid_sources[0x52]	295270	1			T5	1026		T6	20		T7	2
valid_sources[0x53]	285850	1			T5	1180		T6	10		T9	33
valid_sources[0x54]	270682	1			T5	976		T6	25		T7	6
valid_sources[0x55]	356443	1			T5	1167		T6	12		T7	6
valid_sources[0x56]	256354	1			T5	1118		T6	6		T7	5
valid_sources[0x57]	292886	1			T5	1136		T6	12		T7	8
valid_sources[0x58]	385248	1			T3	2869		T4	4844		T5	1120
valid_sources[0x59]	256239	1			T3	7		T5	986		T6	29
valid_sources[0x5a]	286489	1			T3	42		T5	1162		T6	19
valid_sources[0x5b]	256060	1			T5	1020		T6	11		T7	27
valid_sources[0x5c]	245803	1			T5	1003		T6	15		T7	23
valid_sources[0x5d]	295224	1			T5	1048		T6	24		T7	18
valid_sources[0x5e]	257986	1			T3	3956		T5	1027		T6	34
valid_sources[0x5f]	275499	1			T5	1199		T6	27		T7	7
valid_sources[0x60]	312046	1			T3	30		T5	1094		T6	12
valid_sources[0x61]	298094	1			T5	1074		T6	23		T7	19
valid_sources[0x62]	334699	1			T3	41729		T5	1034		T6	12
valid_sources[0x63]	263599	1			T3	8358		T5	1084		T6	4
valid_sources[0x64]	275253	1			T5	1065		T6	25		T7	8
valid_sources[0x65]	248457	1			T5	1003		T6	15		T7	9
valid_sources[0x66]	279230	1			T5	1192		T6	36		T7	13
valid_sources[0x67]	296899	1			T5	1052		T6	6		T9	17
valid_sources[0x68]	318809	1			T5	1038		T6	10		T7	8
valid_sources[0x69]	258259	1			T5	1149		T6	22		T9	44
valid_sources[0x6a]	289191	1			T5	1098		T6	21		T7	2
valid_sources[0x6b]	298191	1			T5	1125		T6	16		T7	10
valid_sources[0x6c]	303240	1			T5	1108		T6	13		T7	20
valid_sources[0x6d]	249353	1			T3	4255		T5	1117		T6	15
valid_sources[0x6e]	310028	1			T5	943		T6	38		T7	1
valid_sources[0x6f]	270879	1			T5	1045		T6	12		T7	1
valid_sources[0x70]	323267	1			T3	9371		T5	986		T6	20
valid_sources[0x71]	302129	1			T3	46		T5	1006		T6	15
valid_sources[0x72]	256200	1			T5	1062		T6	3		T7	1
valid_sources[0x73]	271410	1			T5	1066		T6	11		T7	49
valid_sources[0x74]	272280	1			T3	4018		T5	1046		T6	11
valid_sources[0x75]	296146	1			T5	1015		T6	2		T7	7
valid_sources[0x76]	257223	1			T5	1020		T6	8		T7	14
valid_sources[0x77]	274562	1			T3	5269		T5	1213		T6	32
valid_sources[0x78]	310521	1			T3	15347		T5	1143		T6	26
valid_sources[0x79]	251077	1			T5	1021		T6	17		T7	5
valid_sources[0x7a]	262743	1			T3	2047		T5	953		T6	27
valid_sources[0x7b]	347691	1			T5	974		T6	12		T7	7
valid_sources[0x7c]	264342	1			T3	4841		T5	974		T6	13
valid_sources[0x7d]	265075	1			T5	1128		T6	9		T7	10
valid_sources[0x7e]	288891	1			T5	980		T6	15		T7	2
valid_sources[0x7f]	381417	1			T5	1045		T6	5		T9	24
valid_sources[0x80]	256828	1			T5	1059		T6	10		T9	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29655943

1

T3

336165

T4

36894

T5

24852

values[0x0]

all_enables

biggest_size

14939250

1

T3

168098

T4

18647

T5

12169

values[0x1]

all_enables

biggest_size

14938838

1

T3

168515

T4

18486

T5

12392

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2275985	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

135726

1

T3

79

T4

2

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2292930	1			T1	181		T2	520		T3	40732
values[0x0]	57558	1			T1	1		T2	1		T3	110
values[0x1]	61223	1			T3	110		T4	3		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1520489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

891222

1

T1

54

T2

148

T3

13742

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7233	1			T1	1		T5	2		T6	9
valid_sources[0x01]	7089	1			T1	3		T5	2		T6	9
valid_sources[0x02]	7338	1			T5	2		T6	13		T10	9
valid_sources[0x03]	18041	1			T5	3		T6	13		T10	8
valid_sources[0x04]	15135	1			T5	6		T6	18		T10	17
valid_sources[0x05]	11566	1			T5	2		T6	4		T10	10
valid_sources[0x06]	7374	1			T5	1		T6	13		T10	10
valid_sources[0x07]	7059	1			T5	6		T6	16		T10	11
valid_sources[0x08]	8212	1			T5	4		T6	9		T10	18
valid_sources[0x09]	7508	1			T5	1		T6	12		T10	16
valid_sources[0x0a]	13904	1			T5	2		T6	17		T10	5
valid_sources[0x0b]	10285	1			T6	14		T10	4		T12	1
valid_sources[0x0c]	10602	1			T1	1		T5	2		T6	20
valid_sources[0x0d]	8239	1			T5	2		T6	13		T10	6
valid_sources[0x0e]	6976	1			T6	9		T10	19		T8	2
valid_sources[0x0f]	7420	1			T1	3		T5	4		T6	18
valid_sources[0x10]	6840	1			T1	1		T5	2		T6	9
valid_sources[0x11]	7553	1			T1	1		T6	10		T10	6
valid_sources[0x12]	7092	1			T5	2		T6	12		T10	8
valid_sources[0x13]	7746	1			T5	1		T6	5		T10	21
valid_sources[0x14]	7876	1			T1	1		T5	3		T6	17
valid_sources[0x15]	6759	1			T5	3		T6	4		T10	11
valid_sources[0x16]	7065	1			T5	3		T6	9		T10	14
valid_sources[0x17]	6796	1			T5	2		T6	12		T10	9
valid_sources[0x18]	9486	1			T1	4		T5	7		T6	23
valid_sources[0x19]	7032	1			T1	3		T5	1		T6	5
valid_sources[0x1a]	6921	1			T5	3		T6	11		T10	5
valid_sources[0x1b]	6832	1			T5	2		T6	8		T10	7
valid_sources[0x1c]	7638	1			T5	2		T6	14		T9	235
valid_sources[0x1d]	6449	1			T6	23		T10	8		T8	4
valid_sources[0x1e]	8308	1			T1	2		T5	2		T6	13
valid_sources[0x1f]	7002	1			T1	8		T5	4		T6	6
valid_sources[0x20]	9673	1			T1	4		T5	3		T6	18
valid_sources[0x21]	11648	1			T1	4		T5	3		T6	6
valid_sources[0x22]	8980	1			T6	26		T10	19		T8	1
valid_sources[0x23]	8171	1			T1	1		T5	2		T6	29
valid_sources[0x24]	10738	1			T1	1		T5	3		T6	16
valid_sources[0x25]	16559	1			T5	2		T6	9		T10	14
valid_sources[0x26]	10691	1			T5	1		T6	1		T10	8
valid_sources[0x27]	7494	1			T1	1		T5	3		T6	22
valid_sources[0x28]	7258	1			T5	2		T6	3		T10	16
valid_sources[0x29]	7280	1			T6	28		T10	11		T8	3
valid_sources[0x2a]	6744	1			T1	5		T5	3		T6	6
valid_sources[0x2b]	7299	1			T5	7		T6	16		T10	21
valid_sources[0x2c]	8521	1			T1	4		T6	9		T10	10
valid_sources[0x2d]	6967	1			T1	3		T5	1		T6	11
valid_sources[0x2e]	20078	1			T1	1		T5	1		T6	23
valid_sources[0x2f]	14699	1			T5	4		T6	12		T10	13
valid_sources[0x30]	7041	1			T6	18		T10	10		T8	2
valid_sources[0x31]	8467	1			T5	6		T6	9		T10	16
valid_sources[0x32]	8509	1			T5	4		T6	12		T10	3
valid_sources[0x33]	6627	1			T5	5		T6	11		T10	12
valid_sources[0x34]	16928	1			T5	4		T6	17		T10	5
valid_sources[0x35]	8195	1			T1	2		T6	20		T10	12
valid_sources[0x36]	7250	1			T5	2		T6	17		T10	4
valid_sources[0x37]	7401	1			T1	2		T5	3		T6	12
valid_sources[0x38]	7141	1			T5	1		T6	21		T10	30
valid_sources[0x39]	7186	1			T1	2		T5	1		T6	14
valid_sources[0x3a]	7640	1			T5	5		T6	4		T10	9
valid_sources[0x3b]	10169	1			T6	28		T10	11		T12	12
valid_sources[0x3c]	17332	1			T5	2		T6	13		T10	13
valid_sources[0x3d]	8681	1			T5	2		T6	8		T10	9
valid_sources[0x3e]	8168	1			T5	3		T6	16		T10	6
valid_sources[0x3f]	7543	1			T1	2		T5	2		T6	1
valid_sources[0x40]	10672	1			T5	4		T6	10		T10	10
valid_sources[0x41]	7794	1			T6	19		T10	14		T8	3
valid_sources[0x42]	15435	1			T5	1		T6	9		T10	15
valid_sources[0x43]	13226	1			T1	2		T5	1		T6	11
valid_sources[0x44]	6850	1			T1	3		T5	4		T6	13
valid_sources[0x45]	19647	1			T1	3		T5	1		T6	15
valid_sources[0x46]	7079	1			T6	8		T10	6		T8	2
valid_sources[0x47]	24219	1			T1	1		T6	32		T10	5
valid_sources[0x48]	8471	1			T5	1		T6	9		T10	19
valid_sources[0x49]	7266	1			T5	3		T6	10		T10	13
valid_sources[0x4a]	7191	1			T5	2		T6	5		T10	17
valid_sources[0x4b]	12183	1			T5	1		T6	17		T10	24
valid_sources[0x4c]	7500	1			T5	1		T6	13		T10	11
valid_sources[0x4d]	36984	1			T5	1		T6	15		T10	9
valid_sources[0x4e]	17481	1			T5	1		T6	9		T10	8
valid_sources[0x4f]	7738	1			T6	21		T10	12		T8	1
valid_sources[0x50]	8860	1			T1	2		T5	1		T6	13
valid_sources[0x51]	14978	1			T5	3		T6	6		T10	10
valid_sources[0x52]	8476	1			T1	1		T6	11		T10	11
valid_sources[0x53]	12524	1			T5	1		T6	10		T10	13
valid_sources[0x54]	8527	1			T5	1		T6	9		T10	11
valid_sources[0x55]	7009	1			T5	3		T6	18		T10	9
valid_sources[0x56]	11836	1			T6	13		T10	9		T8	2
valid_sources[0x57]	7558	1			T5	2		T6	24		T10	9
valid_sources[0x58]	18349	1			T5	3		T6	19		T10	14
valid_sources[0x59]	18894	1			T5	3		T6	13		T10	3
valid_sources[0x5a]	7730	1			T5	3		T6	18		T10	10
valid_sources[0x5b]	6753	1			T5	1		T6	9		T10	7
valid_sources[0x5c]	8987	1			T5	7		T6	13		T10	9
valid_sources[0x5d]	6856	1			T1	2		T5	2		T6	21
valid_sources[0x5e]	7525	1			T6	12		T10	15		T8	2
valid_sources[0x5f]	7350	1			T5	4		T6	18		T10	10
valid_sources[0x60]	7033	1			T5	1		T6	18		T10	17
valid_sources[0x61]	8171	1			T5	1		T6	4		T10	15
valid_sources[0x62]	7090	1			T5	8		T6	11		T10	10
valid_sources[0x63]	7306	1			T5	2		T6	22		T10	6
valid_sources[0x64]	13506	1			T5	2		T6	17		T10	8
valid_sources[0x65]	6809	1			T5	4		T6	9		T10	9
valid_sources[0x66]	7103	1			T5	2		T6	18		T10	10
valid_sources[0x67]	6644	1			T5	4		T6	13		T10	13
valid_sources[0x68]	6741	1			T5	2		T6	16		T10	10
valid_sources[0x69]	7974	1			T5	3		T6	8		T10	10
valid_sources[0x6a]	7053	1			T5	2		T6	13		T10	7
valid_sources[0x6b]	41272	1			T5	4		T6	9		T10	15
valid_sources[0x6c]	7154	1			T1	1		T5	2		T6	8
valid_sources[0x6d]	8303	1			T1	5		T6	10		T10	28
valid_sources[0x6e]	9948	1			T1	5		T5	2		T6	6
valid_sources[0x6f]	6837	1			T6	21		T10	13		T8	6
valid_sources[0x70]	8485	1			T5	2		T6	21		T10	13
valid_sources[0x71]	14090	1			T5	5		T6	2		T10	12
valid_sources[0x72]	9035	1			T1	4		T5	1		T6	29
valid_sources[0x73]	7974	1			T1	1		T5	5		T6	10
valid_sources[0x74]	7126	1			T5	1		T6	24		T10	7
valid_sources[0x75]	8899	1			T5	2		T6	9		T10	5
valid_sources[0x76]	48236	1			T3	40952		T5	1		T6	29
valid_sources[0x77]	7291	1			T1	1		T5	3		T6	17
valid_sources[0x78]	7250	1			T1	5		T5	2		T6	23
valid_sources[0x79]	16422	1			T5	1		T6	17		T10	17
valid_sources[0x7a]	6831	1			T6	18		T10	9		T12	3
valid_sources[0x7b]	10187	1			T5	7		T6	15		T10	11
valid_sources[0x7c]	6607	1			T5	5		T6	10		T10	7
valid_sources[0x7d]	7896	1			T5	2		T6	18		T10	10
valid_sources[0x7e]	13638	1			T5	4		T6	12		T10	10
valid_sources[0x7f]	15062	1			T1	1		T5	2		T6	16
valid_sources[0x80]	6857	1			T1	1		T5	3		T6	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36922

1

T3

23

T6

17

T8

4

values[0x0]

all_enables

biggest_size

50253

1

T3

32

T4

2

T5

1

values[0x1]

all_enables

biggest_size

48551

1

T3

24

T6

5

T13

1