Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13676306

1

T3

54221

T4

7238

T5

223416

full_word

54559040

1

T3

581550

T4

74027

T5

49413

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68235046	1			T3	635771		T4	81265		T5	272829
auto[TlIntgErrCmd]	88	1			T47	3		T48	3		T55	4
auto[TlIntgErrData]	99	1			T47	3		T48	4		T54	5
auto[TlIntgErrBoth]	113	1			T47	4		T48	3		T54	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31273848

1

T3

268575

T4

40549

T5

136517

auto[1]

36961498

1

T3

367196

T4

40716

T5

136312

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6531803	1			T3	22860		T4	3655		T5	111665
auto[TlIntgErrNone]	partial	auto[1]	7144229	1			T3	31361		T4	3583		T5	111751
auto[TlIntgErrNone]	full_word	auto[0]	24741899	1			T3	245715		T4	36894		T5	24852
auto[TlIntgErrNone]	full_word	auto[1]	29817115	1			T3	335835		T4	37133		T5	24561
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T47	2		T48	3		T55	3
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T47	1		T55	1		T56	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T66	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T111	2		T116	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T48	1		T54	5		T55	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T47	3		T48	1		T55	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T48	1		T56	1		T118	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T48	1		T111	1		T114	2
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T47	1		T48	1		T54	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T47	3		T48	1		T54	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T56	2		T66	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T48	1		T54	1		T66	1