Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	561171	1			T5	34795		T6	28		T7	235
auto[1]	10582471	1			T3	63623		T4	24606		T5	29478
auto[2]	473710	1			T5	29614		T6	22		T7	147
auto[3]	10507147	1			T3	63348		T4	25014		T5	24831

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14511227	1			T3	104746		T4	41398		T5	2487
auto[1]	2115917	1			T3	10605		T4	3910		T5	15477
auto[2]	2110315	1			T3	10562		T4	3961		T5	14708
auto[3]	3387040	1			T3	1058		T4	351		T5	86046

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8680229

1

T3

126845

T4

49568

T6

62

auto[1]

13444270

1

T3

126

T4

52

T5

118718

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	288418	1			T6	20		T9	30		T8	9
auto[0]	auto[0]	auto[1]	29917	1			T6	6		T9	132		T30	218
auto[0]	auto[0]	auto[2]	29836	1			T6	2		T9	138		T30	200
auto[0]	auto[0]	auto[3]	10521	1			T7	233		T9	719		T30	25
auto[0]	auto[1]	auto[0]	3281022	1			T3	52381		T4	20459		T6	4
auto[0]	auto[1]	auto[1]	346441	1			T3	5305		T4	1860		T6	3
auto[0]	auto[1]	auto[2]	329198	1			T3	5332		T4	2089		T7	5
auto[0]	auto[1]	auto[3]	68720	1			T3	547		T4	174		T7	186
auto[0]	auto[2]	auto[0]	251763	1			T6	15		T9	35		T8	6
auto[0]	auto[2]	auto[1]	26029	1			T6	4		T7	7		T9	128
auto[0]	auto[2]	auto[2]	23765	1			T6	3		T7	1		T9	96
auto[0]	auto[2]	auto[3]	7945	1			T7	139		T9	445		T30	13
auto[0]	auto[3]	auto[0]	3246628	1			T3	52268		T4	20894		T6	2
auto[0]	auto[3]	auto[1]	326362	1			T3	5287		T4	2047		T7	3
auto[0]	auto[3]	auto[2]	343267	1			T3	5215		T4	1870		T6	3
auto[0]	auto[3]	auto[3]	70397	1			T3	510		T4	175		T7	227
auto[1]	auto[0]	auto[0]	6966	1			T5	1182		T9	1		T30	2
auto[1]	auto[0]	auto[1]	30111	1			T5	5137		T125	2282		T126	1
auto[1]	auto[0]	auto[2]	30149	1			T5	5159		T125	2332		T126	1
auto[1]	auto[0]	auto[3]	135253	1			T5	23317		T7	2		T127	2
auto[1]	auto[1]	auto[0]	3715743	1			T3	41		T4	21		T5	178
auto[1]	auto[1]	auto[1]	677721	1			T3	9		T4	2		T5	5244
auto[1]	auto[1]	auto[2]	658904	1			T3	7		T5	777		T13	6678
auto[1]	auto[1]	auto[3]	1504722	1			T3	1		T4	1		T5	23279
auto[1]	auto[2]	auto[0]	5966	1			T5	1044		T30	1		T16	1
auto[1]	auto[2]	auto[1]	24978	1			T5	4656		T28	1		T125	1365
auto[1]	auto[2]	auto[2]	24121	1			T5	4356		T16	1		T125	2472
auto[1]	auto[2]	auto[3]	109143	1			T5	19558		T125	11753		T126	1
auto[1]	auto[3]	auto[0]	3714721	1			T3	56		T4	24		T5	83
auto[1]	auto[3]	auto[1]	654358	1			T3	4		T4	1		T5	440
auto[1]	auto[3]	auto[2]	671075	1			T3	8		T4	2		T5	4416
auto[1]	auto[3]	auto[3]	1480339	1			T4	1		T5	19892		T9	1