Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	326364839	160807	0	0
ctrl_regwen_rd_A	326364839	10173	0	0
exec_rd_A	326364839	9405	0	0
exec_regwen_rd_A	326364839	9870	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326364839	160807	0	0
T26	132306	0	0	0
T31	29128	861	0	0
T32	0	4855	0	0
T33	0	3114	0	0
T47	0	5	0	0
T48	0	5	0	0
T49	0	3053	0	0
T50	0	428	0	0
T51	0	555	0	0
T52	0	22	0	0
T53	0	37	0	0
T58	5222	0	0	0
T59	124119	0	0	0
T60	6057	0	0	0
T61	934368	0	0	0
T62	339507	0	0	0
T63	2069	0	0	0
T64	636694	0	0	0
T65	10447	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326364839	10173	0	0
T26	132306	0	0	0
T31	29128	240	0	0
T33	0	605	0	0
T46	0	102	0	0
T48	0	67	0	0
T49	0	283	0	0
T53	0	26	0	0
T56	0	81	0	0
T58	5222	0	0	0
T59	124119	0	0	0
T60	6057	0	0	0
T61	934368	0	0	0
T62	339507	0	0	0
T63	2069	0	0	0
T64	636694	0	0	0
T65	10447	0	0	0
T72	0	9	0	0
T73	0	214	0	0
T75	0	5	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326364839	9405	0	0
T26	132306	0	0	0
T31	29128	181	0	0
T33	0	615	0	0
T46	0	60	0	0
T48	0	43	0	0
T49	0	245	0	0
T53	0	33	0	0
T56	0	93	0	0
T58	5222	0	0	0
T59	124119	0	0	0
T60	6057	0	0	0
T61	934368	0	0	0
T62	339507	0	0	0
T63	2069	0	0	0
T64	636694	0	0	0
T65	10447	0	0	0
T73	0	225	0	0
T75	0	3	0	0
T84	0	7	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326364839	9870	0	0
T26	132306	0	0	0
T31	29128	250	0	0
T33	0	714	0	0
T46	0	80	0	0
T48	0	53	0	0
T49	0	276	0	0
T53	0	17	0	0
T58	5222	0	0	0
T59	124119	0	0	0
T60	6057	0	0	0
T61	934368	0	0	0
T62	339507	0	0	0
T63	2069	0	0	0
T64	636694	0	0	0
T65	10447	0	0	0
T72	0	3	0	0
T73	0	217	0	0
T75	0	6	0	0
T84	0	9	0	0