Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12948925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

50413466

1

T1

114

T2

1250

T3

202339

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31582187	1			T1	838		T2	645		T3	111019
values[0x0]	14594671	1			T1	346		T2	288		T3	54012
values[0x1]	17185533	1			T1	762		T2	317		T3	57499

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6449602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

56912789

1

T1

941

T2

1250

T3

212507

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	216377	1			T3	879		T5	3		T6	18
valid_sources[0x01]	222659	1			T1	38		T3	858		T5	2
valid_sources[0x02]	256171	1			T3	897		T4	5148		T6	9
valid_sources[0x03]	243749	1			T3	844		T5	2		T6	20
valid_sources[0x04]	220701	1			T1	15		T3	854		T5	3
valid_sources[0x05]	245877	1			T3	836		T5	4		T6	40
valid_sources[0x06]	232683	1			T3	854		T5	3		T6	6
valid_sources[0x07]	242775	1			T1	25		T3	878		T5	1
valid_sources[0x08]	253446	1			T3	962		T5	2		T6	18
valid_sources[0x09]	229443	1			T3	880		T4	12101		T5	1
valid_sources[0x0a]	227922	1			T3	860		T5	3		T6	38
valid_sources[0x0b]	221744	1			T3	909		T4	5064		T5	1
valid_sources[0x0c]	222765	1			T3	911		T4	41		T5	1
valid_sources[0x0d]	212933	1			T3	900		T5	1		T6	25
valid_sources[0x0e]	256284	1			T3	835		T5	6		T6	2
valid_sources[0x0f]	217405	1			T3	931		T6	28		T12	16
valid_sources[0x10]	212238	1			T3	867		T5	4		T6	19
valid_sources[0x11]	223807	1			T3	845		T6	18		T12	5
valid_sources[0x12]	234941	1			T3	830		T4	2		T5	1
valid_sources[0x13]	261043	1			T3	854		T4	23		T6	20
valid_sources[0x14]	225249	1			T3	868		T5	4		T6	15
valid_sources[0x15]	272416	1			T3	920		T5	3		T6	14
valid_sources[0x16]	257197	1			T3	829		T6	4		T12	18
valid_sources[0x17]	241420	1			T3	809		T4	768		T6	8
valid_sources[0x18]	284419	1			T3	861		T4	10402		T6	13
valid_sources[0x19]	289304	1			T1	16		T3	855		T4	1068
valid_sources[0x1a]	253277	1			T3	861		T5	4		T6	8
valid_sources[0x1b]	321963	1			T3	859		T5	3		T6	13
valid_sources[0x1c]	315055	1			T1	100		T3	926		T5	1
valid_sources[0x1d]	220251	1			T3	895		T5	1		T6	17
valid_sources[0x1e]	242261	1			T3	901		T4	41		T5	2
valid_sources[0x1f]	244682	1			T3	873		T5	3		T6	10
valid_sources[0x20]	228763	1			T3	829		T5	1		T6	15
valid_sources[0x21]	253453	1			T1	82		T3	880		T5	2
valid_sources[0x22]	234019	1			T3	862		T5	1		T6	9
valid_sources[0x23]	306507	1			T3	918		T5	4		T6	24
valid_sources[0x24]	234979	1			T1	16		T3	823		T5	4
valid_sources[0x25]	252437	1			T3	832		T5	2		T6	19
valid_sources[0x26]	230042	1			T1	20		T3	855		T5	2
valid_sources[0x27]	239277	1			T3	897		T4	9012		T5	3
valid_sources[0x28]	247782	1			T3	873		T5	1		T6	20
valid_sources[0x29]	231814	1			T3	855		T5	2		T6	16
valid_sources[0x2a]	226313	1			T3	851		T6	25		T12	56
valid_sources[0x2b]	213453	1			T3	862		T5	1		T6	7
valid_sources[0x2c]	243589	1			T3	878		T5	2		T6	25
valid_sources[0x2d]	220178	1			T3	881		T4	74		T5	4
valid_sources[0x2e]	223298	1			T3	898		T5	1		T6	20
valid_sources[0x2f]	221633	1			T3	869		T6	15		T12	65
valid_sources[0x30]	228052	1			T3	865		T5	2		T6	10
valid_sources[0x31]	267914	1			T1	52		T3	840		T5	1
valid_sources[0x32]	254461	1			T3	850		T4	10		T5	1
valid_sources[0x33]	264811	1			T3	887		T5	3		T6	5
valid_sources[0x34]	243983	1			T3	880		T6	15		T12	59
valid_sources[0x35]	222829	1			T3	879		T5	3		T6	16
valid_sources[0x36]	239931	1			T3	865		T5	1		T6	25
valid_sources[0x37]	226433	1			T3	862		T5	2		T6	13
valid_sources[0x38]	272407	1			T3	794		T6	12		T12	29
valid_sources[0x39]	280955	1			T3	819		T5	2		T6	13
valid_sources[0x3a]	215388	1			T3	896		T5	3		T6	22
valid_sources[0x3b]	236629	1			T3	847		T5	3		T6	14
valid_sources[0x3c]	319895	1			T3	841		T5	3		T6	12
valid_sources[0x3d]	255635	1			T3	859		T6	10		T12	13
valid_sources[0x3e]	223349	1			T3	909		T5	2		T6	18
valid_sources[0x3f]	249466	1			T3	943		T5	3		T6	14
valid_sources[0x40]	215219	1			T3	810		T5	5		T6	17
valid_sources[0x41]	248794	1			T3	847		T4	81		T6	21
valid_sources[0x42]	263705	1			T1	58		T3	955		T5	2
valid_sources[0x43]	258070	1			T3	855		T5	3		T6	18
valid_sources[0x44]	229527	1			T3	870		T5	6		T6	22
valid_sources[0x45]	287002	1			T3	830		T6	14		T12	46
valid_sources[0x46]	281621	1			T3	927		T5	2		T6	12
valid_sources[0x47]	225188	1			T1	20		T3	880		T5	2
valid_sources[0x48]	231518	1			T3	820		T5	1		T6	17
valid_sources[0x49]	232312	1			T3	923		T5	4		T6	10
valid_sources[0x4a]	215620	1			T3	872		T5	3		T6	12
valid_sources[0x4b]	296540	1			T3	863		T5	2		T6	25
valid_sources[0x4c]	232872	1			T1	3		T3	901		T5	5
valid_sources[0x4d]	244059	1			T3	864		T5	1		T6	38
valid_sources[0x4e]	250272	1			T3	860		T4	22795		T5	3
valid_sources[0x4f]	236398	1			T1	17		T3	894		T6	9
valid_sources[0x50]	214065	1			T1	15		T3	952		T5	2
valid_sources[0x51]	216432	1			T3	905		T5	1		T6	28
valid_sources[0x52]	233607	1			T1	29		T3	847		T5	1
valid_sources[0x53]	232098	1			T3	897		T6	20		T12	36
valid_sources[0x54]	226156	1			T3	902		T5	3		T6	26
valid_sources[0x55]	272173	1			T3	904		T5	2		T6	7
valid_sources[0x56]	243355	1			T3	890		T4	5222		T6	15
valid_sources[0x57]	238144	1			T3	859		T5	2		T6	13
valid_sources[0x58]	246383	1			T3	871		T4	15706		T5	1
valid_sources[0x59]	223107	1			T3	877		T6	15		T12	93
valid_sources[0x5a]	227687	1			T3	843		T4	124		T6	13
valid_sources[0x5b]	315637	1			T3	862		T6	19		T12	43
valid_sources[0x5c]	270428	1			T3	896		T4	3947		T5	1
valid_sources[0x5d]	259258	1			T3	858		T5	3		T6	6
valid_sources[0x5e]	239013	1			T3	865		T5	1		T6	17
valid_sources[0x5f]	252615	1			T3	817		T5	6		T6	34
valid_sources[0x60]	271070	1			T3	868		T5	2		T6	8
valid_sources[0x61]	291601	1			T3	858		T5	7		T6	13
valid_sources[0x62]	251459	1			T3	795		T5	1		T6	22
valid_sources[0x63]	319994	1			T3	844		T4	14958		T6	10
valid_sources[0x64]	214111	1			T1	8		T3	861		T6	14
valid_sources[0x65]	240047	1			T3	822		T6	21		T12	31
valid_sources[0x66]	269310	1			T1	3		T3	877		T5	3
valid_sources[0x67]	216676	1			T1	227		T3	832		T5	5
valid_sources[0x68]	251014	1			T3	876		T5	4		T6	26
valid_sources[0x69]	220713	1			T3	915		T5	6		T6	10
valid_sources[0x6a]	233240	1			T1	29		T3	890		T4	1236
valid_sources[0x6b]	219615	1			T3	810		T6	23		T12	17
valid_sources[0x6c]	361597	1			T1	16		T3	842		T5	1
valid_sources[0x6d]	258872	1			T3	906		T4	18989		T6	31
valid_sources[0x6e]	244799	1			T3	818		T5	2		T6	24
valid_sources[0x6f]	233094	1			T3	873		T6	12		T12	55
valid_sources[0x70]	250596	1			T3	900		T6	27		T12	17
valid_sources[0x71]	224884	1			T1	194		T3	901		T5	1
valid_sources[0x72]	229134	1			T3	876		T6	13		T12	53
valid_sources[0x73]	237177	1			T3	860		T5	1		T6	21
valid_sources[0x74]	312053	1			T3	848		T5	2		T6	8
valid_sources[0x75]	236337	1			T3	885		T5	2		T6	14
valid_sources[0x76]	234510	1			T3	785		T5	3		T6	33
valid_sources[0x77]	217377	1			T1	16		T3	936		T5	2
valid_sources[0x78]	226378	1			T3	865		T5	4		T6	18
valid_sources[0x79]	250139	1			T1	59		T3	803		T5	4
valid_sources[0x7a]	316349	1			T3	882		T4	29797		T6	9
valid_sources[0x7b]	228480	1			T3	899		T4	31		T5	3
valid_sources[0x7c]	293543	1			T3	842		T5	1		T6	18
valid_sources[0x7d]	313879	1			T3	954		T6	14		T12	42
valid_sources[0x7e]	233599	1			T3	896		T5	2		T6	11
valid_sources[0x7f]	224280	1			T3	817		T5	2		T6	24
valid_sources[0x80]	275010	1			T3	825		T5	1		T6	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25112458

1

T1

6

T2

645

T3

100947

values[0x0]

all_enables

biggest_size

12651384

1

T1

54

T2

288

T3

50902

values[0x1]

all_enables

biggest_size

12649624

1

T1

54

T2

317

T3

50490

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1913831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122935

1

T2

1

T3

8

T4

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1929440	1			T1	518		T2	1048		T3	9338
values[0x0]	51996	1			T3	22		T4	18		T6	574
values[0x1]	55330	1			T1	1		T2	2		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1278522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

758244

1

T1

159

T2

332

T3

3077

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5948	1			T1	4		T3	27		T6	21
valid_sources[0x01]	6430	1			T2	5		T3	53		T6	8
valid_sources[0x02]	5662	1			T2	5		T3	39		T6	7
valid_sources[0x03]	7681	1			T1	2		T3	24		T6	9
valid_sources[0x04]	6413	1			T2	4		T3	35		T6	13
valid_sources[0x05]	6236	1			T1	1		T2	8		T3	36
valid_sources[0x06]	7137	1			T1	1		T3	45		T6	10
valid_sources[0x07]	8600	1			T1	3		T2	6		T3	26
valid_sources[0x08]	6058	1			T2	2		T3	31		T6	11
valid_sources[0x09]	9059	1			T1	4		T2	5		T3	50
valid_sources[0x0a]	6814	1			T1	2		T2	4		T3	34
valid_sources[0x0b]	5927	1			T2	3		T3	32		T5	1
valid_sources[0x0c]	5987	1			T2	1		T3	47		T6	11
valid_sources[0x0d]	7654	1			T2	3		T3	34		T6	9
valid_sources[0x0e]	6512	1			T2	13		T3	48		T6	12
valid_sources[0x0f]	6268	1			T1	3		T2	5		T3	26
valid_sources[0x10]	6637	1			T1	1		T2	2		T3	32
valid_sources[0x11]	8933	1			T1	2		T2	11		T3	41
valid_sources[0x12]	7973	1			T2	5		T3	25		T5	1
valid_sources[0x13]	6600	1			T1	2		T2	1		T3	40
valid_sources[0x14]	6546	1			T1	2		T2	8		T3	32
valid_sources[0x15]	7948	1			T1	5		T2	3		T3	35
valid_sources[0x16]	6000	1			T2	8		T3	44		T5	1
valid_sources[0x17]	6655	1			T1	2		T2	3		T3	48
valid_sources[0x18]	6146	1			T1	3		T2	2		T3	29
valid_sources[0x19]	6455	1			T1	1		T2	9		T3	27
valid_sources[0x1a]	6124	1			T1	1		T2	1		T3	48
valid_sources[0x1b]	6729	1			T1	8		T2	3		T3	24
valid_sources[0x1c]	5512	1			T1	5		T2	1		T3	42
valid_sources[0x1d]	9500	1			T1	1		T2	1		T3	28
valid_sources[0x1e]	5907	1			T1	3		T2	1		T3	30
valid_sources[0x1f]	14133	1			T1	2		T2	6		T3	35
valid_sources[0x20]	6089	1			T2	5		T3	31		T6	10
valid_sources[0x21]	6253	1			T1	1		T2	11		T3	15
valid_sources[0x22]	30661	1			T1	4		T3	29		T6	9
valid_sources[0x23]	7410	1			T1	1		T2	5		T3	43
valid_sources[0x24]	6272	1			T1	2		T3	54		T6	13
valid_sources[0x25]	5786	1			T1	4		T2	1		T3	23
valid_sources[0x26]	9912	1			T1	1		T2	2		T3	58
valid_sources[0x27]	8495	1			T1	3		T3	36		T6	9
valid_sources[0x28]	6022	1			T1	1		T2	9		T3	39
valid_sources[0x29]	7966	1			T1	1		T2	3		T3	26
valid_sources[0x2a]	8444	1			T1	3		T3	46		T6	11
valid_sources[0x2b]	6125	1			T2	1		T3	47		T6	8
valid_sources[0x2c]	6356	1			T1	5		T2	3		T3	27
valid_sources[0x2d]	5854	1			T1	1		T2	6		T3	15
valid_sources[0x2e]	6614	1			T2	5		T3	41		T6	9
valid_sources[0x2f]	7438	1			T1	2		T2	7		T3	34
valid_sources[0x30]	6325	1			T2	7		T3	50		T6	15
valid_sources[0x31]	6344	1			T1	2		T2	8		T3	32
valid_sources[0x32]	6953	1			T1	2		T2	9		T3	52
valid_sources[0x33]	16434	1			T1	4		T2	7		T3	31
valid_sources[0x34]	6846	1			T1	4		T2	7		T3	16
valid_sources[0x35]	6981	1			T1	1		T3	41		T5	1
valid_sources[0x36]	6033	1			T1	1		T3	33		T6	6
valid_sources[0x37]	6287	1			T1	1		T2	2		T3	51
valid_sources[0x38]	6150	1			T1	1		T2	3		T3	19
valid_sources[0x39]	7604	1			T1	3		T2	1		T3	43
valid_sources[0x3a]	7459	1			T1	1		T3	61		T6	7
valid_sources[0x3b]	5940	1			T3	44		T6	8		T11	5
valid_sources[0x3c]	15593	1			T1	1		T2	8		T3	39
valid_sources[0x3d]	7072	1			T1	2		T2	1		T3	26
valid_sources[0x3e]	7375	1			T2	11		T3	54		T6	9
valid_sources[0x3f]	6239	1			T1	2		T2	8		T3	32
valid_sources[0x40]	6433	1			T1	3		T2	1		T3	22
valid_sources[0x41]	7003	1			T1	2		T2	2		T3	59
valid_sources[0x42]	6734	1			T1	2		T2	12		T3	30
valid_sources[0x43]	5963	1			T1	2		T2	1		T3	52
valid_sources[0x44]	6050	1			T1	2		T2	4		T3	29
valid_sources[0x45]	6157	1			T1	1		T2	5		T3	48
valid_sources[0x46]	6422	1			T1	3		T3	37		T6	12
valid_sources[0x47]	6526	1			T1	1		T2	2		T3	37
valid_sources[0x48]	7498	1			T1	3		T2	7		T3	47
valid_sources[0x49]	7589	1			T3	36		T6	11		T11	3
valid_sources[0x4a]	7139	1			T1	1		T2	6		T3	56
valid_sources[0x4b]	18163	1			T1	3		T2	3		T3	36
valid_sources[0x4c]	10453	1			T1	6		T2	8		T3	48
valid_sources[0x4d]	12021	1			T2	5		T3	56		T6	13
valid_sources[0x4e]	9425	1			T1	1		T2	3		T3	24
valid_sources[0x4f]	6035	1			T1	5		T2	7		T3	27
valid_sources[0x50]	6018	1			T1	2		T2	9		T3	27
valid_sources[0x51]	7565	1			T1	1		T2	2		T3	50
valid_sources[0x52]	14660	1			T1	1		T2	3		T3	43
valid_sources[0x53]	7354	1			T1	3		T2	3		T3	41
valid_sources[0x54]	6878	1			T1	3		T2	4		T3	31
valid_sources[0x55]	5957	1			T1	7		T2	4		T3	39
valid_sources[0x56]	5700	1			T1	2		T2	4		T3	44
valid_sources[0x57]	6340	1			T2	1		T3	23		T5	1
valid_sources[0x58]	6945	1			T1	2		T2	9		T3	30
valid_sources[0x59]	5795	1			T2	3		T3	52		T6	10
valid_sources[0x5a]	6309	1			T1	3		T2	9		T3	45
valid_sources[0x5b]	12556	1			T1	1		T2	8		T3	35
valid_sources[0x5c]	6116	1			T1	7		T2	4		T3	39
valid_sources[0x5d]	7123	1			T1	1		T2	2		T3	34
valid_sources[0x5e]	5864	1			T1	3		T2	3		T3	43
valid_sources[0x5f]	12090	1			T2	2		T3	35		T6	11
valid_sources[0x60]	6967	1			T1	6		T2	2		T3	39
valid_sources[0x61]	18528	1			T1	2		T2	2		T3	56
valid_sources[0x62]	6918	1			T1	4		T2	4		T3	39
valid_sources[0x63]	6243	1			T1	3		T2	16		T3	27
valid_sources[0x64]	6524	1			T2	6		T3	38		T6	5
valid_sources[0x65]	7020	1			T1	3		T2	8		T3	46
valid_sources[0x66]	6073	1			T2	6		T3	36		T5	2
valid_sources[0x67]	6359	1			T2	3		T3	42		T6	6
valid_sources[0x68]	8666	1			T1	3		T3	35		T6	11
valid_sources[0x69]	6414	1			T1	4		T2	8		T3	19
valid_sources[0x6a]	6783	1			T1	4		T2	1		T3	52
valid_sources[0x6b]	6535	1			T1	2		T2	3		T3	45
valid_sources[0x6c]	6036	1			T1	4		T2	2		T3	34
valid_sources[0x6d]	12006	1			T2	5		T3	33		T6	9
valid_sources[0x6e]	7253	1			T1	2		T2	1		T3	42
valid_sources[0x6f]	9704	1			T1	4		T3	35		T6	11
valid_sources[0x70]	14054	1			T1	1		T2	1		T3	37
valid_sources[0x71]	5901	1			T1	2		T2	4		T3	30
valid_sources[0x72]	6748	1			T1	1		T2	4		T3	25
valid_sources[0x73]	10826	1			T1	2		T2	8		T3	36
valid_sources[0x74]	6409	1			T1	3		T2	1		T3	31
valid_sources[0x75]	6596	1			T1	1		T2	3		T3	20
valid_sources[0x76]	7045	1			T2	11		T3	34		T6	13
valid_sources[0x77]	5833	1			T2	15		T3	48		T6	12
valid_sources[0x78]	6359	1			T1	3		T3	22		T6	4
valid_sources[0x79]	7200	1			T1	2		T3	26		T6	11
valid_sources[0x7a]	6909	1			T1	3		T2	2		T3	30
valid_sources[0x7b]	6338	1			T1	5		T2	5		T3	27
valid_sources[0x7c]	15293	1			T1	1		T3	45		T6	10
valid_sources[0x7d]	6472	1			T1	1		T3	39		T6	9
valid_sources[0x7e]	5941	1			T1	2		T3	32		T6	7
valid_sources[0x7f]	6080	1			T2	2		T3	58		T6	13
valid_sources[0x80]	16137	1			T1	2		T2	4		T3	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33538

1

T6

380

T14

8

T15

1327

values[0x0]

all_enables

biggest_size

45298

1

T3

6

T4

8

T6

567

values[0x1]

all_enables

biggest_size

44099

1

T2

1

T3

2

T4

1