Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

12674974

1

T1

1832

T3

20191

T4

17129

full_word

45965605

1

T1

114

T2

1250

T3

202339

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	58640279	1			T1	1946		T2	1250		T3	222530
auto[TlIntgErrCmd]	93	1			T38	1		T39	3		T93	5
auto[TlIntgErrData]	91	1			T38	4		T39	3		T93	6
auto[TlIntgErrBoth]	116	1			T38	5		T39	4		T93	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26797785

1

T1

838

T2

645

T3

111019

auto[1]

31842794

1

T1

1108

T2

605

T3

111511

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6065552	1			T1	832		T3	10072		T4	8484
auto[TlIntgErrNone]	partial	auto[1]	6609145	1			T1	1000		T3	10119		T4	8645
auto[TlIntgErrNone]	full_word	auto[0]	20732110	1			T1	6		T2	645		T3	100947
auto[TlIntgErrNone]	full_word	auto[1]	25233472	1			T1	108		T2	605		T3	101392
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T93	2		T102	4		T104	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T38	1		T39	3		T93	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T106	1		T107	1		T105	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T93	1		T102	1		T104	2
auto[TlIntgErrData]	partial	auto[0]	42	1			T38	1		T39	2		T93	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T38	3		T39	1		T93	5
auto[TlIntgErrData]	full_word	auto[0]	1	1			T108	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T104	1		T109	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T38	2		T39	1		T93	7
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T38	2		T39	3		T93	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T38	1		T101	1		T106	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T104	1		T106	1		T103	2