Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	561781	1			T13	358		T14	3575		T15	1572
auto[1]	9134310	1			T1	772		T2	645		T3	63896
auto[2]	476863	1			T13	224		T14	3183		T15	1423
auto[3]	9059286	1			T1	994		T2	604		T3	64426

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12541535	1			T1	9		T2	1249		T3	106237
auto[1]	1839830	1			T1	105		T3	10461		T4	7418
auto[2]	1834316	1			T1	167		T3	10611		T4	7470
auto[3]	3016559	1			T1	1485		T3	1013		T4	789

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6777352

1

T1

1765

T2

1247

T3

128197

auto[1]

12454888

1

T1

1

T2

2

T3

125

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	244413	1			T13	289		T14	2904		T15	1283
auto[0]	auto[0]	auto[1]	24659	1			T13	29		T14	312		T15	122
auto[0]	auto[0]	auto[2]	24710	1			T13	35		T14	319		T15	150
auto[0]	auto[0]	auto[3]	6005	1			T13	5		T14	39		T15	16
auto[0]	auto[1]	auto[0]	2536751	1			T2	644		T3	52892		T4	36826
auto[0]	auto[1]	auto[1]	270667	1			T1	6		T3	5149		T4	3648
auto[0]	auto[1]	auto[2]	255322	1			T1	81		T3	5314		T4	3716
auto[0]	auto[1]	auto[3]	61188	1			T1	685		T3	479		T4	377
auto[0]	auto[2]	auto[0]	213340	1			T13	182		T14	2737		T15	1187
auto[0]	auto[2]	auto[1]	21615	1			T13	17		T14	254		T15	115
auto[0]	auto[2]	auto[2]	19830	1			T13	22		T14	178		T15	108
auto[0]	auto[2]	auto[3]	4501	1			T13	3		T14	13		T15	12
auto[0]	auto[3]	auto[0]	2507479	1			T1	9		T2	603		T3	53246
auto[0]	auto[3]	auto[1]	253685	1			T1	99		T3	5298		T4	3762
auto[0]	auto[3]	auto[2]	268475	1			T1	86		T3	5288		T4	3746
auto[0]	auto[3]	auto[3]	64712	1			T1	799		T3	531		T4	411
auto[1]	auto[0]	auto[0]	8813	1			T14	1		T15	1		T119	16
auto[1]	auto[0]	auto[1]	39040	1			T119	2		T30	3		T120	1
auto[1]	auto[0]	auto[2]	38773	1			T30	1		T27	1		T121	3
auto[1]	auto[0]	auto[3]	175368	1			T117	1		T118	1		T122	16427
auto[1]	auto[1]	auto[0]	3513166	1			T2	1		T3	47		T4	26
auto[1]	auto[1]	auto[1]	612940	1			T3	9		T4	5		T14	2
auto[1]	auto[1]	auto[2]	590275	1			T3	3		T4	4		T57	838
auto[1]	auto[1]	auto[3]	1294001	1			T3	3		T12	6		T57	10911
auto[1]	auto[2]	auto[0]	7506	1			T14	1		T15	1		T119	9
auto[1]	auto[2]	auto[1]	32910	1			T119	3		T37	1		T30	2
auto[1]	auto[2]	auto[2]	32224	1			T119	2		T120	1		T121	1
auto[1]	auto[2]	auto[3]	144937	1			T30	1		T122	15825		T123	12323
auto[1]	auto[3]	auto[0]	3510067	1			T2	1		T3	52		T4	34
auto[1]	auto[3]	auto[1]	584314	1			T3	5		T4	3		T57	865
auto[1]	auto[3]	auto[2]	604707	1			T3	6		T4	4		T12	1
auto[1]	auto[3]	auto[3]	1265847	1			T1	1		T4	1		T12	4