Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	275129486	141027	0	0
ctrl_regwen_rd_A	275129486	7315	0	0
exec_rd_A	275129486	6885	0	0
exec_regwen_rd_A	275129486	7334	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275129486	141027	0	0
T6	55825	2278	0	0
T7	31419	0	0	0
T11	24662	0	0	0
T12	18967	0	0	0
T13	38078	0	0	0
T14	298441	0	0	0
T15	0	5831	0	0
T16	519715	0	0	0
T17	4034	0	0	0
T18	30746	0	0	0
T31	0	3056	0	0
T32	1868	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T40	0	1421	0	0
T41	0	2080	0	0
T42	0	3359	0	0
T43	0	293	0	0
T44	0	723	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275129486	7315	0	0
T15	312433	1036	0	0
T31	100486	302	0	0
T40	26994	0	0	0
T41	93352	0	0	0
T43	0	3	0	0
T49	0	32	0	0
T50	0	42	0	0
T55	0	36	0	0
T56	0	14	0	0
T62	0	28	0	0
T79	0	25	0	0
T82	0	21	0	0
T94	12986	0	0	0
T95	1714	0	0	0
T96	14866	0	0	0
T97	65350	0	0	0
T98	356844	0	0	0
T99	6002	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275129486	6885	0	0
T15	312433	1056	0	0
T31	100486	235	0	0
T40	26994	0	0	0
T41	93352	0	0	0
T43	0	22	0	0
T49	0	28	0	0
T50	0	42	0	0
T55	0	52	0	0
T56	0	19	0	0
T62	0	39	0	0
T79	0	43	0	0
T82	0	2	0	0
T94	12986	0	0	0
T95	1714	0	0	0
T96	14866	0	0	0
T97	65350	0	0	0
T98	356844	0	0	0
T99	6002	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275129486	7334	0	0
T15	312433	1210	0	0
T31	100486	270	0	0
T40	26994	0	0	0
T41	93352	0	0	0
T43	0	30	0	0
T49	0	55	0	0
T50	0	25	0	0
T55	0	32	0	0
T56	0	13	0	0
T62	0	8	0	0
T79	0	15	0	0
T82	0	17	0	0
T94	12986	0	0	0
T95	1714	0	0	0
T96	14866	0	0	0
T97	65350	0	0	0
T98	356844	0	0	0
T99	6002	0	0	0