| T505 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1809700891 |
|
|
Dec 27 01:00:34 PM PST 23 |
Dec 27 01:00:57 PM PST 23 |
5228348301 ps |
| T506 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3021304239 |
|
|
Dec 27 01:00:29 PM PST 23 |
Dec 27 01:07:56 PM PST 23 |
1969829067 ps |
| T507 |
/workspace/coverage/default/39.sram_ctrl_stress_all.2248200565 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:48:07 PM PST 23 |
29088263522 ps |
| T508 |
/workspace/coverage/default/3.sram_ctrl_executable.1369198710 |
|
|
Dec 27 12:59:33 PM PST 23 |
Dec 27 01:22:56 PM PST 23 |
25752422502 ps |
| T509 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1033964752 |
|
|
Dec 27 12:59:30 PM PST 23 |
Dec 27 01:03:31 PM PST 23 |
9419010279 ps |
| T510 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3988332070 |
|
|
Dec 27 12:59:56 PM PST 23 |
Dec 27 01:08:45 PM PST 23 |
15225188524 ps |
| T511 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1593892081 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:03:03 PM PST 23 |
1589530686 ps |
| T512 |
/workspace/coverage/default/43.sram_ctrl_regwen.860908337 |
|
|
Dec 27 01:01:01 PM PST 23 |
Dec 27 01:23:19 PM PST 23 |
21468499401 ps |
| T513 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.1087109030 |
|
|
Dec 27 01:00:31 PM PST 23 |
Dec 27 01:00:43 PM PST 23 |
2336064334 ps |
| T514 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4116125977 |
|
|
Dec 27 12:59:56 PM PST 23 |
Dec 27 01:06:07 PM PST 23 |
34857819142 ps |
| T515 |
/workspace/coverage/default/40.sram_ctrl_smoke.2233630065 |
|
|
Dec 27 01:00:50 PM PST 23 |
Dec 27 01:02:41 PM PST 23 |
568747373 ps |
| T516 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1530783952 |
|
|
Dec 27 12:59:41 PM PST 23 |
Dec 27 01:03:31 PM PST 23 |
2411811587 ps |
| T517 |
/workspace/coverage/default/45.sram_ctrl_executable.3721723214 |
|
|
Dec 27 01:00:41 PM PST 23 |
Dec 27 01:04:44 PM PST 23 |
6876877735 ps |
| T518 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2767675353 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:03:37 PM PST 23 |
16314425491 ps |
| T519 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2760762849 |
|
|
Dec 27 01:00:43 PM PST 23 |
Dec 27 01:05:56 PM PST 23 |
20509572968 ps |
| T520 |
/workspace/coverage/default/17.sram_ctrl_bijection.1054297601 |
|
|
Dec 27 12:59:54 PM PST 23 |
Dec 27 01:00:58 PM PST 23 |
4366082248 ps |
| T521 |
/workspace/coverage/default/29.sram_ctrl_alert_test.515876775 |
|
|
Dec 27 01:00:22 PM PST 23 |
Dec 27 01:00:27 PM PST 23 |
13156800 ps |
| T522 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1404510767 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:00:40 PM PST 23 |
28310183 ps |
| T523 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3095364443 |
|
|
Dec 27 01:00:41 PM PST 23 |
Dec 27 01:04:46 PM PST 23 |
9793259082 ps |
| T524 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1566003951 |
|
|
Dec 27 12:59:40 PM PST 23 |
Dec 27 01:04:08 PM PST 23 |
5799482044 ps |
| T525 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.724132909 |
|
|
Dec 27 01:00:41 PM PST 23 |
Dec 27 01:00:54 PM PST 23 |
83824717 ps |
| T25 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2560121242 |
|
|
Dec 27 12:59:15 PM PST 23 |
Dec 27 12:59:30 PM PST 23 |
1001973085 ps |
| T526 |
/workspace/coverage/default/20.sram_ctrl_smoke.2229690031 |
|
|
Dec 27 12:59:59 PM PST 23 |
Dec 27 01:00:04 PM PST 23 |
333577227 ps |
| T527 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1836277552 |
|
|
Dec 27 12:59:48 PM PST 23 |
Dec 27 01:06:00 PM PST 23 |
16724198344 ps |
| T528 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.2030386557 |
|
|
Dec 27 01:00:29 PM PST 23 |
Dec 27 01:00:36 PM PST 23 |
131520879 ps |
| T529 |
/workspace/coverage/default/31.sram_ctrl_partial_access.826456267 |
|
|
Dec 27 01:00:16 PM PST 23 |
Dec 27 01:00:30 PM PST 23 |
822655458 ps |
| T530 |
/workspace/coverage/default/34.sram_ctrl_stress_all.97197732 |
|
|
Dec 27 01:00:22 PM PST 23 |
Dec 27 01:36:06 PM PST 23 |
11882494725 ps |
| T531 |
/workspace/coverage/default/29.sram_ctrl_regwen.1312366471 |
|
|
Dec 27 01:00:13 PM PST 23 |
Dec 27 01:07:15 PM PST 23 |
1310162261 ps |
| T532 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.952531825 |
|
|
Dec 27 12:59:54 PM PST 23 |
Dec 27 01:00:01 PM PST 23 |
49582104 ps |
| T533 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.2246751586 |
|
|
Dec 27 01:00:12 PM PST 23 |
Dec 27 01:14:38 PM PST 23 |
11210390073 ps |
| T534 |
/workspace/coverage/default/1.sram_ctrl_regwen.2594714624 |
|
|
Dec 27 12:59:03 PM PST 23 |
Dec 27 01:10:41 PM PST 23 |
1485090950 ps |
| T535 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1525427550 |
|
|
Dec 27 12:59:21 PM PST 23 |
Dec 27 12:59:37 PM PST 23 |
613006528 ps |
| T536 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.4255427708 |
|
|
Dec 27 01:00:36 PM PST 23 |
Dec 27 01:00:43 PM PST 23 |
68570992 ps |
| T537 |
/workspace/coverage/default/30.sram_ctrl_executable.1220433568 |
|
|
Dec 27 01:00:27 PM PST 23 |
Dec 27 01:18:14 PM PST 23 |
4847539284 ps |
| T538 |
/workspace/coverage/default/24.sram_ctrl_executable.4133937320 |
|
|
Dec 27 01:00:36 PM PST 23 |
Dec 27 01:09:11 PM PST 23 |
100325713732 ps |
| T539 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.272928006 |
|
|
Dec 27 12:59:32 PM PST 23 |
Dec 27 12:59:49 PM PST 23 |
396893736 ps |
| T540 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3425936986 |
|
|
Dec 27 12:59:32 PM PST 23 |
Dec 27 12:59:47 PM PST 23 |
587078398 ps |
| T541 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2929532687 |
|
|
Dec 27 12:59:16 PM PST 23 |
Dec 27 12:59:28 PM PST 23 |
15288157 ps |
| T542 |
/workspace/coverage/default/34.sram_ctrl_smoke.3520136095 |
|
|
Dec 27 01:00:21 PM PST 23 |
Dec 27 01:00:57 PM PST 23 |
239905095 ps |
| T543 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2327354448 |
|
|
Dec 27 01:00:25 PM PST 23 |
Dec 27 01:00:36 PM PST 23 |
387628898 ps |
| T544 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2245268524 |
|
|
Dec 27 01:00:41 PM PST 23 |
Dec 27 01:00:55 PM PST 23 |
103037456 ps |
| T545 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2722862076 |
|
|
Dec 27 12:59:51 PM PST 23 |
Dec 27 01:01:45 PM PST 23 |
144666081 ps |
| T546 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3440528788 |
|
|
Dec 27 12:59:36 PM PST 23 |
Dec 27 01:44:39 PM PST 23 |
1602652942 ps |
| T547 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2857653995 |
|
|
Dec 27 12:59:53 PM PST 23 |
Dec 27 01:39:40 PM PST 23 |
3048544738 ps |
| T548 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1213779490 |
|
|
Dec 27 01:00:41 PM PST 23 |
Dec 27 01:14:34 PM PST 23 |
4613851572 ps |
| T549 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3504672751 |
|
|
Dec 27 12:59:19 PM PST 23 |
Dec 27 12:59:44 PM PST 23 |
3086698475 ps |
| T550 |
/workspace/coverage/default/21.sram_ctrl_bijection.2706191760 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:01:25 PM PST 23 |
2818233966 ps |
| T551 |
/workspace/coverage/default/25.sram_ctrl_stress_all.2391223520 |
|
|
Dec 27 01:00:05 PM PST 23 |
Dec 27 01:13:05 PM PST 23 |
27039638918 ps |
| T552 |
/workspace/coverage/default/29.sram_ctrl_smoke.4134210903 |
|
|
Dec 27 01:00:28 PM PST 23 |
Dec 27 01:00:41 PM PST 23 |
336655621 ps |
| T553 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2654632247 |
|
|
Dec 27 01:00:55 PM PST 23 |
Dec 27 01:01:03 PM PST 23 |
136021815 ps |
| T554 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3544930925 |
|
|
Dec 27 12:59:30 PM PST 23 |
Dec 27 12:59:45 PM PST 23 |
657442355 ps |
| T555 |
/workspace/coverage/default/40.sram_ctrl_regwen.1180878262 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 01:08:10 PM PST 23 |
8178762377 ps |
| T556 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3195450950 |
|
|
Dec 27 12:59:56 PM PST 23 |
Dec 27 01:00:13 PM PST 23 |
1095144328 ps |
| T557 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.2458260221 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 01:00:54 PM PST 23 |
3634345545 ps |
| T26 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.4098154857 |
|
|
Dec 27 12:59:46 PM PST 23 |
Dec 27 12:59:50 PM PST 23 |
174191271 ps |
| T558 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2587493544 |
|
|
Dec 27 01:00:05 PM PST 23 |
Dec 27 01:05:32 PM PST 23 |
12489907313 ps |
| T559 |
/workspace/coverage/default/38.sram_ctrl_bijection.1359715898 |
|
|
Dec 27 01:00:39 PM PST 23 |
Dec 27 01:01:50 PM PST 23 |
11579573461 ps |
| T560 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.532061305 |
|
|
Dec 27 01:00:01 PM PST 23 |
Dec 27 01:00:08 PM PST 23 |
291380217 ps |
| T561 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.3081712773 |
|
|
Dec 27 01:00:23 PM PST 23 |
Dec 27 01:00:45 PM PST 23 |
2152598327 ps |
| T562 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2773710049 |
|
|
Dec 27 01:00:11 PM PST 23 |
Dec 27 01:00:25 PM PST 23 |
2741310268 ps |
| T563 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3595923740 |
|
|
Dec 27 01:00:29 PM PST 23 |
Dec 27 01:00:54 PM PST 23 |
6143326189 ps |
| T564 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1883242945 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 01:04:28 PM PST 23 |
11644898376 ps |
| T565 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3480151182 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 01:01:28 PM PST 23 |
103896037 ps |
| T566 |
/workspace/coverage/default/2.sram_ctrl_bijection.1293631324 |
|
|
Dec 27 12:59:19 PM PST 23 |
Dec 27 01:00:43 PM PST 23 |
1295623223 ps |
| T567 |
/workspace/coverage/default/25.sram_ctrl_partial_access.2456394629 |
|
|
Dec 27 01:00:22 PM PST 23 |
Dec 27 01:02:41 PM PST 23 |
764548114 ps |
| T568 |
/workspace/coverage/default/48.sram_ctrl_smoke.936452860 |
|
|
Dec 27 01:00:50 PM PST 23 |
Dec 27 01:01:22 PM PST 23 |
352082892 ps |
| T569 |
/workspace/coverage/default/26.sram_ctrl_bijection.1932719633 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:01:21 PM PST 23 |
2636425292 ps |
| T570 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3313869501 |
|
|
Dec 27 12:59:14 PM PST 23 |
Dec 27 01:52:50 PM PST 23 |
792181526 ps |
| T571 |
/workspace/coverage/default/40.sram_ctrl_bijection.1061945201 |
|
|
Dec 27 01:00:34 PM PST 23 |
Dec 27 01:01:03 PM PST 23 |
6149623861 ps |
| T572 |
/workspace/coverage/default/49.sram_ctrl_regwen.3828736259 |
|
|
Dec 27 01:00:46 PM PST 23 |
Dec 27 01:22:40 PM PST 23 |
11122774956 ps |
| T573 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.610964662 |
|
|
Dec 27 01:00:05 PM PST 23 |
Dec 27 01:19:37 PM PST 23 |
587461408 ps |
| T574 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.846969882 |
|
|
Dec 27 01:00:34 PM PST 23 |
Dec 27 01:20:18 PM PST 23 |
17738592486 ps |
| T575 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.928246745 |
|
|
Dec 27 12:59:28 PM PST 23 |
Dec 27 01:01:21 PM PST 23 |
118689437 ps |
| T576 |
/workspace/coverage/default/10.sram_ctrl_bijection.3205704778 |
|
|
Dec 27 12:59:32 PM PST 23 |
Dec 27 01:00:32 PM PST 23 |
11071954589 ps |
| T577 |
/workspace/coverage/default/38.sram_ctrl_partial_access.1053640814 |
|
|
Dec 27 01:00:25 PM PST 23 |
Dec 27 01:00:51 PM PST 23 |
4332694420 ps |
| T578 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1045583843 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 02:06:43 PM PST 23 |
1057965918 ps |
| T579 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3197838449 |
|
|
Dec 27 12:59:51 PM PST 23 |
Dec 27 12:59:54 PM PST 23 |
87701547 ps |
| T580 |
/workspace/coverage/default/12.sram_ctrl_stress_all.4053616679 |
|
|
Dec 27 12:59:45 PM PST 23 |
Dec 27 02:01:33 PM PST 23 |
47517816285 ps |
| T581 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2229287443 |
|
|
Dec 27 01:02:15 PM PST 23 |
Dec 27 01:02:18 PM PST 23 |
81303545 ps |
| T582 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3248821665 |
|
|
Dec 27 01:01:01 PM PST 23 |
Dec 27 01:05:47 PM PST 23 |
11497894393 ps |
| T583 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2121761106 |
|
|
Dec 27 01:00:41 PM PST 23 |
Dec 27 01:01:06 PM PST 23 |
1320221115 ps |
| T584 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3539419832 |
|
|
Dec 27 01:00:59 PM PST 23 |
Dec 27 01:01:07 PM PST 23 |
274823004 ps |
| T585 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3685155164 |
|
|
Dec 27 12:59:23 PM PST 23 |
Dec 27 01:05:22 PM PST 23 |
15666728399 ps |
| T586 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1217345407 |
|
|
Dec 27 01:00:34 PM PST 23 |
Dec 27 01:16:36 PM PST 23 |
10183371150 ps |
| T587 |
/workspace/coverage/default/44.sram_ctrl_bijection.630849716 |
|
|
Dec 27 01:00:29 PM PST 23 |
Dec 27 01:00:57 PM PST 23 |
1078690155 ps |
| T588 |
/workspace/coverage/default/39.sram_ctrl_partial_access.1925105192 |
|
|
Dec 27 01:00:35 PM PST 23 |
Dec 27 01:00:45 PM PST 23 |
53930623 ps |
| T589 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.545439235 |
|
|
Dec 27 01:00:45 PM PST 23 |
Dec 27 01:00:59 PM PST 23 |
679799246 ps |
| T590 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3499791723 |
|
|
Dec 27 01:00:29 PM PST 23 |
Dec 27 01:17:19 PM PST 23 |
3741205897 ps |
| T591 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3781626784 |
|
|
Dec 27 01:00:35 PM PST 23 |
Dec 27 01:27:17 PM PST 23 |
1251762626 ps |
| T592 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2521162775 |
|
|
Dec 27 12:59:14 PM PST 23 |
Dec 27 12:59:58 PM PST 23 |
110363282 ps |
| T593 |
/workspace/coverage/default/10.sram_ctrl_smoke.1853954450 |
|
|
Dec 27 12:59:35 PM PST 23 |
Dec 27 12:59:48 PM PST 23 |
130401130 ps |
| T594 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1814310282 |
|
|
Dec 27 01:00:30 PM PST 23 |
Dec 27 01:05:00 PM PST 23 |
5738443417 ps |
| T595 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1693458119 |
|
|
Dec 27 01:00:35 PM PST 23 |
Dec 27 01:01:39 PM PST 23 |
330602256 ps |
| T596 |
/workspace/coverage/default/4.sram_ctrl_alert_test.136224228 |
|
|
Dec 27 12:58:59 PM PST 23 |
Dec 27 12:59:08 PM PST 23 |
13116497 ps |
| T597 |
/workspace/coverage/default/28.sram_ctrl_regwen.1081857932 |
|
|
Dec 27 01:00:30 PM PST 23 |
Dec 27 01:07:49 PM PST 23 |
11452239174 ps |
| T598 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2584781574 |
|
|
Dec 27 12:59:14 PM PST 23 |
Dec 27 12:59:38 PM PST 23 |
281121862 ps |
| T599 |
/workspace/coverage/default/24.sram_ctrl_bijection.1993180801 |
|
|
Dec 27 01:00:19 PM PST 23 |
Dec 27 01:00:56 PM PST 23 |
525534823 ps |
| T600 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1862455574 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:00:37 PM PST 23 |
63862314 ps |
| T601 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1630881212 |
|
|
Dec 27 12:59:08 PM PST 23 |
Dec 27 12:59:34 PM PST 23 |
140671054 ps |
| T602 |
/workspace/coverage/default/22.sram_ctrl_regwen.2671274745 |
|
|
Dec 27 12:59:51 PM PST 23 |
Dec 27 01:10:28 PM PST 23 |
12541802892 ps |
| T603 |
/workspace/coverage/default/5.sram_ctrl_smoke.1641554998 |
|
|
Dec 27 12:59:19 PM PST 23 |
Dec 27 01:00:24 PM PST 23 |
103411406 ps |
| T604 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3962238180 |
|
|
Dec 27 12:59:14 PM PST 23 |
Dec 27 12:59:30 PM PST 23 |
116869670 ps |
| T605 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1837714698 |
|
|
Dec 27 12:59:23 PM PST 23 |
Dec 27 01:04:53 PM PST 23 |
3313167072 ps |
| T606 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.4207114077 |
|
|
Dec 27 01:00:01 PM PST 23 |
Dec 27 01:00:13 PM PST 23 |
2744805503 ps |
| T607 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3144082309 |
|
|
Dec 27 01:00:17 PM PST 23 |
Dec 27 01:00:32 PM PST 23 |
1926361993 ps |
| T608 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3140855875 |
|
|
Dec 27 01:00:13 PM PST 23 |
Dec 27 02:06:05 PM PST 23 |
2565163194 ps |
| T609 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1498156157 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:21:17 PM PST 23 |
80200608165 ps |
| T610 |
/workspace/coverage/default/26.sram_ctrl_stress_all.1477349886 |
|
|
Dec 27 01:00:39 PM PST 23 |
Dec 27 01:40:20 PM PST 23 |
69097141022 ps |
| T611 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.3008528034 |
|
|
Dec 27 01:00:21 PM PST 23 |
Dec 27 01:18:46 PM PST 23 |
15238378150 ps |
| T612 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2459269706 |
|
|
Dec 27 01:00:31 PM PST 23 |
Dec 27 01:00:42 PM PST 23 |
155071706 ps |
| T613 |
/workspace/coverage/default/23.sram_ctrl_alert_test.4182013396 |
|
|
Dec 27 01:00:16 PM PST 23 |
Dec 27 01:00:19 PM PST 23 |
12161578 ps |
| T614 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.1848584295 |
|
|
Dec 27 01:00:25 PM PST 23 |
Dec 27 01:02:47 PM PST 23 |
258732408 ps |
| T615 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.1588585434 |
|
|
Dec 27 01:00:46 PM PST 23 |
Dec 27 01:02:54 PM PST 23 |
125074265 ps |
| T616 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3491678904 |
|
|
Dec 27 12:59:29 PM PST 23 |
Dec 27 12:59:40 PM PST 23 |
339835274 ps |
| T617 |
/workspace/coverage/default/21.sram_ctrl_smoke.1900643500 |
|
|
Dec 27 12:59:59 PM PST 23 |
Dec 27 01:00:11 PM PST 23 |
156160788 ps |
| T618 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.375286831 |
|
|
Dec 27 01:00:34 PM PST 23 |
Dec 27 01:13:14 PM PST 23 |
7497257171 ps |
| T619 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.825946766 |
|
|
Dec 27 01:00:44 PM PST 23 |
Dec 27 01:11:49 PM PST 23 |
1453832862 ps |
| T620 |
/workspace/coverage/default/35.sram_ctrl_regwen.341861211 |
|
|
Dec 27 01:00:38 PM PST 23 |
Dec 27 01:12:55 PM PST 23 |
7343188503 ps |
| T621 |
/workspace/coverage/default/38.sram_ctrl_regwen.4160086092 |
|
|
Dec 27 01:00:28 PM PST 23 |
Dec 27 01:29:50 PM PST 23 |
8834978049 ps |
| T622 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3741776783 |
|
|
Dec 27 12:59:17 PM PST 23 |
Dec 27 12:59:29 PM PST 23 |
86436160 ps |
| T623 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2908419699 |
|
|
Dec 27 01:00:15 PM PST 23 |
Dec 27 01:58:34 PM PST 23 |
465513685 ps |
| T624 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.4030437417 |
|
|
Dec 27 01:00:23 PM PST 23 |
Dec 27 01:00:39 PM PST 23 |
926625253 ps |
| T625 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2037388310 |
|
|
Dec 27 12:59:42 PM PST 23 |
Dec 27 01:00:22 PM PST 23 |
1999109878 ps |
| T626 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3408553173 |
|
|
Dec 27 12:59:35 PM PST 23 |
Dec 27 01:03:04 PM PST 23 |
8154957338 ps |
| T627 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2860752758 |
|
|
Dec 27 01:00:28 PM PST 23 |
Dec 27 01:02:53 PM PST 23 |
133385803 ps |
| T628 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2538964248 |
|
|
Dec 27 12:59:42 PM PST 23 |
Dec 27 12:59:46 PM PST 23 |
52756124 ps |
| T629 |
/workspace/coverage/default/40.sram_ctrl_alert_test.3121811913 |
|
|
Dec 27 01:00:39 PM PST 23 |
Dec 27 01:00:48 PM PST 23 |
90391021 ps |
| T630 |
/workspace/coverage/default/10.sram_ctrl_stress_all.934807318 |
|
|
Dec 27 12:59:45 PM PST 23 |
Dec 27 01:08:07 PM PST 23 |
8788577748 ps |
| T631 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3968315884 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:04:25 PM PST 23 |
19342518790 ps |
| T632 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.3286829137 |
|
|
Dec 27 01:00:04 PM PST 23 |
Dec 27 01:00:55 PM PST 23 |
389398675 ps |
| T633 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1056522002 |
|
|
Dec 27 01:00:34 PM PST 23 |
Dec 27 01:01:31 PM PST 23 |
447168961 ps |
| T634 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1540469058 |
|
|
Dec 27 12:59:38 PM PST 23 |
Dec 27 01:05:01 PM PST 23 |
1226886878 ps |
| T635 |
/workspace/coverage/default/42.sram_ctrl_bijection.2108307556 |
|
|
Dec 27 01:01:02 PM PST 23 |
Dec 27 01:01:47 PM PST 23 |
2542910412 ps |
| T636 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1113184735 |
|
|
Dec 27 12:59:49 PM PST 23 |
Dec 27 12:59:52 PM PST 23 |
28598771 ps |
| T637 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.4293721234 |
|
|
Dec 27 01:00:18 PM PST 23 |
Dec 27 01:00:27 PM PST 23 |
178082455 ps |
| T638 |
/workspace/coverage/default/3.sram_ctrl_alert_test.3279505895 |
|
|
Dec 27 12:59:18 PM PST 23 |
Dec 27 12:59:29 PM PST 23 |
17362217 ps |
| T639 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2745713440 |
|
|
Dec 27 01:00:38 PM PST 23 |
Dec 27 01:17:32 PM PST 23 |
38712262376 ps |
| T640 |
/workspace/coverage/default/46.sram_ctrl_executable.1331651750 |
|
|
Dec 27 01:02:15 PM PST 23 |
Dec 27 01:07:14 PM PST 23 |
80046556678 ps |
| T641 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1167827588 |
|
|
Dec 27 01:00:38 PM PST 23 |
Dec 27 01:01:54 PM PST 23 |
132268252 ps |
| T642 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.3341680808 |
|
|
Dec 27 01:00:23 PM PST 23 |
Dec 27 01:00:29 PM PST 23 |
35036418 ps |
| T643 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2571407417 |
|
|
Dec 27 01:00:34 PM PST 23 |
Dec 27 01:00:48 PM PST 23 |
83962348 ps |
| T644 |
/workspace/coverage/default/7.sram_ctrl_regwen.3885568700 |
|
|
Dec 27 12:59:16 PM PST 23 |
Dec 27 01:08:57 PM PST 23 |
7314624359 ps |
| T645 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1108976490 |
|
|
Dec 27 12:59:38 PM PST 23 |
Dec 27 01:00:46 PM PST 23 |
132764915 ps |
| T646 |
/workspace/coverage/default/13.sram_ctrl_partial_access.4255604383 |
|
|
Dec 27 01:00:06 PM PST 23 |
Dec 27 01:00:16 PM PST 23 |
1669823760 ps |
| T647 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2224160181 |
|
|
Dec 27 01:01:05 PM PST 23 |
Dec 27 01:01:11 PM PST 23 |
92280224 ps |
| T648 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3517898838 |
|
|
Dec 27 12:59:16 PM PST 23 |
Dec 27 12:59:32 PM PST 23 |
76454925 ps |
| T649 |
/workspace/coverage/default/18.sram_ctrl_alert_test.331482328 |
|
|
Dec 27 01:00:22 PM PST 23 |
Dec 27 01:00:27 PM PST 23 |
20479016 ps |
| T650 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1380042468 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:00:51 PM PST 23 |
295982313 ps |
| T651 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1142666520 |
|
|
Dec 27 01:00:43 PM PST 23 |
Dec 27 01:01:31 PM PST 23 |
223239557 ps |
| T652 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.542424460 |
|
|
Dec 27 01:01:05 PM PST 23 |
Dec 27 01:01:09 PM PST 23 |
355485968 ps |
| T653 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2887032512 |
|
|
Dec 27 12:59:43 PM PST 23 |
Dec 27 12:59:52 PM PST 23 |
338661301 ps |
| T654 |
/workspace/coverage/default/9.sram_ctrl_alert_test.3039559964 |
|
|
Dec 27 12:59:22 PM PST 23 |
Dec 27 12:59:33 PM PST 23 |
19935656 ps |
| T655 |
/workspace/coverage/default/18.sram_ctrl_bijection.2821469854 |
|
|
Dec 27 12:59:43 PM PST 23 |
Dec 27 01:00:48 PM PST 23 |
980166642 ps |
| T656 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1011919259 |
|
|
Dec 27 12:59:15 PM PST 23 |
Dec 27 01:02:58 PM PST 23 |
4280707458 ps |
| T657 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.1467095222 |
|
|
Dec 27 12:59:52 PM PST 23 |
Dec 27 12:59:57 PM PST 23 |
66257274 ps |
| T658 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3965375353 |
|
|
Dec 27 01:01:16 PM PST 23 |
Dec 27 01:08:56 PM PST 23 |
18998430855 ps |
| T659 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1673111314 |
|
|
Dec 27 01:00:07 PM PST 23 |
Dec 27 01:00:15 PM PST 23 |
583726100 ps |
| T660 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2591115619 |
|
|
Dec 27 12:59:35 PM PST 23 |
Dec 27 01:26:35 PM PST 23 |
1242341630 ps |
| T661 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2261970772 |
|
|
Dec 27 12:59:21 PM PST 23 |
Dec 27 01:01:25 PM PST 23 |
834394246 ps |
| T662 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.1004630975 |
|
|
Dec 27 01:00:20 PM PST 23 |
Dec 27 01:02:38 PM PST 23 |
659122990 ps |
| T663 |
/workspace/coverage/default/23.sram_ctrl_executable.604876753 |
|
|
Dec 27 01:00:52 PM PST 23 |
Dec 27 01:03:39 PM PST 23 |
17599523475 ps |
| T664 |
/workspace/coverage/default/12.sram_ctrl_smoke.3370913511 |
|
|
Dec 27 12:59:23 PM PST 23 |
Dec 27 12:59:45 PM PST 23 |
4098802253 ps |
| T665 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.3969769694 |
|
|
Dec 27 01:00:38 PM PST 23 |
Dec 27 01:01:25 PM PST 23 |
385543415 ps |
| T666 |
/workspace/coverage/default/45.sram_ctrl_bijection.1526357032 |
|
|
Dec 27 01:00:36 PM PST 23 |
Dec 27 01:01:13 PM PST 23 |
486386423 ps |
| T667 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3109683206 |
|
|
Dec 27 12:59:42 PM PST 23 |
Dec 27 12:59:49 PM PST 23 |
89964241 ps |
| T668 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.4269173552 |
|
|
Dec 27 12:59:14 PM PST 23 |
Dec 27 01:32:02 PM PST 23 |
17145314730 ps |
| T669 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1427956249 |
|
|
Dec 27 12:59:42 PM PST 23 |
Dec 27 02:12:03 PM PST 23 |
2089514322 ps |
| T670 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3954323977 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 01:07:32 PM PST 23 |
71534083784 ps |
| T671 |
/workspace/coverage/default/7.sram_ctrl_partial_access.4009953617 |
|
|
Dec 27 12:59:30 PM PST 23 |
Dec 27 12:59:44 PM PST 23 |
148144481 ps |
| T672 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2885670598 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:05:02 PM PST 23 |
42603219081 ps |
| T673 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3342178532 |
|
|
Dec 27 12:59:50 PM PST 23 |
Dec 27 01:15:43 PM PST 23 |
2463307881 ps |
| T674 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1549017572 |
|
|
Dec 27 12:59:47 PM PST 23 |
Dec 27 12:59:53 PM PST 23 |
117060116 ps |
| T675 |
/workspace/coverage/default/39.sram_ctrl_smoke.2356222526 |
|
|
Dec 27 01:00:28 PM PST 23 |
Dec 27 01:01:36 PM PST 23 |
2156587717 ps |
| T676 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2830716799 |
|
|
Dec 27 01:00:17 PM PST 23 |
Dec 27 01:00:25 PM PST 23 |
1237544391 ps |
| T677 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3441104378 |
|
|
Dec 27 12:59:35 PM PST 23 |
Dec 27 01:06:11 PM PST 23 |
8033480611 ps |
| T678 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3625004807 |
|
|
Dec 27 01:00:14 PM PST 23 |
Dec 27 01:00:17 PM PST 23 |
34800399 ps |
| T679 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2481157565 |
|
|
Dec 27 01:02:16 PM PST 23 |
Dec 27 01:02:23 PM PST 23 |
1213410751 ps |
| T680 |
/workspace/coverage/default/30.sram_ctrl_smoke.4202922146 |
|
|
Dec 27 01:00:23 PM PST 23 |
Dec 27 01:00:42 PM PST 23 |
223985467 ps |
| T681 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1249812887 |
|
|
Dec 27 12:59:37 PM PST 23 |
Dec 27 01:59:06 PM PST 23 |
636580056 ps |
| T682 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1936764115 |
|
|
Dec 27 01:00:04 PM PST 23 |
Dec 27 01:03:27 PM PST 23 |
11134738526 ps |
| T683 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.3551081573 |
|
|
Dec 27 01:00:11 PM PST 23 |
Dec 27 01:06:01 PM PST 23 |
2072367583 ps |
| T684 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2592946121 |
|
|
Dec 27 12:59:39 PM PST 23 |
Dec 27 01:15:20 PM PST 23 |
43835904256 ps |
| T685 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.818557266 |
|
|
Dec 27 01:00:40 PM PST 23 |
Dec 27 02:03:49 PM PST 23 |
713768434 ps |
| T686 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.3379151205 |
|
|
Dec 27 01:00:13 PM PST 23 |
Dec 27 01:20:31 PM PST 23 |
3080377782 ps |
| T687 |
/workspace/coverage/default/19.sram_ctrl_stress_all.625937853 |
|
|
Dec 27 12:59:59 PM PST 23 |
Dec 27 01:44:56 PM PST 23 |
127602588774 ps |
| T688 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.161438264 |
|
|
Dec 27 01:00:35 PM PST 23 |
Dec 27 01:00:46 PM PST 23 |
250830001 ps |
| T689 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.336984446 |
|
|
Dec 27 01:00:14 PM PST 23 |
Dec 27 01:01:03 PM PST 23 |
434303768 ps |
| T690 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2531268095 |
|
|
Dec 27 12:59:55 PM PST 23 |
Dec 27 01:00:06 PM PST 23 |
1134231693 ps |
| T691 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2456807358 |
|
|
Dec 27 01:00:45 PM PST 23 |
Dec 27 01:01:04 PM PST 23 |
1376809459 ps |
| T692 |
/workspace/coverage/default/34.sram_ctrl_regwen.3599511910 |
|
|
Dec 27 01:00:23 PM PST 23 |
Dec 27 01:04:45 PM PST 23 |
2931657170 ps |
| T693 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.1683361061 |
|
|
Dec 27 01:00:27 PM PST 23 |
Dec 27 01:00:38 PM PST 23 |
236339441 ps |
| T694 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1327182702 |
|
|
Dec 27 01:00:41 PM PST 23 |
Dec 27 01:00:50 PM PST 23 |
30603481 ps |
| T695 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2670162818 |
|
|
Dec 27 12:59:01 PM PST 23 |
Dec 27 01:02:42 PM PST 23 |
2193480164 ps |
| T696 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.4223854939 |
|
|
Dec 27 01:00:38 PM PST 23 |
Dec 27 01:00:56 PM PST 23 |
2095778152 ps |
| T697 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.4242917417 |
|
|
Dec 27 01:00:05 PM PST 23 |
Dec 27 01:00:12 PM PST 23 |
80848616 ps |
| T698 |
/workspace/coverage/default/12.sram_ctrl_bijection.357851183 |
|
|
Dec 27 12:59:57 PM PST 23 |
Dec 27 01:00:40 PM PST 23 |
1927769722 ps |
| T699 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.2490716825 |
|
|
Dec 27 01:00:30 PM PST 23 |
Dec 27 01:00:44 PM PST 23 |
636128421 ps |
| T700 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.827574556 |
|
|
Dec 27 01:00:44 PM PST 23 |
Dec 27 01:00:56 PM PST 23 |
85359528 ps |
| T701 |
/workspace/coverage/default/44.sram_ctrl_regwen.525030602 |
|
|
Dec 27 01:01:06 PM PST 23 |
Dec 27 01:03:22 PM PST 23 |
1453378213 ps |
| T702 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3065821621 |
|
|
Dec 27 12:59:48 PM PST 23 |
Dec 27 12:59:53 PM PST 23 |
67775556 ps |
| T703 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2326164415 |
|
|
Dec 27 01:00:28 PM PST 23 |
Dec 27 01:30:47 PM PST 23 |
362939137 ps |
| T704 |
/workspace/coverage/default/35.sram_ctrl_stress_all.3088933597 |
|
|
Dec 27 01:00:54 PM PST 23 |
Dec 27 01:48:55 PM PST 23 |
80851124478 ps |
| T705 |
/workspace/coverage/default/13.sram_ctrl_bijection.2226373337 |
|
|
Dec 27 12:59:34 PM PST 23 |
Dec 27 01:00:01 PM PST 23 |
1162254626 ps |
| T706 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.83600078 |
|
|
Dec 27 12:59:49 PM PST 23 |
Dec 27 01:07:59 PM PST 23 |
107519269445 ps |
| T707 |
/workspace/coverage/default/25.sram_ctrl_alert_test.1160921277 |
|
|
Dec 27 01:00:21 PM PST 23 |
Dec 27 01:00:24 PM PST 23 |
39641067 ps |
| T708 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.3982615712 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:26:56 PM PST 23 |
20132447884 ps |
| T709 |
/workspace/coverage/default/40.sram_ctrl_partial_access.1397185516 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:01:36 PM PST 23 |
1074355683 ps |
| T710 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2779941782 |
|
|
Dec 27 12:59:45 PM PST 23 |
Dec 27 01:00:00 PM PST 23 |
76983484 ps |
| T711 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2609140742 |
|
|
Dec 27 12:59:43 PM PST 23 |
Dec 27 01:00:19 PM PST 23 |
147376402 ps |
| T712 |
/workspace/coverage/default/28.sram_ctrl_executable.2646835015 |
|
|
Dec 27 01:00:22 PM PST 23 |
Dec 27 01:15:21 PM PST 23 |
12688882712 ps |
| T713 |
/workspace/coverage/default/23.sram_ctrl_stress_all.3143936422 |
|
|
Dec 27 01:00:22 PM PST 23 |
Dec 27 01:16:39 PM PST 23 |
24214050398 ps |
| T714 |
/workspace/coverage/default/47.sram_ctrl_stress_all.2059443148 |
|
|
Dec 27 01:01:07 PM PST 23 |
Dec 27 02:01:58 PM PST 23 |
52139882114 ps |
| T715 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1863111977 |
|
|
Dec 27 12:59:37 PM PST 23 |
Dec 27 12:59:48 PM PST 23 |
185621205 ps |
| T716 |
/workspace/coverage/default/9.sram_ctrl_executable.3146124160 |
|
|
Dec 27 12:59:58 PM PST 23 |
Dec 27 01:18:42 PM PST 23 |
4949240500 ps |
| T717 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2679811525 |
|
|
Dec 27 12:59:50 PM PST 23 |
Dec 27 12:59:59 PM PST 23 |
470326759 ps |
| T718 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.487681691 |
|
|
Dec 27 01:00:57 PM PST 23 |
Dec 27 01:13:14 PM PST 23 |
5416926836 ps |
| T719 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1426128535 |
|
|
Dec 27 01:00:15 PM PST 23 |
Dec 27 01:00:20 PM PST 23 |
80621778 ps |
| T720 |
/workspace/coverage/default/16.sram_ctrl_alert_test.810550094 |
|
|
Dec 27 12:59:59 PM PST 23 |
Dec 27 01:00:01 PM PST 23 |
21233159 ps |
| T721 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.27460174 |
|
|
Dec 27 01:00:21 PM PST 23 |
Dec 27 01:04:40 PM PST 23 |
3606938741 ps |
| T722 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1474159795 |
|
|
Dec 27 01:00:31 PM PST 23 |
Dec 27 01:03:59 PM PST 23 |
4551418689 ps |
| T723 |
/workspace/coverage/default/33.sram_ctrl_regwen.528770958 |
|
|
Dec 27 01:00:55 PM PST 23 |
Dec 27 01:08:25 PM PST 23 |
6916759198 ps |
| T724 |
/workspace/coverage/default/42.sram_ctrl_regwen.979992186 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 01:09:06 PM PST 23 |
5691082860 ps |
| T725 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2479368814 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:22:12 PM PST 23 |
3544104474 ps |
| T726 |
/workspace/coverage/default/39.sram_ctrl_regwen.3189108573 |
|
|
Dec 27 01:01:04 PM PST 23 |
Dec 27 01:11:23 PM PST 23 |
4720680562 ps |
| T727 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1223738 |
|
|
Dec 27 01:00:16 PM PST 23 |
Dec 27 01:51:05 PM PST 23 |
1322330423 ps |
| T728 |
/workspace/coverage/default/12.sram_ctrl_executable.3135641010 |
|
|
Dec 27 12:59:30 PM PST 23 |
Dec 27 01:14:57 PM PST 23 |
42171172744 ps |
| T729 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1115950357 |
|
|
Dec 27 01:00:50 PM PST 23 |
Dec 27 01:05:54 PM PST 23 |
24954580445 ps |
| T730 |
/workspace/coverage/default/17.sram_ctrl_executable.372559606 |
|
|
Dec 27 01:00:21 PM PST 23 |
Dec 27 01:10:35 PM PST 23 |
9317864329 ps |
| T731 |
/workspace/coverage/default/14.sram_ctrl_regwen.392363745 |
|
|
Dec 27 12:59:58 PM PST 23 |
Dec 27 01:11:41 PM PST 23 |
144874737162 ps |
| T732 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1883981752 |
|
|
Dec 27 12:59:11 PM PST 23 |
Dec 27 12:59:31 PM PST 23 |
903961456 ps |
| T733 |
/workspace/coverage/default/7.sram_ctrl_executable.562141915 |
|
|
Dec 27 12:59:28 PM PST 23 |
Dec 27 01:15:54 PM PST 23 |
129783116650 ps |
| T734 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3062918308 |
|
|
Dec 27 01:00:31 PM PST 23 |
Dec 27 01:16:34 PM PST 23 |
1208543323 ps |
| T735 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.9558809 |
|
|
Dec 27 01:00:40 PM PST 23 |
Dec 27 01:10:17 PM PST 23 |
14432637357 ps |
| T736 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.1916975024 |
|
|
Dec 27 01:00:24 PM PST 23 |
Dec 27 01:06:24 PM PST 23 |
6915858423 ps |
| T737 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.150020753 |
|
|
Dec 27 12:59:47 PM PST 23 |
Dec 27 12:59:54 PM PST 23 |
125134886 ps |
| T738 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1934273260 |
|
|
Dec 27 01:00:37 PM PST 23 |
Dec 27 01:00:45 PM PST 23 |
32823832 ps |
| T739 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3286653611 |
|
|
Dec 27 01:00:36 PM PST 23 |
Dec 27 01:00:48 PM PST 23 |
346352286 ps |
| T740 |
/workspace/coverage/default/5.sram_ctrl_executable.703135347 |
|
|
Dec 27 12:59:29 PM PST 23 |
Dec 27 01:01:03 PM PST 23 |
327161410 ps |
| T741 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3286627583 |
|
|
Dec 27 01:00:25 PM PST 23 |
Dec 27 01:00:38 PM PST 23 |
2383379953 ps |
| T742 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.375765531 |
|
|
Dec 27 12:59:49 PM PST 23 |
Dec 27 01:33:50 PM PST 23 |
232022782 ps |
| T743 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1426600134 |
|
|
Dec 27 01:00:09 PM PST 23 |
Dec 27 01:36:27 PM PST 23 |
5486684128 ps |
| T744 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.2220957975 |
|
|
Dec 27 01:00:33 PM PST 23 |
Dec 27 01:00:40 PM PST 23 |
31148553 ps |
| T745 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1317686559 |
|
|
Dec 27 12:59:44 PM PST 23 |
Dec 27 12:59:49 PM PST 23 |
31727452 ps |
| T746 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3209965327 |
|
|
Dec 27 01:00:14 PM PST 23 |
Dec 27 01:00:17 PM PST 23 |
14458634 ps |
| T747 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2463370154 |
|
|
Dec 27 12:59:41 PM PST 23 |
Dec 27 02:01:41 PM PST 23 |
6750345379 ps |
| T748 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2880438501 |
|
|
Dec 27 12:59:05 PM PST 23 |
Dec 27 01:18:03 PM PST 23 |
1674640834 ps |
| T749 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3427489239 |
|
|
Dec 27 01:00:24 PM PST 23 |
Dec 27 01:00:41 PM PST 23 |
167666572 ps |
| T750 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1367946063 |
|
|
Dec 27 12:59:15 PM PST 23 |
Dec 27 01:24:01 PM PST 23 |
10573162976 ps |
| T751 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2001029189 |
|
|
Dec 27 01:00:11 PM PST 23 |
Dec 27 01:00:48 PM PST 23 |
7797941448 ps |
| T752 |
/workspace/coverage/default/23.sram_ctrl_regwen.1406797244 |
|
|
Dec 27 01:00:26 PM PST 23 |
Dec 27 01:19:55 PM PST 23 |
8551837235 ps |