Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151455318	1			T1	129832		T2	8162		T3	11066
instr_valid_dis	119455792	1			T1	129832		T2	8162		T3	11066
instr_en	23114690	1			T4	51002		T5	20250		T6	592450

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10824135	1			T4	64470		T6	71326		T13	26940
sram_ifetch_valid_disable	118205822	1			T1	129832		T2	8162		T3	11066
sram_ifetch_enable	22425361	1			T4	114010		T5	30220		T6	262666

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151455318	1			T1	129832		T2	8162		T3	11066
hw_debug_en_valid_off	115542912	1			T1	129832		T2	8162		T3	11066
hw_debug_en_on	24205639	1			T4	170818		T5	30124		T6	237632

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	118205822	1			T1	129832		T2	8162		T3	11066
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	104551154	1			T1	129832		T2	8162		T3	11066
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10401082	1			T4	25300		T6	258458		T13	32450
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3811757	1			T4	54		T6	29092		T52	30392
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2011254	1			T128	37568		T131	77220		T133	58690
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1355510	1			T6	29092		T52	30392		T130	51064
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4869953	1			T4	41354		T6	42234		T13	26940
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2194351	1			T4	41354		T13	26940		T129	45340
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1796321	1			T6	42234		T7	18598		T52	51168
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10377535	1			T4	83762		T6	16386		T13	32450
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4672423	1			T4	75016		T7	74884		T25	12102
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3992929	1			T4	8746		T6	16386		T13	32450

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8662850	1			T4	25702		T5	20250		T6	262666
lc_exec_en	8958151	1			T4	45702		T5	30124		T6	179012
valid_exec_dis	112221440	1			T1	129832		T2	8162		T3	11066
invalid_exec_dis	33249496	1			T4	178480		T5	30220		T6	333992