| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1858190508 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3713729021 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3102402720 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3947411471 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3726424423 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3048250730 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2831867778 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.90832323 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1594906103 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2479141830 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1928321898 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3949520212 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3106215809 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2763251341 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1665038506 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1340016788 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.756070760 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1334643786 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.440532831 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4042354920 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.529211929 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3146220845 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2538589300 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.458185162 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2796765582 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3087303444 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1374962812 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2385565240 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4106656346 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.769899934 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3567018140 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1207425861 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1072836312 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2990556832 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2741887435 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3381374759 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.950696772 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2026818836 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3298287285 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2663420614 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1060613391 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1311992538 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3548696802 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1134677930 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1860782321 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1618625922 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4119004640 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.612990614 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3266577362 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2639451136 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2419117012 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1919297599 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.210210581 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.492061626 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.259145749 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3593149817 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1232307197 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3976750865 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.845163724 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3426547354 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1962169037 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.422301862 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1494817852 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2507561054 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.884030270 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.361483850 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2457487026 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3231296545 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3843572088 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.665744958 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.246159713 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2294779822 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3168523349 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4275226568 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3349571976 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.861289508 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2295539083 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1419620122 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1754775825 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.161830098 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1223635930 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4033075779 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2144425656 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.37834202 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.128384323 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4265178897 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1178151344 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1864682083 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2732875538 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2452716283 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3550161548 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3946806141 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3008749305 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3948757943 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1901624043 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1324933276 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3054957557 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1102602212 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1260298670 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3709866371 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.326783851 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.651819675 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1818149187 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3177545346 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1511070644 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1903561950 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2089823167 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2409648013 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.375736175 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4116117465 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.667147794 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.308212862 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1744030601 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2725930030 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.294216237 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3959074994 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2408380766 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2877894664 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1328043468 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3892389336 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2824562782 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1621515698 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1391602206 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.473832561 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.870932676 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4059018723 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.981315410 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.271550107 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1737146852 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.936163962 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.3531862132 |
| /workspace/coverage/default/0.sram_ctrl_bijection.3934785309 |
| /workspace/coverage/default/0.sram_ctrl_executable.3777226448 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.3531270233 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.2552700191 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1115597760 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.398289936 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3308990880 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.3776061651 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2675621759 |
| /workspace/coverage/default/0.sram_ctrl_regwen.711820833 |
| /workspace/coverage/default/0.sram_ctrl_smoke.403870730 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.2697745117 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1566531667 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2984167427 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2073970994 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.645867432 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.2671421878 |
| /workspace/coverage/default/1.sram_ctrl_bijection.3289733216 |
| /workspace/coverage/default/1.sram_ctrl_executable.3679372916 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.3127683602 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.2172817877 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.819864409 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.3651384864 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.24541462 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.1776364689 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3122829731 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.3529222639 |
| /workspace/coverage/default/1.sram_ctrl_regwen.2696662594 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.1013268654 |
| /workspace/coverage/default/1.sram_ctrl_smoke.3990784610 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.478564178 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.926201964 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.777216863 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.733142645 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2242239885 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.3043552326 |
| /workspace/coverage/default/10.sram_ctrl_bijection.1348869969 |
| /workspace/coverage/default/10.sram_ctrl_executable.1206064786 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.3048776658 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.155813290 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1076195254 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.2458399965 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.941999534 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.886186442 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2673602674 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.3856822296 |
| /workspace/coverage/default/10.sram_ctrl_regwen.134759997 |
| /workspace/coverage/default/10.sram_ctrl_smoke.4115228680 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.1436079918 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2193127383 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2922049769 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4011504344 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2258937337 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.2848340661 |
| /workspace/coverage/default/11.sram_ctrl_bijection.2488215001 |
| /workspace/coverage/default/11.sram_ctrl_executable.1164455139 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.2781139131 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2340653207 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3836890082 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.526263520 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.3545857433 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.230029231 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2818866173 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.1822090634 |
| /workspace/coverage/default/11.sram_ctrl_regwen.1675425866 |
| /workspace/coverage/default/11.sram_ctrl_smoke.1710401435 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.2706685654 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2222943145 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3200279102 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3758510126 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.4257666568 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.220360149 |
| /workspace/coverage/default/12.sram_ctrl_bijection.3990729603 |
| /workspace/coverage/default/12.sram_ctrl_executable.3399172295 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.3819754508 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.749650254 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2539997682 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.616306602 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.3400199366 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.2978934389 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2619841442 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.4243554228 |
| /workspace/coverage/default/12.sram_ctrl_regwen.2408534240 |
| /workspace/coverage/default/12.sram_ctrl_smoke.2980836137 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.4251809105 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.970239638 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3582369683 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3578346345 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2676662817 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.2279873017 |
| /workspace/coverage/default/13.sram_ctrl_bijection.1401519444 |
| /workspace/coverage/default/13.sram_ctrl_executable.1813763513 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.1165692077 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.3112955496 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1270311076 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.946534839 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.558676983 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.1761348970 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2860448564 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.845078719 |
| /workspace/coverage/default/13.sram_ctrl_regwen.3938375201 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1774882676 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.3165027604 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3857605942 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2333877719 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1895526787 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.338412718 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.3644665143 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2357725828 |
| /workspace/coverage/default/14.sram_ctrl_executable.3312798871 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.1481679503 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2828494873 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.4072901100 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.2126166809 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.2115098130 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.334845960 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2571956700 |
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| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.658554998 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.983586739 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.3379744322 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.3572369555 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1425577545 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.137474831 |
| /workspace/coverage/default/43.sram_ctrl_regwen.1663579204 |
| /workspace/coverage/default/43.sram_ctrl_smoke.276265775 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.466545181 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4261627942 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3102534940 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3611449306 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1577824979 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.1141953817 |
| /workspace/coverage/default/44.sram_ctrl_bijection.2843056693 |
| /workspace/coverage/default/44.sram_ctrl_executable.1923787466 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.3264351202 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.277345832 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.28440455 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.798197598 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.1998902523 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.286563807 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.62563808 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.802561959 |
| /workspace/coverage/default/44.sram_ctrl_regwen.1805974005 |
| /workspace/coverage/default/44.sram_ctrl_smoke.3501669853 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.2504490148 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4111141732 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3475339993 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.518060777 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1632210894 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.3876469361 |
| /workspace/coverage/default/45.sram_ctrl_bijection.3050042556 |
| /workspace/coverage/default/45.sram_ctrl_executable.4096656406 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.611928054 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.282452518 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2416137025 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.701452525 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.1499969703 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.2814584152 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1599744895 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.1208472258 |
| /workspace/coverage/default/45.sram_ctrl_regwen.1797033757 |
| /workspace/coverage/default/45.sram_ctrl_smoke.2938826786 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.3094378944 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2403049423 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3833283705 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1207229887 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1171986292 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.60510833 |
| /workspace/coverage/default/46.sram_ctrl_bijection.2996939740 |
| /workspace/coverage/default/46.sram_ctrl_executable.514744190 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.1481062161 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.2481632712 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.548558557 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.2910576104 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.1676852927 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.3963535039 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2469793271 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.62444047 |
| /workspace/coverage/default/46.sram_ctrl_regwen.3768484617 |
| /workspace/coverage/default/46.sram_ctrl_smoke.3000461139 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2720087647 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2890767878 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3526205655 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.4161885356 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.1162573050 |
| /workspace/coverage/default/47.sram_ctrl_bijection.2056911676 |
| /workspace/coverage/default/47.sram_ctrl_executable.3283751942 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.1990766922 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.3795801942 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.4006768045 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.3950496028 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.864800308 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.738861881 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2816058229 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.534886605 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3804139700 |
| /workspace/coverage/default/47.sram_ctrl_smoke.4266157053 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.1113352352 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1635885112 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1209548039 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3446131346 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3602420176 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.3349804522 |
| /workspace/coverage/default/48.sram_ctrl_bijection.390236260 |
| /workspace/coverage/default/48.sram_ctrl_executable.1618503686 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.1617586618 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2487045553 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.704320053 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.4094830885 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.321241934 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2349099864 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.802184423 |
| /workspace/coverage/default/48.sram_ctrl_regwen.2096953158 |
| /workspace/coverage/default/48.sram_ctrl_smoke.1584457651 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.1332877722 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2294455112 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1531841098 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.740366185 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2458293858 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.241245119 |
| /workspace/coverage/default/49.sram_ctrl_bijection.1258961425 |
| /workspace/coverage/default/49.sram_ctrl_executable.490587716 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.3771950872 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.3907718475 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3298305732 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.2150954989 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.1217791642 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.3422402838 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1650973476 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.582429080 |
| /workspace/coverage/default/49.sram_ctrl_regwen.629127789 |
| /workspace/coverage/default/49.sram_ctrl_smoke.371979704 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.3169690468 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1622908267 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2485279507 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3956635881 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.339370896 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.1624953090 |
| /workspace/coverage/default/5.sram_ctrl_bijection.1589615768 |
| /workspace/coverage/default/5.sram_ctrl_executable.3089383451 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.2667238829 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.752483265 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2983475375 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.3007780714 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.2225613150 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1289293933 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1817848421 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.2684748384 |
| /workspace/coverage/default/5.sram_ctrl_regwen.2939058714 |
| /workspace/coverage/default/5.sram_ctrl_smoke.4106285869 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.3431174919 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3360284101 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3212290655 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4127444154 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.92222487 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.1846135336 |
| /workspace/coverage/default/6.sram_ctrl_bijection.2541081489 |
| /workspace/coverage/default/6.sram_ctrl_executable.1160147602 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.3362202770 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.2897814557 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.968002079 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.2927369050 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.678336059 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.2666510666 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1511350194 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.652382781 |
| /workspace/coverage/default/6.sram_ctrl_regwen.2724438139 |
| /workspace/coverage/default/6.sram_ctrl_smoke.2429850970 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.35989220 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2390935272 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2036212585 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2659673012 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1879118014 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.2332150245 |
| /workspace/coverage/default/7.sram_ctrl_bijection.4054539390 |
| /workspace/coverage/default/7.sram_ctrl_executable.654899037 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.2478260215 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.2716438244 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2592328328 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.3506500710 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1771987528 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.3471903539 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4135920325 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.1910807003 |
| /workspace/coverage/default/7.sram_ctrl_regwen.2018872090 |
| /workspace/coverage/default/7.sram_ctrl_smoke.1051189361 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.902585490 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2971858963 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.434075010 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3942130629 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3430831105 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.4178181634 |
| /workspace/coverage/default/8.sram_ctrl_bijection.3380152420 |
| /workspace/coverage/default/8.sram_ctrl_executable.3890034591 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.3899933550 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.423573520 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2999223352 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.2707958417 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.1992592033 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.2488349016 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4267295214 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.687055220 |
| /workspace/coverage/default/8.sram_ctrl_regwen.187660970 |
| /workspace/coverage/default/8.sram_ctrl_smoke.2889524041 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4155920272 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.4135829814 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3216665070 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1291772877 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.982034642 |
| /workspace/coverage/default/9.sram_ctrl_bijection.2509140940 |
| /workspace/coverage/default/9.sram_ctrl_executable.1065009042 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3119844530 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.4269032029 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.47501562 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.1811797268 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3579740564 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.1972030296 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2583819061 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.1877327397 |
| /workspace/coverage/default/9.sram_ctrl_regwen.2558576877 |
| /workspace/coverage/default/9.sram_ctrl_smoke.3917066243 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.3614026672 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3273663129 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1025476753 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1683847379 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/33.sram_ctrl_stress_all.3010080685 |
|
|
Dec 31 12:28:46 PM PST 23 |
Dec 31 01:15:08 PM PST 23 |
97581214186 ps |
| T2 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1150997424 |
|
|
Dec 31 12:28:35 PM PST 23 |
Dec 31 12:28:58 PM PST 23 |
565426423 ps |
| T3 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1655989127 |
|
|
Dec 31 12:29:20 PM PST 23 |
Dec 31 12:29:50 PM PST 23 |
136320269 ps |
| T4 |
/workspace/coverage/default/32.sram_ctrl_executable.2732020562 |
|
|
Dec 31 12:28:59 PM PST 23 |
Dec 31 12:39:10 PM PST 23 |
27504463137 ps |
| T5 |
/workspace/coverage/default/5.sram_ctrl_regwen.2939058714 |
|
|
Dec 31 12:27:52 PM PST 23 |
Dec 31 12:29:07 PM PST 23 |
4280728903 ps |
| T8 |
/workspace/coverage/default/4.sram_ctrl_bijection.1578580274 |
|
|
Dec 31 12:27:46 PM PST 23 |
Dec 31 12:28:07 PM PST 23 |
1480426420 ps |
| T9 |
/workspace/coverage/default/25.sram_ctrl_bijection.3329194584 |
|
|
Dec 31 12:28:29 PM PST 23 |
Dec 31 12:29:21 PM PST 23 |
692502803 ps |
| T10 |
/workspace/coverage/default/49.sram_ctrl_bijection.1258961425 |
|
|
Dec 31 12:29:27 PM PST 23 |
Dec 31 12:30:36 PM PST 23 |
1839196588 ps |
| T6 |
/workspace/coverage/default/20.sram_ctrl_stress_all.3042678682 |
|
|
Dec 31 12:27:44 PM PST 23 |
Dec 31 01:02:02 PM PST 23 |
33771574371 ps |
| T11 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.2458399965 |
|
|
Dec 31 12:30:06 PM PST 23 |
Dec 31 12:30:19 PM PST 23 |
687435482 ps |
| T19 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3330570708 |
|
|
Dec 31 12:28:37 PM PST 23 |
Dec 31 12:28:47 PM PST 23 |
44396368 ps |
| T12 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2761918225 |
|
|
Dec 31 12:29:44 PM PST 23 |
Dec 31 12:34:02 PM PST 23 |
45082869085 ps |
| T13 |
/workspace/coverage/default/15.sram_ctrl_executable.4254628539 |
|
|
Dec 31 12:28:41 PM PST 23 |
Dec 31 12:42:25 PM PST 23 |
8070566608 ps |
| T14 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2072314702 |
|
|
Dec 31 12:30:38 PM PST 23 |
Dec 31 12:38:30 PM PST 23 |
4175610156 ps |
| T15 |
/workspace/coverage/default/24.sram_ctrl_partial_access.4192652877 |
|
|
Dec 31 12:30:44 PM PST 23 |
Dec 31 12:32:28 PM PST 23 |
208445713 ps |
| T20 |
/workspace/coverage/default/41.sram_ctrl_alert_test.328158181 |
|
|
Dec 31 12:29:03 PM PST 23 |
Dec 31 12:29:12 PM PST 23 |
13865818 ps |
| T29 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2849590829 |
|
|
Dec 31 12:28:54 PM PST 23 |
Dec 31 12:29:00 PM PST 23 |
78034935 ps |
| T70 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.209346692 |
|
|
Dec 31 12:28:29 PM PST 23 |
Dec 31 12:28:43 PM PST 23 |
54005488 ps |
| T78 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1771987528 |
|
|
Dec 31 12:29:35 PM PST 23 |
Dec 31 12:34:44 PM PST 23 |
21146075971 ps |
| T71 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3149353159 |
|
|
Dec 31 12:28:28 PM PST 23 |
Dec 31 12:38:02 PM PST 23 |
36897151233 ps |
| T30 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.62444047 |
|
|
Dec 31 12:29:03 PM PST 23 |
Dec 31 12:29:18 PM PST 23 |
128542539 ps |
| T7 |
/workspace/coverage/default/11.sram_ctrl_stress_all.2706685654 |
|
|
Dec 31 12:28:09 PM PST 23 |
Dec 31 12:44:33 PM PST 23 |
29058385444 ps |
| T72 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3836890082 |
|
|
Dec 31 12:29:30 PM PST 23 |
Dec 31 12:29:36 PM PST 23 |
53743522 ps |
| T21 |
/workspace/coverage/default/40.sram_ctrl_alert_test.4169705577 |
|
|
Dec 31 12:28:46 PM PST 23 |
Dec 31 12:28:53 PM PST 23 |
14147181 ps |
| T79 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4135920325 |
|
|
Dec 31 12:28:28 PM PST 23 |
Dec 31 12:34:51 PM PST 23 |
195114213311 ps |
| T73 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.1285854193 |
|
|
Dec 31 12:30:25 PM PST 23 |
Dec 31 12:35:27 PM PST 23 |
11390841603 ps |
| T80 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2272402995 |
|
|
Dec 31 12:28:51 PM PST 23 |
Dec 31 12:29:06 PM PST 23 |
456079023 ps |
| T81 |
/workspace/coverage/default/41.sram_ctrl_bijection.516740726 |
|
|
Dec 31 12:30:51 PM PST 23 |
Dec 31 12:32:00 PM PST 23 |
8670176561 ps |
| T82 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2739021134 |
|
|
Dec 31 12:29:34 PM PST 23 |
Dec 31 12:31:14 PM PST 23 |
614521789 ps |
| T134 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.2312911201 |
|
|
Dec 31 12:30:08 PM PST 23 |
Dec 31 12:30:26 PM PST 23 |
76698632 ps |
| T31 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2933176865 |
|
|
Dec 31 12:28:08 PM PST 23 |
Dec 31 12:28:12 PM PST 23 |
72532292 ps |
| T27 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3360284101 |
|
|
Dec 31 12:27:32 PM PST 23 |
Dec 31 01:10:46 PM PST 23 |
1365047254 ps |
| T52 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2697745117 |
|
|
Dec 31 12:28:06 PM PST 23 |
Dec 31 12:41:59 PM PST 23 |
45233884216 ps |
| T53 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1569574389 |
|
|
Dec 31 12:27:49 PM PST 23 |
Dec 31 12:27:51 PM PST 23 |
81725089 ps |
| T54 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1748297493 |
|
|
Dec 31 12:28:49 PM PST 23 |
Dec 31 12:33:09 PM PST 23 |
10444811073 ps |
| T25 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1915745514 |
|
|
Dec 31 12:28:19 PM PST 23 |
Dec 31 01:16:39 PM PST 23 |
783697977 ps |
| T55 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.2359075184 |
|
|
Dec 31 12:29:09 PM PST 23 |
Dec 31 12:30:03 PM PST 23 |
460598765 ps |
| T56 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1499969703 |
|
|
Dec 31 12:29:12 PM PST 23 |
Dec 31 12:30:02 PM PST 23 |
585557315 ps |
| T57 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1150160932 |
|
|
Dec 31 12:28:51 PM PST 23 |
Dec 31 12:40:15 PM PST 23 |
107690359220 ps |
| T58 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.4094830885 |
|
|
Dec 31 12:28:58 PM PST 23 |
Dec 31 12:48:10 PM PST 23 |
26286907067 ps |
| T135 |
/workspace/coverage/default/7.sram_ctrl_partial_access.3471903539 |
|
|
Dec 31 12:28:04 PM PST 23 |
Dec 31 12:28:26 PM PST 23 |
275601680 ps |
| T136 |
/workspace/coverage/default/27.sram_ctrl_alert_test.3807175106 |
|
|
Dec 31 12:29:19 PM PST 23 |
Dec 31 12:29:23 PM PST 23 |
26227689 ps |
| T128 |
/workspace/coverage/default/44.sram_ctrl_stress_all.2504490148 |
|
|
Dec 31 12:29:06 PM PST 23 |
Dec 31 01:19:32 PM PST 23 |
22842436215 ps |
| T127 |
/workspace/coverage/default/23.sram_ctrl_regwen.4148454120 |
|
|
Dec 31 12:28:39 PM PST 23 |
Dec 31 12:39:02 PM PST 23 |
2685317294 ps |
| T129 |
/workspace/coverage/default/20.sram_ctrl_executable.2727919232 |
|
|
Dec 31 12:28:51 PM PST 23 |
Dec 31 12:40:16 PM PST 23 |
47683478731 ps |
| T137 |
/workspace/coverage/default/34.sram_ctrl_bijection.4082028830 |
|
|
Dec 31 12:28:48 PM PST 23 |
Dec 31 12:29:50 PM PST 23 |
7113175638 ps |
| T138 |
/workspace/coverage/default/47.sram_ctrl_partial_access.738861881 |
|
|
Dec 31 12:30:02 PM PST 23 |
Dec 31 12:32:13 PM PST 23 |
1287327757 ps |
| T139 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1098631466 |
|
|
Dec 31 12:29:18 PM PST 23 |
Dec 31 12:29:23 PM PST 23 |
44115103 ps |
| T107 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.390921802 |
|
|
Dec 31 12:30:37 PM PST 23 |
Dec 31 12:34:18 PM PST 23 |
3279245543 ps |
| T140 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.398289936 |
|
|
Dec 31 12:27:53 PM PST 23 |
Dec 31 12:28:04 PM PST 23 |
346406251 ps |
| T108 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2469793271 |
|
|
Dec 31 12:30:31 PM PST 23 |
Dec 31 12:34:10 PM PST 23 |
6295649677 ps |
| T141 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2842180129 |
|
|
Dec 31 12:28:36 PM PST 23 |
Dec 31 12:30:26 PM PST 23 |
154929703 ps |
| T142 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2828494873 |
|
|
Dec 31 12:27:54 PM PST 23 |
Dec 31 12:28:12 PM PST 23 |
253963879 ps |
| T143 |
/workspace/coverage/default/13.sram_ctrl_bijection.1401519444 |
|
|
Dec 31 12:28:18 PM PST 23 |
Dec 31 12:29:36 PM PST 23 |
4980178266 ps |
| T144 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.3795801942 |
|
|
Dec 31 12:29:33 PM PST 23 |
Dec 31 12:29:40 PM PST 23 |
52473982 ps |
| T130 |
/workspace/coverage/default/46.sram_ctrl_regwen.3768484617 |
|
|
Dec 31 12:30:40 PM PST 23 |
Dec 31 12:37:37 PM PST 23 |
9834260406 ps |
| T145 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2139373388 |
|
|
Dec 31 12:28:31 PM PST 23 |
Dec 31 12:28:41 PM PST 23 |
83625479 ps |
| T146 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.802184423 |
|
|
Dec 31 12:29:23 PM PST 23 |
Dec 31 12:29:25 PM PST 23 |
27523464 ps |
| T109 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2860448564 |
|
|
Dec 31 12:27:47 PM PST 23 |
Dec 31 12:35:26 PM PST 23 |
37768094714 ps |
| T147 |
/workspace/coverage/default/9.sram_ctrl_partial_access.1972030296 |
|
|
Dec 31 12:27:54 PM PST 23 |
Dec 31 12:28:12 PM PST 23 |
877319727 ps |
| T148 |
/workspace/coverage/default/40.sram_ctrl_bijection.2315248132 |
|
|
Dec 31 12:29:27 PM PST 23 |
Dec 31 12:30:26 PM PST 23 |
7944953639 ps |
| T131 |
/workspace/coverage/default/11.sram_ctrl_executable.1164455139 |
|
|
Dec 31 12:27:54 PM PST 23 |
Dec 31 12:36:17 PM PST 23 |
21320515847 ps |
| T132 |
/workspace/coverage/default/47.sram_ctrl_executable.3283751942 |
|
|
Dec 31 12:29:12 PM PST 23 |
Dec 31 12:45:38 PM PST 23 |
36483520504 ps |
| T149 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.1422466206 |
|
|
Dec 31 12:30:14 PM PST 23 |
Dec 31 12:30:24 PM PST 23 |
346823214 ps |
| T150 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3048776658 |
|
|
Dec 31 12:30:05 PM PST 23 |
Dec 31 12:30:17 PM PST 23 |
1126654129 ps |
| T151 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3463830018 |
|
|
Dec 31 12:28:53 PM PST 23 |
Dec 31 12:29:50 PM PST 23 |
137994238 ps |
| T116 |
/workspace/coverage/default/37.sram_ctrl_stress_all.264763916 |
|
|
Dec 31 12:28:50 PM PST 23 |
Dec 31 01:33:18 PM PST 23 |
270996090693 ps |
| T86 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2628430838 |
|
|
Dec 31 12:28:10 PM PST 23 |
Dec 31 12:28:15 PM PST 23 |
163488265 ps |
| T152 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3349804522 |
|
|
Dec 31 12:30:35 PM PST 23 |
Dec 31 12:30:40 PM PST 23 |
73448429 ps |
| T133 |
/workspace/coverage/default/33.sram_ctrl_executable.1619380600 |
|
|
Dec 31 12:29:02 PM PST 23 |
Dec 31 12:47:15 PM PST 23 |
3476427703 ps |
| T153 |
/workspace/coverage/default/29.sram_ctrl_executable.4193798140 |
|
|
Dec 31 12:29:01 PM PST 23 |
Dec 31 12:31:15 PM PST 23 |
12700198898 ps |
| T154 |
/workspace/coverage/default/48.sram_ctrl_bijection.390236260 |
|
|
Dec 31 12:29:17 PM PST 23 |
Dec 31 12:29:48 PM PST 23 |
467741683 ps |
| T26 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3853180007 |
|
|
Dec 31 12:29:21 PM PST 23 |
Dec 31 01:50:50 PM PST 23 |
75440370752 ps |
| T155 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1340221406 |
|
|
Dec 31 12:28:57 PM PST 23 |
Dec 31 12:29:07 PM PST 23 |
1097877094 ps |
| T156 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1895526787 |
|
|
Dec 31 12:28:45 PM PST 23 |
Dec 31 12:29:56 PM PST 23 |
659672555 ps |
| T157 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.4259007932 |
|
|
Dec 31 12:27:57 PM PST 23 |
Dec 31 12:28:04 PM PST 23 |
31910028 ps |
| T16 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3223295537 |
|
|
Dec 31 12:29:25 PM PST 23 |
Dec 31 12:37:27 PM PST 23 |
14194222642 ps |
| T158 |
/workspace/coverage/default/10.sram_ctrl_bijection.1348869969 |
|
|
Dec 31 12:30:04 PM PST 23 |
Dec 31 12:31:01 PM PST 23 |
5305999716 ps |
| T159 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2978125178 |
|
|
Dec 31 12:27:55 PM PST 23 |
Dec 31 12:28:04 PM PST 23 |
89434045 ps |
| T160 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.3245715811 |
|
|
Dec 31 12:27:48 PM PST 23 |
Dec 31 12:27:59 PM PST 23 |
455661650 ps |
| T161 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1915507898 |
|
|
Dec 31 12:29:09 PM PST 23 |
Dec 31 12:29:22 PM PST 23 |
495083501 ps |
| T162 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3031057758 |
|
|
Dec 31 12:28:59 PM PST 23 |
Dec 31 01:41:20 PM PST 23 |
116966588288 ps |
| T163 |
/workspace/coverage/default/40.sram_ctrl_partial_access.3814765999 |
|
|
Dec 31 12:28:51 PM PST 23 |
Dec 31 12:29:28 PM PST 23 |
140806695 ps |
| T164 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.704320053 |
|
|
Dec 31 12:30:08 PM PST 23 |
Dec 31 12:30:16 PM PST 23 |
144239173 ps |
| T165 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2478260215 |
|
|
Dec 31 12:27:56 PM PST 23 |
Dec 31 12:28:12 PM PST 23 |
741355064 ps |
| T166 |
/workspace/coverage/default/21.sram_ctrl_smoke.3535198136 |
|
|
Dec 31 12:28:57 PM PST 23 |
Dec 31 12:29:08 PM PST 23 |
570103484 ps |
| T167 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.916919991 |
|
|
Dec 31 12:30:30 PM PST 23 |
Dec 31 12:40:06 PM PST 23 |
2954785506 ps |
| T168 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.749650254 |
|
|
Dec 31 12:29:01 PM PST 23 |
Dec 31 12:30:38 PM PST 23 |
544314185 ps |
| T169 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3094378944 |
|
|
Dec 31 12:30:40 PM PST 23 |
Dec 31 01:50:06 PM PST 23 |
217339441934 ps |
| T170 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3400199366 |
|
|
Dec 31 12:30:29 PM PST 23 |
Dec 31 12:46:09 PM PST 23 |
6238307052 ps |
| T28 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.326783851 |
|
|
Dec 31 12:43:48 PM PST 23 |
Dec 31 12:43:53 PM PST 23 |
795394666 ps |
| T106 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1207425861 |
|
|
Dec 31 12:43:36 PM PST 23 |
Dec 31 12:43:39 PM PST 23 |
32038708 ps |
| T43 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4033075779 |
|
|
Dec 31 12:43:55 PM PST 23 |
Dec 31 12:44:13 PM PST 23 |
478071933 ps |
| T46 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3298287285 |
|
|
Dec 31 12:43:57 PM PST 23 |
Dec 31 12:44:11 PM PST 23 |
182153794 ps |
| T44 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2419117012 |
|
|
Dec 31 12:44:00 PM PST 23 |
Dec 31 12:44:12 PM PST 23 |
241469604 ps |
| T62 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3177545346 |
|
|
Dec 31 12:43:28 PM PST 23 |
Dec 31 12:43:34 PM PST 23 |
1562100445 ps |
| T45 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4161744007 |
|
|
Dec 31 12:43:53 PM PST 23 |
Dec 31 12:44:07 PM PST 23 |
526547316 ps |
| T47 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3946806141 |
|
|
Dec 31 12:43:35 PM PST 23 |
Dec 31 12:43:38 PM PST 23 |
90245457 ps |
| T48 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3231296545 |
|
|
Dec 31 12:43:53 PM PST 23 |
Dec 31 12:44:06 PM PST 23 |
42994084 ps |
| T63 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2725930030 |
|
|
Dec 31 12:43:37 PM PST 23 |
Dec 31 12:43:40 PM PST 23 |
22421909 ps |
| T64 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1665038506 |
|
|
Dec 31 12:43:41 PM PST 23 |
Dec 31 12:43:43 PM PST 23 |
27936319 ps |
| T65 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3381374759 |
|
|
Dec 31 12:43:34 PM PST 23 |
Dec 31 12:43:37 PM PST 23 |
27779986 ps |
| T59 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2144425656 |
|
|
Dec 31 12:43:16 PM PST 23 |
Dec 31 12:43:18 PM PST 23 |
304963785 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.861289508 |
|
|
Dec 31 12:43:33 PM PST 23 |
Dec 31 12:43:36 PM PST 23 |
439397217 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.161830098 |
|
|
Dec 31 12:43:28 PM PST 23 |
Dec 31 12:43:35 PM PST 23 |
790275686 ps |
| T68 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.361483850 |
|
|
Dec 31 12:43:30 PM PST 23 |
Dec 31 12:43:37 PM PST 23 |
420713542 ps |
| T49 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3709866371 |
|
|
Dec 31 12:43:33 PM PST 23 |
Dec 31 12:43:40 PM PST 23 |
249257915 ps |
| T69 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2351417177 |
|
|
Dec 31 12:43:49 PM PST 23 |
Dec 31 12:44:02 PM PST 23 |
4110434930 ps |
| T50 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1860782321 |
|
|
Dec 31 12:43:52 PM PST 23 |
Dec 31 12:44:03 PM PST 23 |
134294909 ps |
| T83 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.210210581 |
|
|
Dec 31 12:44:01 PM PST 23 |
Dec 31 12:44:14 PM PST 23 |
38911195 ps |
| T84 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.128384323 |
|
|
Dec 31 12:43:43 PM PST 23 |
Dec 31 12:43:45 PM PST 23 |
83046543 ps |
| T51 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1903561950 |
|
|
Dec 31 12:43:31 PM PST 23 |
Dec 31 12:43:35 PM PST 23 |
60337743 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2831867778 |
|
|
Dec 31 12:43:30 PM PST 23 |
Dec 31 12:43:33 PM PST 23 |
59223040 ps |
| T74 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.529211929 |
|
|
Dec 31 12:43:48 PM PST 23 |
Dec 31 12:43:51 PM PST 23 |
13690587 ps |
| T85 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2457487026 |
|
|
Dec 31 12:43:51 PM PST 23 |
Dec 31 12:43:55 PM PST 23 |
62723896 ps |
| T61 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.271550107 |
|
|
Dec 31 12:43:37 PM PST 23 |
Dec 31 12:43:43 PM PST 23 |
451122381 ps |
| T101 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3008749305 |
|
|
Dec 31 12:43:18 PM PST 23 |
Dec 31 12:43:19 PM PST 23 |
29785464 ps |
| T111 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1744030601 |
|
|
Dec 31 12:44:03 PM PST 23 |
Dec 31 12:44:15 PM PST 23 |
133694161 ps |
| T75 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3567018140 |
|
|
Dec 31 12:43:31 PM PST 23 |
Dec 31 12:43:44 PM PST 23 |
428857862 ps |
| T171 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2385565240 |
|
|
Dec 31 12:43:47 PM PST 23 |
Dec 31 12:43:50 PM PST 23 |
29432083 ps |
| T172 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1334643786 |
|
|
Dec 31 12:44:00 PM PST 23 |
Dec 31 12:44:10 PM PST 23 |
25804384 ps |
| T76 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3426547354 |
|
|
Dec 31 12:43:39 PM PST 23 |
Dec 31 12:43:47 PM PST 23 |
783941183 ps |
| T77 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2824562782 |
|
|
Dec 31 12:43:14 PM PST 23 |
Dec 31 12:43:24 PM PST 23 |
1521215779 ps |
| T173 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1223635930 |
|
|
Dec 31 12:43:38 PM PST 23 |
Dec 31 12:43:40 PM PST 23 |
69030006 ps |
| T174 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.246159713 |
|
|
Dec 31 12:43:48 PM PST 23 |
Dec 31 12:43:49 PM PST 23 |
10872799 ps |
| T175 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3892389336 |
|
|
Dec 31 12:43:32 PM PST 23 |
Dec 31 12:43:34 PM PST 23 |
44093448 ps |
| T176 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2479141830 |
|
|
Dec 31 12:43:55 PM PST 23 |
Dec 31 12:44:11 PM PST 23 |
415724952 ps |
| T177 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3976750865 |
|
|
Dec 31 12:43:38 PM PST 23 |
Dec 31 12:43:42 PM PST 23 |
54340929 ps |
| T112 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.293667519 |
|
|
Dec 31 12:44:04 PM PST 23 |
Dec 31 12:44:15 PM PST 23 |
316948118 ps |
| T178 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1962169037 |
|
|
Dec 31 12:43:48 PM PST 23 |
Dec 31 12:43:52 PM PST 23 |
22800534 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2452716283 |
|
|
Dec 31 12:43:43 PM PST 23 |
Dec 31 12:43:45 PM PST 23 |
20301736 ps |
| T114 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1919297599 |
|
|
Dec 31 12:43:48 PM PST 23 |
Dec 31 12:43:50 PM PST 23 |
244382965 ps |
| T115 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1311992538 |
|
|
Dec 31 12:43:45 PM PST 23 |
Dec 31 12:43:47 PM PST 23 |
23995895 ps |
| T179 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2294779822 |
|
|
Dec 31 12:43:44 PM PST 23 |
Dec 31 12:43:46 PM PST 23 |
17088343 ps |
| T87 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4042354920 |
|
|
Dec 31 12:43:52 PM PST 23 |
Dec 31 12:44:01 PM PST 23 |
1301731585 ps |
| T180 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1134677930 |
|
|
Dec 31 12:43:35 PM PST 23 |
Dec 31 12:43:38 PM PST 23 |
32781088 ps |
| T181 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3146220845 |
|
|
Dec 31 12:43:34 PM PST 23 |
Dec 31 12:43:39 PM PST 23 |
222508988 ps |
| T182 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3949520212 |
|
|
Dec 31 12:43:21 PM PST 23 |
Dec 31 12:43:23 PM PST 23 |
42664383 ps |
| T183 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2639451136 |
|
|
Dec 31 12:43:18 PM PST 23 |
Dec 31 12:43:23 PM PST 23 |
126351914 ps |
| T88 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.375736175 |
|
|
Dec 31 12:43:35 PM PST 23 |
Dec 31 12:43:40 PM PST 23 |
245637453 ps |
| T184 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3168523349 |
|
|
Dec 31 12:43:47 PM PST 23 |
Dec 31 12:43:51 PM PST 23 |
298135381 ps |
| T185 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3550161548 |
|
|
Dec 31 12:43:37 PM PST 23 |
Dec 31 12:43:41 PM PST 23 |
72695161 ps |
| T117 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2538589300 |
|
|
Dec 31 12:43:40 PM PST 23 |
Dec 31 12:43:43 PM PST 23 |
97995021 ps |
| T121 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.756070760 |
|
|
Dec 31 12:43:05 PM PST 23 |
Dec 31 12:43:07 PM PST 23 |
137655993 ps |
| T122 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2990556832 |
|
|
Dec 31 12:43:41 PM PST 23 |
Dec 31 12:43:44 PM PST 23 |
349834955 ps |
| T125 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.90832323 |
|
|
Dec 31 12:43:33 PM PST 23 |
Dec 31 12:43:37 PM PST 23 |
421851095 ps |
| T186 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.473832561 |
|
|
Dec 31 12:43:40 PM PST 23 |
Dec 31 12:43:44 PM PST 23 |
28565760 ps |
| T187 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2796765582 |
|
|
Dec 31 12:43:52 PM PST 23 |
Dec 31 12:44:01 PM PST 23 |
14562950 ps |
| T188 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.870932676 |
|
|
Dec 31 12:43:35 PM PST 23 |
Dec 31 12:43:37 PM PST 23 |
14104052 ps |
| T126 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2295309843 |
|
|
Dec 31 12:43:30 PM PST 23 |
Dec 31 12:43:34 PM PST 23 |
1051073139 ps |
| T189 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3048250730 |
|
|
Dec 31 12:43:37 PM PST 23 |
Dec 31 12:43:40 PM PST 23 |
56666021 ps |
| T123 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.308212862 |
|
|
Dec 31 12:43:36 PM PST 23 |
Dec 31 12:43:41 PM PST 23 |
1379717510 ps |
| T89 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.884030270 |
|
|
Dec 31 12:43:48 PM PST 23 |
Dec 31 12:43:50 PM PST 23 |
28515673 ps |
| T190 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1178151344 |
|
|
Dec 31 12:43:48 PM PST 23 |
Dec 31 12:43:52 PM PST 23 |
39510512 ps |
| T191 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.981315410 |
|
|
Dec 31 12:43:44 PM PST 23 |
Dec 31 12:43:45 PM PST 23 |
62723776 ps |
| T192 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4116117465 |
|
|
Dec 31 12:43:36 PM PST 23 |
Dec 31 12:43:40 PM PST 23 |
62384841 ps |
| T193 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1419620122 |
|
|
Dec 31 12:43:29 PM PST 23 |
Dec 31 12:43:31 PM PST 23 |
94224122 ps |
| T194 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1594906103 |
|
|
Dec 31 12:43:40 PM PST 23 |
Dec 31 12:43:42 PM PST 23 |
16522384 ps |
| T195 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1391602206 |
|
|
Dec 31 12:44:03 PM PST 23 |
Dec 31 12:44:15 PM PST 23 |
231740094 ps |
| T196 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3054957557 |
|
|
Dec 31 12:43:39 PM PST 23 |
Dec 31 12:43:41 PM PST 23 |
12868654 ps |
| T197 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2877894664 |
|
|
Dec 31 12:43:41 PM PST 23 |
Dec 31 12:43:44 PM PST 23 |
305548884 ps |
| T198 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1901624043 |
|
|
Dec 31 12:43:35 PM PST 23 |
Dec 31 12:43:38 PM PST 23 |
14825886 ps |
| T199 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2663420614 |
|
|
Dec 31 12:43:58 PM PST 23 |
Dec 31 12:44:10 PM PST 23 |
225025367 ps |
| T200 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3713729021 |
|
|
Dec 31 12:43:32 PM PST 23 |
Dec 31 12:43:36 PM PST 23 |
146259878 ps |
| T201 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3947411471 |
|
|
Dec 31 12:43:41 PM PST 23 |
Dec 31 12:43:43 PM PST 23 |
12776557 ps |
| T202 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1060613391 |
|
|
Dec 31 12:43:10 PM PST 23 |
Dec 31 12:43:12 PM PST 23 |
146084415 ps |
| T90 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.769899934 |
|
|
Dec 31 12:43:46 PM PST 23 |
Dec 31 12:43:48 PM PST 23 |
41274856 ps |
| T203 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2409648013 |
|
|
Dec 31 12:43:32 PM PST 23 |
Dec 31 12:43:34 PM PST 23 |
15351165 ps |
| T204 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2295539083 |
|
|
Dec 31 12:43:10 PM PST 23 |
Dec 31 12:43:11 PM PST 23 |
15906412 ps |
| T205 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3726424423 |
|
|
Dec 31 12:43:10 PM PST 23 |
Dec 31 12:43:13 PM PST 23 |
1072754379 ps |
| T206 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1864682083 |
|
|
Dec 31 12:43:46 PM PST 23 |
Dec 31 12:43:48 PM PST 23 |
28826035 ps |
| T207 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.667147794 |
|
|
Dec 31 12:43:45 PM PST 23 |
Dec 31 12:43:50 PM PST 23 |
126712370 ps |
| T208 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1072836312 |
|
|
Dec 31 12:43:53 PM PST 23 |
Dec 31 12:44:06 PM PST 23 |
74035171 ps |
| T209 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.259145749 |
|
|
Dec 31 12:43:30 PM PST 23 |
Dec 31 12:43:32 PM PST 23 |
23148793 ps |
| T91 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1102602212 |
|
|
Dec 31 12:43:53 PM PST 23 |
Dec 31 12:44:16 PM PST 23 |
7591483409 ps |
| T210 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.612990614 |
|
|
Dec 31 12:43:41 PM PST 23 |
Dec 31 12:43:48 PM PST 23 |
2699131462 ps |
| T211 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.492061626 |
|
|
Dec 31 12:43:38 PM PST 23 |
Dec 31 12:43:43 PM PST 23 |
407990117 ps |
| T212 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2026818836 |
|
|
Dec 31 12:43:27 PM PST 23 |
Dec 31 12:43:29 PM PST 23 |
17740062 ps |
| T100 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.845163724 |
|
|
Dec 31 12:43:35 PM PST 23 |
Dec 31 12:43:38 PM PST 23 |
24237289 ps |
| T213 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1340016788 |
|
|
Dec 31 12:43:22 PM PST 23 |
Dec 31 12:43:24 PM PST 23 |
27804555 ps |
| T214 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3948757943 |
|
|
Dec 31 12:43:35 PM PST 23 |
Dec 31 12:43:38 PM PST 23 |
203622344 ps |
| T99 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4059018723 |
|
|
Dec 31 12:43:28 PM PST 23 |
Dec 31 12:43:39 PM PST 23 |
1758762961 ps |
| T118 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3539846661 |
|
|
Dec 31 12:43:39 PM PST 23 |
Dec 31 12:43:43 PM PST 23 |
714325939 ps |
| T215 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4106656346 |
|
|
Dec 31 12:43:34 PM PST 23 |
Dec 31 12:43:37 PM PST 23 |
60954395 ps |
| T124 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1232307197 |
|
|
Dec 31 12:43:38 PM PST 23 |
Dec 31 12:43:42 PM PST 23 |
483115562 ps |
| T216 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2741887435 |
|
|
Dec 31 12:43:38 PM PST 23 |
Dec 31 12:43:45 PM PST 23 |
39444968 ps |
| T217 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1494817852 |
|
|
Dec 31 12:43:53 PM PST 23 |
Dec 31 12:44:03 PM PST 23 |
1322023296 ps |
| T218 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1818149187 |
|
|
Dec 31 12:43:42 PM PST 23 |
Dec 31 12:43:44 PM PST 23 |
16181610 ps |
| T102 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.950696772 |
|
|
Dec 31 12:43:26 PM PST 23 |
Dec 31 12:43:29 PM PST 23 |
854322524 ps |
| T219 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1260298670 |
|
|
Dec 31 12:43:55 PM PST 23 |
Dec 31 12:44:10 PM PST 23 |
25175641 ps |
| T220 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1621515698 |
|
|
Dec 31 12:43:16 PM PST 23 |
Dec 31 12:43:17 PM PST 23 |
88009127 ps |
| T221 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.422301862 |
|
|
Dec 31 12:43:48 PM PST 23 |
Dec 31 12:43:51 PM PST 23 |
247236733 ps |
| T96 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4265178897 |
|
|
Dec 31 12:43:35 PM PST 23 |
Dec 31 12:43:37 PM PST 23 |
14177811 ps |
| T222 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.458185162 |
|
|
Dec 31 12:43:44 PM PST 23 |
Dec 31 12:43:46 PM PST 23 |
37136634 ps |
| T223 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.665744958 |
|
|
Dec 31 12:44:02 PM PST 23 |
Dec 31 12:44:14 PM PST 23 |
41190525 ps |
| T224 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3102402720 |
|
|
Dec 31 12:43:26 PM PST 23 |
Dec 31 12:43:28 PM PST 23 |
14404443 ps |
| T225 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1511070644 |
|
|
Dec 31 12:43:37 PM PST 23 |
Dec 31 12:43:40 PM PST 23 |
25638188 ps |
| T120 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3843572088 |
|
|
Dec 31 12:43:57 PM PST 23 |
Dec 31 12:44:11 PM PST 23 |
183935347 ps |
| T226 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1754775825 |
|
|
Dec 31 12:43:04 PM PST 23 |
Dec 31 12:43:05 PM PST 23 |
65236107 ps |
| T227 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1324933276 |
|
|
Dec 31 12:43:47 PM PST 23 |
Dec 31 12:43:49 PM PST 23 |
85470408 ps |
| T228 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3593149817 |
|
|
Dec 31 12:43:26 PM PST 23 |
Dec 31 12:43:29 PM PST 23 |
67527912 ps |
| T229 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1328043468 |
|
|
Dec 31 12:43:31 PM PST 23 |
Dec 31 12:43:34 PM PST 23 |
22314200 ps |
| T230 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4275226568 |
|
|
Dec 31 12:43:19 PM PST 23 |
Dec 31 12:43:22 PM PST 23 |
841029988 ps |
| T231 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2732875538 |
|
|
Dec 31 12:43:20 PM PST 23 |
Dec 31 12:43:27 PM PST 23 |
410913487 ps |
| T232 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1374962812 |
|
|
Dec 31 12:43:33 PM PST 23 |
Dec 31 12:43:36 PM PST 23 |
47359585 ps |
| T233 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3349571976 |
|
|
Dec 31 12:43:29 PM PST 23 |
Dec 31 12:43:30 PM PST 23 |
32812805 ps |
| T103 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.294216237 |
|
|
Dec 31 12:43:36 PM PST 23 |
Dec 31 12:43:49 PM PST 23 |
799877772 ps |
| T234 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.37834202 |
|
|
Dec 31 12:43:12 PM PST 23 |
Dec 31 12:43:14 PM PST 23 |
16268427 ps |
| T235 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1737146852 |
|
|
Dec 31 12:43:50 PM PST 23 |
Dec 31 12:43:55 PM PST 23 |
173742828 ps |
| T236 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3106215809 |
|
|
Dec 31 12:43:15 PM PST 23 |
Dec 31 12:43:17 PM PST 23 |
12134713 ps |
| T237 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3959074994 |
|
|
Dec 31 12:43:31 PM PST 23 |
Dec 31 12:43:33 PM PST 23 |
45228756 ps |
| T238 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3266577362 |
|
|
Dec 31 12:43:28 PM PST 23 |
Dec 31 12:43:29 PM PST 23 |
25775161 ps |
| T104 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3087303444 |
|
|
Dec 31 12:43:38 PM PST 23 |
Dec 31 12:43:44 PM PST 23 |
309568541 ps |
| T239 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2089823167 |
|
|
Dec 31 12:43:27 PM PST 23 |
Dec 31 12:43:29 PM PST 23 |
116877856 ps |
| T240 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1928321898 |
|
|
Dec 31 12:43:58 PM PST 23 |
Dec 31 12:44:09 PM PST 23 |
18498237 ps |
| T105 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3548696802 |
|
|
Dec 31 12:43:31 PM PST 23 |
Dec 31 12:43:35 PM PST 23 |
267485889 ps |
| T241 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4119004640 |
|
|
Dec 31 12:43:40 PM PST 23 |
Dec 31 12:43:42 PM PST 23 |
12973212 ps |
| T242 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1618625922 |
|
|
Dec 31 12:43:39 PM PST 23 |
Dec 31 12:43:42 PM PST 23 |
98946322 ps |
| T243 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.440532831 |
|
|
Dec 31 12:43:52 PM PST 23 |
Dec 31 12:44:00 PM PST 23 |
24545057 ps |
| T244 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.651819675 |
|
|
Dec 31 12:43:21 PM PST 23 |
Dec 31 12:43:24 PM PST 23 |
246467320 ps |
| T245 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2763251341 |
|
|
Dec 31 12:43:38 PM PST 23 |
Dec 31 12:43:46 PM PST 23 |
1622531206 ps |
| T119 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2504962833 |
|
|
Dec 31 12:43:18 PM PST 23 |
Dec 31 12:43:21 PM PST 23 |
359890394 ps |
| T246 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1858190508 |
|
|
Dec 31 12:43:34 PM PST 23 |
Dec 31 12:43:37 PM PST 23 |
13627549 ps |
| T247 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2507561054 |
|
|
Dec 31 12:43:51 PM PST 23 |
Dec 31 12:43:57 PM PST 23 |
43613689 ps |
| T248 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2408380766 |
|
|
Dec 31 12:43:36 PM PST 23 |
Dec 31 12:43:42 PM PST 23 |
113806392 ps |
| T249 |
/workspace/coverage/default/32.sram_ctrl_partial_access.1074367505 |
|
|
Dec 31 12:29:27 PM PST 23 |
Dec 31 12:29:38 PM PST 23 |
164212642 ps |
| T250 |
/workspace/coverage/default/40.sram_ctrl_regwen.669708022 |
|
|
Dec 31 12:28:59 PM PST 23 |
Dec 31 12:38:18 PM PST 23 |
23715542114 ps |
| T251 |
/workspace/coverage/default/46.sram_ctrl_executable.514744190 |
|
|
Dec 31 12:31:03 PM PST 23 |
Dec 31 12:33:31 PM PST 23 |
960373242 ps |
| T252 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.3456894701 |
|
|
Dec 31 12:27:56 PM PST 23 |
Dec 31 12:28:11 PM PST 23 |
905228012 ps |
| T253 |
/workspace/coverage/default/34.sram_ctrl_executable.1999660347 |
|
|
Dec 31 12:29:28 PM PST 23 |
Dec 31 01:00:25 PM PST 23 |
17486931886 ps |
| T254 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2673602674 |
|
|
Dec 31 12:28:04 PM PST 23 |
Dec 31 12:31:20 PM PST 23 |
3483113028 ps |
| T255 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.587683875 |
|
|
Dec 31 12:28:29 PM PST 23 |
Dec 31 12:32:57 PM PST 23 |
4017333363 ps |
| T92 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3096816202 |
|
|
Dec 31 12:30:32 PM PST 23 |
Dec 31 12:30:47 PM PST 23 |
169594655 ps |
| T256 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.983586739 |
|
|
Dec 31 12:29:16 PM PST 23 |
Dec 31 12:29:28 PM PST 23 |
138779844 ps |
| T257 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3531270233 |
|
|
Dec 31 12:28:50 PM PST 23 |
Dec 31 12:28:58 PM PST 23 |
1391232220 ps |
| T258 |
/workspace/coverage/default/42.sram_ctrl_partial_access.4274773408 |
|
|
Dec 31 12:30:27 PM PST 23 |
Dec 31 12:32:02 PM PST 23 |
226650200 ps |
| T259 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.534886605 |
|
|
Dec 31 12:29:15 PM PST 23 |
Dec 31 12:29:20 PM PST 23 |
26430469 ps |
| T260 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.1397713613 |
|
|
Dec 31 12:29:39 PM PST 23 |
Dec 31 12:30:31 PM PST 23 |
1071854378 ps |
| T93 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.47501562 |
|
|
Dec 31 12:29:29 PM PST 23 |
Dec 31 12:29:37 PM PST 23 |
67497632 ps |
| T17 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1255118585 |
|
|
Dec 31 12:29:03 PM PST 23 |
Dec 31 12:35:12 PM PST 23 |
2593875718 ps |
| T261 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.687055220 |
|
|
Dec 31 12:28:01 PM PST 23 |
Dec 31 12:28:08 PM PST 23 |
301973174 ps |
| T262 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.946534839 |
|
|
Dec 31 12:28:18 PM PST 23 |
Dec 31 12:28:24 PM PST 23 |
552116146 ps |
| T94 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3607388888 |
|
|
Dec 31 12:28:44 PM PST 23 |
Dec 31 12:28:52 PM PST 23 |
155395458 ps |
| T263 |
/workspace/coverage/default/27.sram_ctrl_smoke.2380881519 |
|
|
Dec 31 12:28:30 PM PST 23 |
Dec 31 12:28:42 PM PST 23 |
88593765 ps |
| T264 |
/workspace/coverage/default/14.sram_ctrl_bijection.2357725828 |
|
|
Dec 31 12:28:03 PM PST 23 |
Dec 31 12:29:01 PM PST 23 |
886804003 ps |
| T265 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.979796629 |
|
|
Dec 31 12:29:12 PM PST 23 |
Dec 31 12:41:51 PM PST 23 |
31560143033 ps |
| T110 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.107369166 |
|
|
Dec 31 12:28:14 PM PST 23 |
Dec 31 12:47:41 PM PST 23 |
990456117 ps |
| T95 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3961118540 |
|
|
Dec 31 12:28:27 PM PST 23 |
Dec 31 12:28:34 PM PST 23 |
582737159 ps |
| T266 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2073970994 |
|
|
Dec 31 12:27:38 PM PST 23 |
Dec 31 12:27:51 PM PST 23 |
145468922 ps |
| T18 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.557422809 |
|
|
Dec 31 12:28:57 PM PST 23 |
Dec 31 12:36:24 PM PST 23 |
3050784193 ps |