Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45228363	1			T1	593928		T2	759		T3	4532
triple_byte_access	2558064	1			T1	10329		T2	635		T3	206
halfword_access	3843800	1			T1	15814		T2	989		T3	315
byte_access	5130077	1			T1	20750		T2	1359		T3	379
zero_access	1291322	1			T1	5217		T2	339		T3	101

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28970470

1

T1

323086

T2

1996

T3

2786

auto[1]

29081156

1

T1

322952

T2

2085

T3

2747

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22563238	1			T1	296905		T2	360		T3	2292
auto[0]	triple_byte_access	1275748	1			T1	5181		T2	297		T3	93
auto[0]	halfword_access	1918410	1			T1	7954		T2	500		T3	154
auto[0]	byte_access	2562796	1			T1	10426		T2	659		T3	196
auto[0]	zero_access	650278	1			T1	2620		T2	180		T3	51
auto[1]	word_access	22665125	1			T1	297023		T2	399		T3	2240
auto[1]	triple_byte_access	1282316	1			T1	5148		T2	338		T3	113
auto[1]	halfword_access	1925390	1			T1	7860		T2	489		T3	161
auto[1]	byte_access	2567281	1			T1	10324		T2	700		T3	183
auto[1]	zero_access	641044	1			T1	2597		T2	159		T3	50