Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

12498902

1

T1

7123

T2

31889

T3

107

full_word

52870150

1

T1

70419

T2

367982

T3

1065

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65368772	1			T1	77542		T2	399871		T3	1172
auto[TlIntgErrCmd]	114	1			T29	1		T43	8		T44	5
auto[TlIntgErrData]	89	1			T29	6		T43	5		T44	4
auto[TlIntgErrBoth]	77	1			T29	3		T43	7		T44	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29829830

1

T1

29144

T2

156598

T3

588

auto[1]

35539222

1

T1

48398

T2

243273

T3

584

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5945380	1			T1	2691		T2	12050		T3	55
auto[TlIntgErrNone]	partial	auto[1]	6553270	1			T1	4432		T2	19839		T3	52
auto[TlIntgErrNone]	full_word	auto[0]	23884325	1			T1	26453		T2	144548		T3	533
auto[TlIntgErrNone]	full_word	auto[1]	28985797	1			T1	43966		T2	223434		T3	532
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T43	1		T44	2		T99	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T29	1		T43	7		T44	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T101	1		T104	1		T105	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T99	1		T103	1		T101	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T29	2		T43	2		T44	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T29	4		T43	3		T99	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T100	1		T103	1		T101	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T44	1		T99	1		T102	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T29	1		T43	2		T99	4
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T29	2		T43	3		T44	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T43	1		T100	1		T106	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T43	1		T107	1		-	-