Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	612711	1			T11	135		T13	9440		T5	3
auto[1]	10021518	1			T1	1934		T2	884		T3	512
auto[2]	517985	1			T3	1		T11	123		T13	9477
auto[3]	9943602	1			T1	1902		T2	880		T3	520

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14083492	1			T1	3200		T2	1271		T3	881
auto[1]	1991774	1			T1	296		T2	228		T3	63
auto[2]	1988501	1			T1	309		T2	229		T3	81
auto[3]	3032049	1			T1	31		T2	36		T3	8

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8147879

1

T1

3835

T2

1764

T3

1033

auto[1]

12947937

1

T1

1

T7

278988

T8

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	258624	1			T11	115		T5	3		T55	10
auto[0]	auto[0]	auto[1]	26662	1			T11	10		T55	84		T24	102
auto[0]	auto[0]	auto[2]	26280	1			T11	9		T55	87		T24	113
auto[0]	auto[0]	auto[3]	7035	1			T11	1		T55	397		T24	7
auto[0]	auto[1]	auto[0]	3083223	1			T1	1624		T2	648		T3	442
auto[0]	auto[1]	auto[1]	328197	1			T1	136		T2	157		T3	21
auto[0]	auto[1]	auto[2]	313213	1			T1	161		T2	56		T3	44
auto[0]	auto[1]	auto[3]	71075	1			T1	13		T2	23		T3	5
auto[0]	auto[2]	auto[0]	224622	1			T3	1		T11	109		T5	7
auto[0]	auto[2]	auto[1]	22999	1			T11	7		T55	58		T24	78
auto[0]	auto[2]	auto[2]	21582	1			T11	7		T55	88		T24	78
auto[0]	auto[2]	auto[3]	5387	1			T55	435		T24	9		T112	2
auto[0]	auto[3]	auto[0]	3050729	1			T1	1575		T2	623		T3	438
auto[0]	auto[3]	auto[1]	309610	1			T1	160		T2	71		T3	42
auto[0]	auto[3]	auto[2]	324632	1			T1	148		T2	173		T3	37
auto[0]	auto[3]	auto[3]	74009	1			T1	18		T2	13		T3	3
auto[1]	auto[0]	auto[0]	10000	1			T13	350		T113	5		T111	872
auto[1]	auto[0]	auto[1]	43781	1			T13	1418		T111	4201		T96	1
auto[1]	auto[0]	auto[2]	43559	1			T13	1347		T24	2		T111	4124
auto[1]	auto[0]	auto[3]	196770	1			T13	6325		T75	1		T111	18447
auto[1]	auto[1]	auto[0]	3723860	1			T7	116650		T9	16		T10	3
auto[1]	auto[1]	auto[1]	624861	1			T7	10458		T9	2		T4	1
auto[1]	auto[1]	auto[2]	604102	1			T7	11749		T9	2		T10	3
auto[1]	auto[1]	auto[3]	1272987	1			T7	1029		T8	2		T9	1
auto[1]	auto[2]	auto[0]	8464	1			T13	187		T111	855		T114	3
auto[1]	auto[2]	auto[1]	36730	1			T13	828		T111	3798		T115	2
auto[1]	auto[2]	auto[2]	36197	1			T13	1598		T111	3551		T109	1
auto[1]	auto[2]	auto[3]	162004	1			T13	6864		T55	1		T111	15476
auto[1]	auto[3]	auto[0]	3723970	1			T1	1		T7	116154		T9	16
auto[1]	auto[3]	auto[1]	598934	1			T7	11497		T9	1		T14	6998
auto[1]	auto[3]	auto[2]	618936	1			T7	10435		T9	3		T10	1
auto[1]	auto[3]	auto[3]	1242782	1			T7	1016		T8	2		T14	711