Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	316106162	145163	0	0
ctrl_regwen_rd_A	316106162	7643	0	0
exec_rd_A	316106162	7248	0	0
exec_regwen_rd_A	316106162	7553	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316106162	145163	0	0
T5	50387	0	0	0
T11	55924	1529	0	0
T12	2252	0	0	0
T13	102655	0	0	0
T14	247282	0	0	0
T18	765	0	0	0
T27	0	2010	0	0
T28	0	2329	0	0
T29	0	4	0	0
T43	0	3	0	0
T45	0	694	0	0
T46	0	158	0	0
T47	0	41	0	0
T48	0	6	0	0
T49	0	867	0	0
T52	85795	0	0	0
T53	365673	0	0	0
T54	6701	0	0	0
T55	56495	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316106162	7643	0	0
T5	50387	0	0	0
T11	55924	394	0	0
T12	2252	0	0	0
T13	102655	0	0	0
T14	247282	0	0	0
T18	765	0	0	0
T29	0	27	0	0
T43	0	66	0	0
T45	0	51	0	0
T47	0	29	0	0
T51	0	29	0	0
T52	85795	0	0	0
T53	365673	0	0	0
T54	6701	0	0	0
T55	56495	0	0	0
T61	0	26	0	0
T65	0	31	0	0
T87	0	34	0	0
T95	0	13	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316106162	7248	0	0
T5	50387	0	0	0
T11	55924	389	0	0
T12	2252	0	0	0
T13	102655	0	0	0
T14	247282	0	0	0
T18	765	0	0	0
T29	0	52	0	0
T43	0	48	0	0
T45	0	41	0	0
T47	0	16	0	0
T51	0	52	0	0
T52	85795	0	0	0
T53	365673	0	0	0
T54	6701	0	0	0
T55	56495	0	0	0
T61	0	26	0	0
T65	0	19	0	0
T87	0	38	0	0
T95	0	33	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316106162	7553	0	0
T5	50387	0	0	0
T11	55924	357	0	0
T12	2252	0	0	0
T13	102655	0	0	0
T14	247282	0	0	0
T18	765	0	0	0
T29	0	44	0	0
T43	0	75	0	0
T45	0	66	0	0
T47	0	21	0	0
T51	0	66	0	0
T52	85795	0	0	0
T53	365673	0	0	0
T54	6701	0	0	0
T55	56495	0	0	0
T61	0	30	0	0
T65	0	9	0	0
T87	0	78	0	0
T95	0	10	0	0