Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	143402196	1			T1	225914		T2	18324		T3	12284
instr_valid_dis	109705343	1			T1	225914		T2	18324		T3	12284
instr_en	23322200	1			T18	5309		T6	76972		T133	37522

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11096988	1			T6	34696		T20	67950		T135	92728
sram_ifetch_valid_disable	110952711	1			T1	225914		T2	18324		T3	12284
sram_ifetch_enable	21352497	1			T18	2151		T6	75810		T20	201816

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	143402196	1			T1	225914		T2	18324		T3	12284
hw_debug_en_valid_off	110607987	1			T1	225914		T2	18324		T3	12284
hw_debug_en_on	22236646	1			T6	75648		T20	156608		T133	147730

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110952711	1			T1	225914		T2	18324		T3	12284
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97431296	1			T1	225914		T2	18324		T3	12284
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9072600	1			T18	5309		T6	46182		T133	2910
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4554258	1			T6	27606		T20	19630		T135	72828
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1748269	1			T6	27606		T20	19630		T135	1656
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1930773	1			T135	71172		T138	14484		T137	37030
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4206779	1			T6	7090		T20	37344		T134	20392
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1884838	1			T6	7090		T20	37344		T134	94
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1789687	1			T134	20298		T45	30718		T138	54598
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9144514	1			T6	53836		T20	24052		T133	122418
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3364333	1			T6	34842		T20	24008		T133	62864
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3975719	1			T6	18994		T135	45738		T134	29698

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9613612	1			T6	30790		T133	34612		T135	23906
lc_exec_en	8885353	1			T6	14722		T20	95212		T133	25312
valid_exec_dis	105203097	1			T1	225914		T2	18324		T3	12284
invalid_exec_dis	32449485	1			T18	2151		T6	110506		T20	269766