| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4127819036 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.180632526 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3232341230 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3715332412 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1380982831 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3865500781 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2082147918 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4037858714 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1476006293 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3579375550 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4167326397 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.949865288 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4006993094 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.518727269 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2902582630 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1860680660 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2256568251 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.529454251 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2415498172 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3101515076 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1752084226 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2933550548 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2228997532 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3665874464 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.34420374 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4167655149 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2484020618 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1860402266 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1137132336 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2226919905 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.715499492 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1892735580 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1774846016 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.414392282 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.758915713 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3096142506 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2025919268 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2113482094 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3310366464 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1346617628 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2415512295 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.924628758 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.26451414 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2150212177 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.395892514 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.220514700 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1020547399 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.667895981 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.972472471 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3930037875 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2151846478 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.51368293 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1619638349 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1410399145 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2162770628 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4235785294 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4102085746 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3074849566 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2564593157 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3823447510 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3438912240 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3373124317 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2134092966 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3059269520 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2519601627 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3461780653 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.723327493 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2522128167 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1017187995 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.628918306 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.321057144 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1434827076 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2651586460 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.154051459 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2885818256 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3994081635 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3894071158 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3969591305 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.570080202 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2340766817 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1065249099 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3287668933 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2365594616 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2556873665 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2435857601 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.665148491 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1264112283 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.898513851 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4082333485 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2291356232 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3028391345 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2648928808 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.229247609 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3388397703 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4166265322 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2588373143 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1989636685 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1435020979 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1400993610 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.659618369 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3725401957 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1078409581 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.638175354 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1063267119 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2193067451 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3315533296 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1691518438 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2327456622 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.670251788 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1991386518 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1423194789 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3737967939 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.944965597 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2431992889 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3711309707 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1381440667 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3651273520 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.29282279 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.846539619 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.519272973 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1271911377 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.567376063 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2380015388 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3909814533 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1371517271 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2441725708 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4128888366 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2960783469 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3694561076 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2369765267 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.877272571 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.3299765984 |
| /workspace/coverage/default/0.sram_ctrl_bijection.2625697901 |
| /workspace/coverage/default/0.sram_ctrl_executable.3137962186 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.692956559 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.4228896014 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.1406648657 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.1736692048 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.1188627887 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1282230109 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.405030573 |
| /workspace/coverage/default/0.sram_ctrl_regwen.507831047 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.2564353991 |
| /workspace/coverage/default/0.sram_ctrl_smoke.282753137 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.1703777450 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2821212268 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.23023819 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2427170504 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.989846652 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.1666156859 |
| /workspace/coverage/default/1.sram_ctrl_bijection.924336544 |
| /workspace/coverage/default/1.sram_ctrl_executable.2450537270 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.2028954484 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.4157382833 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.4040537292 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.1696961918 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.3476061559 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1495999913 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.4175380534 |
| /workspace/coverage/default/1.sram_ctrl_regwen.2150213609 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.709770893 |
| /workspace/coverage/default/1.sram_ctrl_smoke.3959568375 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.1557423059 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3341226099 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3171389242 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.55235249 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2985235114 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.3584117031 |
| /workspace/coverage/default/10.sram_ctrl_bijection.3572697749 |
| /workspace/coverage/default/10.sram_ctrl_executable.49159270 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.149435825 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1280993140 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.2998905560 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.3017870844 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.579521803 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3613861746 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.2599082674 |
| /workspace/coverage/default/10.sram_ctrl_regwen.33172325 |
| /workspace/coverage/default/10.sram_ctrl_smoke.2479281927 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.3454482536 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2989861872 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3367737109 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3714088193 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3779572545 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.2522322781 |
| /workspace/coverage/default/11.sram_ctrl_bijection.788768510 |
| /workspace/coverage/default/11.sram_ctrl_executable.192239900 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.392311568 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3202053685 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.969142650 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.1240564147 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1051613940 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.988544887 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.3499931993 |
| /workspace/coverage/default/11.sram_ctrl_regwen.4176252754 |
| /workspace/coverage/default/11.sram_ctrl_smoke.4146538422 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.2008600809 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2534648297 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3291411775 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.466593250 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.4028557804 |
| /workspace/coverage/default/12.sram_ctrl_bijection.935016953 |
| /workspace/coverage/default/12.sram_ctrl_executable.2963839537 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.2972449281 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.4293863415 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3250135455 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.137634936 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.714857979 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.1735984312 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.594636007 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.828135365 |
| /workspace/coverage/default/12.sram_ctrl_regwen.849606148 |
| /workspace/coverage/default/12.sram_ctrl_smoke.3338468457 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3108457297 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1594309507 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1234871542 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3729588027 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.25812728 |
| /workspace/coverage/default/13.sram_ctrl_bijection.1475025828 |
| /workspace/coverage/default/13.sram_ctrl_executable.557633351 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.3100749742 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.1466299162 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1295331485 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.2259503443 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.731115823 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.1000591436 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.979860939 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1412926460 |
| /workspace/coverage/default/13.sram_ctrl_regwen.2295824350 |
| /workspace/coverage/default/13.sram_ctrl_smoke.340030517 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.4006633941 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2886088159 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2259653209 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1206469203 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.1840606605 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2038470335 |
| /workspace/coverage/default/14.sram_ctrl_executable.2104387959 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.3773448762 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1593061453 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.2852338547 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.560095270 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.1433391269 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1826355221 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.1777928185 |
| /workspace/coverage/default/14.sram_ctrl_regwen.1686195291 |
| /workspace/coverage/default/14.sram_ctrl_smoke.1755585750 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.2091386104 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.660378026 |
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| /workspace/coverage/default/43.sram_ctrl_multiple_keys.328799200 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.4080503310 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3895152807 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.2393916551 |
| /workspace/coverage/default/43.sram_ctrl_regwen.451896603 |
| /workspace/coverage/default/43.sram_ctrl_smoke.1246088287 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.3344477946 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1512061290 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3678886543 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1572438302 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2233075196 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.2972865981 |
| /workspace/coverage/default/44.sram_ctrl_bijection.4146020760 |
| /workspace/coverage/default/44.sram_ctrl_executable.466634631 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.735104979 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.4176115157 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.4109808879 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.2409825622 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2363876030 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3520117693 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.3338380786 |
| /workspace/coverage/default/44.sram_ctrl_regwen.1791288235 |
| /workspace/coverage/default/44.sram_ctrl_smoke.1070284832 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.450200745 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1585256269 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1895078770 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2916887224 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2191231053 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.1754634685 |
| /workspace/coverage/default/45.sram_ctrl_bijection.3790919900 |
| /workspace/coverage/default/45.sram_ctrl_executable.3101815001 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.3963077139 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.3398456342 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3429997291 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.605130394 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.3707482441 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.1913362245 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1588513702 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.2366900298 |
| /workspace/coverage/default/45.sram_ctrl_regwen.379725206 |
| /workspace/coverage/default/45.sram_ctrl_smoke.1795695267 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.3313570215 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3264335308 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.4192553613 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1087306065 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.757970051 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.2522709812 |
| /workspace/coverage/default/46.sram_ctrl_bijection.2356751739 |
| /workspace/coverage/default/46.sram_ctrl_executable.963467503 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.3867302458 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.3193491830 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3295738935 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.2218811533 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.1899013291 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.682325320 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3455612427 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.2583200954 |
| /workspace/coverage/default/46.sram_ctrl_regwen.1980505011 |
| /workspace/coverage/default/46.sram_ctrl_smoke.3439005831 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.384374011 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3749247359 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3530091145 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1696441550 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3103775011 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.1663646783 |
| /workspace/coverage/default/47.sram_ctrl_bijection.236331417 |
| /workspace/coverage/default/47.sram_ctrl_executable.3691341533 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.524331088 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.297174823 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3362819192 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.1366950620 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.264963750 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.3043117013 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4200771919 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3332539621 |
| /workspace/coverage/default/47.sram_ctrl_regwen.298663733 |
| /workspace/coverage/default/47.sram_ctrl_smoke.2306517674 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.184282781 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2968068191 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1509617983 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1481268003 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.4145890558 |
| /workspace/coverage/default/48.sram_ctrl_bijection.2845876426 |
| /workspace/coverage/default/48.sram_ctrl_executable.401270259 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.2507843435 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.2586316715 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1483675143 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.1098822314 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.1811277078 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.3217335384 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3457691759 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.4215661767 |
| /workspace/coverage/default/48.sram_ctrl_regwen.1365340420 |
| /workspace/coverage/default/48.sram_ctrl_smoke.1367357753 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.2251025601 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1838777153 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3475053239 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2702504434 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3770990174 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.1404728833 |
| /workspace/coverage/default/49.sram_ctrl_bijection.748255673 |
| /workspace/coverage/default/49.sram_ctrl_executable.1810082887 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.1180634616 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2610599716 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.4266472418 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.4131498955 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.1870804251 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.2369175869 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4109400591 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.1704985090 |
| /workspace/coverage/default/49.sram_ctrl_regwen.2223634188 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3261228959 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.2688349153 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4227984145 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1363574907 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2841840182 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3158092657 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.290276305 |
| /workspace/coverage/default/5.sram_ctrl_bijection.1792698813 |
| /workspace/coverage/default/5.sram_ctrl_executable.3258973582 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.2746089871 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.1706872700 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3930349644 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.1890462529 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.642670812 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.2454921137 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.536682063 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.4256814081 |
| /workspace/coverage/default/5.sram_ctrl_regwen.4267261306 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2814231476 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.543797692 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3336820697 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1819345290 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.75127730 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3732636828 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1282814244 |
| /workspace/coverage/default/6.sram_ctrl_executable.781868051 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.248807062 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.2361729218 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3848029084 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.1767861208 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.2016422296 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.937816175 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1900695475 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.51560304 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3896960926 |
| /workspace/coverage/default/6.sram_ctrl_smoke.17157759 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.2585886676 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2622654023 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2384998604 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3363387104 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3253302802 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.1382797862 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2443359644 |
| /workspace/coverage/default/7.sram_ctrl_executable.1244789166 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.2136295301 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.1022878589 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1451842590 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.3582885916 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.3736433233 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.2595076554 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2647769146 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.1659721822 |
| /workspace/coverage/default/7.sram_ctrl_regwen.3944743824 |
| /workspace/coverage/default/7.sram_ctrl_smoke.2459437983 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.1995268514 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.500507069 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3040894897 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.855340919 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.4182456315 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.2570493664 |
| /workspace/coverage/default/8.sram_ctrl_bijection.2036617954 |
| /workspace/coverage/default/8.sram_ctrl_executable.1240646179 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.2990740850 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.200460717 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.721332236 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.106963540 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2164668695 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3708174254 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.431548598 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.2604348904 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1750943697 |
| /workspace/coverage/default/8.sram_ctrl_smoke.2022778438 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.284207877 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2343680283 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3779182174 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.46331890 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2467516613 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1615614986 |
| /workspace/coverage/default/9.sram_ctrl_bijection.3177234181 |
| /workspace/coverage/default/9.sram_ctrl_executable.1219837589 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.1294268917 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3093649825 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3324091794 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3579264739 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.3150997435 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1836487511 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.2132548133 |
| /workspace/coverage/default/9.sram_ctrl_regwen.1197651630 |
| /workspace/coverage/default/9.sram_ctrl_smoke.1690345796 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.105631335 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1222276591 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1679763779 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2053873129 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.298725841 |
|
|
Jan 10 12:44:49 PM PST 24 |
Jan 10 12:53:56 PM PST 24 |
8886920244 ps |
| T2 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2361729218 |
|
|
Jan 10 12:45:00 PM PST 24 |
Jan 10 12:47:42 PM PST 24 |
516484400 ps |
| T3 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1406648657 |
|
|
Jan 10 12:44:40 PM PST 24 |
Jan 10 12:46:08 PM PST 24 |
580671328 ps |
| T4 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3166247509 |
|
|
Jan 10 12:46:43 PM PST 24 |
Jan 10 12:59:01 PM PST 24 |
47828705498 ps |
| T5 |
/workspace/coverage/default/39.sram_ctrl_partial_access.3711304425 |
|
|
Jan 10 12:46:45 PM PST 24 |
Jan 10 12:48:06 PM PST 24 |
783555039 ps |
| T9 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3217335384 |
|
|
Jan 10 12:47:09 PM PST 24 |
Jan 10 12:49:15 PM PST 24 |
3881225572 ps |
| T10 |
/workspace/coverage/default/49.sram_ctrl_bijection.748255673 |
|
|
Jan 10 12:47:05 PM PST 24 |
Jan 10 12:49:54 PM PST 24 |
13268730443 ps |
| T11 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3324091794 |
|
|
Jan 10 12:45:12 PM PST 24 |
Jan 10 12:46:44 PM PST 24 |
2356858847 ps |
| T12 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2167886775 |
|
|
Jan 10 12:46:11 PM PST 24 |
Jan 10 12:47:33 PM PST 24 |
42898643 ps |
| T13 |
/workspace/coverage/default/32.sram_ctrl_smoke.4215249028 |
|
|
Jan 10 12:46:25 PM PST 24 |
Jan 10 12:48:55 PM PST 24 |
1157963801 ps |
| T14 |
/workspace/coverage/default/24.sram_ctrl_bijection.3120009427 |
|
|
Jan 10 12:46:00 PM PST 24 |
Jan 10 12:48:10 PM PST 24 |
1499793443 ps |
| T22 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3290532141 |
|
|
Jan 10 12:45:39 PM PST 24 |
Jan 10 12:47:00 PM PST 24 |
28611733 ps |
| T15 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3377642523 |
|
|
Jan 10 12:44:47 PM PST 24 |
Jan 10 12:46:07 PM PST 24 |
345002033 ps |
| T16 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2932366808 |
|
|
Jan 10 12:47:00 PM PST 24 |
Jan 10 12:49:55 PM PST 24 |
312827567 ps |
| T17 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2978500056 |
|
|
Jan 10 12:46:32 PM PST 24 |
Jan 10 12:47:51 PM PST 24 |
152664064 ps |
| T23 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2522709812 |
|
|
Jan 10 12:46:49 PM PST 24 |
Jan 10 12:48:07 PM PST 24 |
16964322 ps |
| T18 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3855350121 |
|
|
Jan 10 12:45:12 PM PST 24 |
Jan 10 01:07:38 PM PST 24 |
1999906079 ps |
| T24 |
/workspace/coverage/default/30.sram_ctrl_alert_test.2115840377 |
|
|
Jan 10 12:46:05 PM PST 24 |
Jan 10 12:47:34 PM PST 24 |
36862209 ps |
| T62 |
/workspace/coverage/default/38.sram_ctrl_bijection.292703012 |
|
|
Jan 10 12:46:30 PM PST 24 |
Jan 10 12:48:17 PM PST 24 |
1761528687 ps |
| T19 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1786774464 |
|
|
Jan 10 12:45:49 PM PST 24 |
Jan 10 12:52:11 PM PST 24 |
1745432843 ps |
| T146 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.2272796131 |
|
|
Jan 10 12:46:32 PM PST 24 |
Jan 10 12:47:58 PM PST 24 |
484579283 ps |
| T6 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1272832243 |
|
|
Jan 10 12:46:07 PM PST 24 |
Jan 10 12:59:52 PM PST 24 |
20080066463 ps |
| T147 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.507915343 |
|
|
Jan 10 12:46:32 PM PST 24 |
Jan 10 12:47:48 PM PST 24 |
133950938 ps |
| T36 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.3414668924 |
|
|
Jan 10 12:46:32 PM PST 24 |
Jan 10 12:47:48 PM PST 24 |
44684013 ps |
| T142 |
/workspace/coverage/default/35.sram_ctrl_partial_access.4045490322 |
|
|
Jan 10 12:46:28 PM PST 24 |
Jan 10 12:48:19 PM PST 24 |
301783856 ps |
| T7 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2136295301 |
|
|
Jan 10 12:44:59 PM PST 24 |
Jan 10 12:46:32 PM PST 24 |
2883968676 ps |
| T8 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1479129248 |
|
|
Jan 10 12:46:40 PM PST 24 |
Jan 10 12:48:06 PM PST 24 |
3402965036 ps |
| T77 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.4156007277 |
|
|
Jan 10 12:45:52 PM PST 24 |
Jan 10 12:52:06 PM PST 24 |
11770967101 ps |
| T108 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.46331890 |
|
|
Jan 10 12:45:07 PM PST 24 |
Jan 10 12:46:50 PM PST 24 |
346453722 ps |
| T148 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1087306065 |
|
|
Jan 10 12:46:53 PM PST 24 |
Jan 10 12:48:16 PM PST 24 |
101904945 ps |
| T149 |
/workspace/coverage/default/43.sram_ctrl_smoke.1246088287 |
|
|
Jan 10 12:46:51 PM PST 24 |
Jan 10 12:49:01 PM PST 24 |
915511406 ps |
| T25 |
/workspace/coverage/default/2.sram_ctrl_alert_test.4149168802 |
|
|
Jan 10 12:44:49 PM PST 24 |
Jan 10 12:46:07 PM PST 24 |
28819151 ps |
| T150 |
/workspace/coverage/default/48.sram_ctrl_smoke.1367357753 |
|
|
Jan 10 12:47:04 PM PST 24 |
Jan 10 12:48:36 PM PST 24 |
731049859 ps |
| T21 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3654215195 |
|
|
Jan 10 12:46:45 PM PST 24 |
Jan 10 12:54:49 PM PST 24 |
27956310693 ps |
| T32 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2804742814 |
|
|
Jan 10 12:45:39 PM PST 24 |
Jan 10 12:47:05 PM PST 24 |
979133701 ps |
| T151 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1556832775 |
|
|
Jan 10 12:46:47 PM PST 24 |
Jan 10 12:48:09 PM PST 24 |
37066825 ps |
| T152 |
/workspace/coverage/default/21.sram_ctrl_bijection.4066187895 |
|
|
Jan 10 12:45:53 PM PST 24 |
Jan 10 12:47:55 PM PST 24 |
620432984 ps |
| T143 |
/workspace/coverage/default/19.sram_ctrl_partial_access.274487805 |
|
|
Jan 10 12:46:00 PM PST 24 |
Jan 10 12:47:47 PM PST 24 |
688670987 ps |
| T111 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2490707176 |
|
|
Jan 10 12:45:50 PM PST 24 |
Jan 10 12:50:20 PM PST 24 |
3965963009 ps |
| T20 |
/workspace/coverage/default/46.sram_ctrl_regwen.1980505011 |
|
|
Jan 10 12:46:49 PM PST 24 |
Jan 10 01:07:11 PM PST 24 |
8972187446 ps |
| T112 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2997917387 |
|
|
Jan 10 12:46:20 PM PST 24 |
Jan 10 12:52:13 PM PST 24 |
13243061972 ps |
| T153 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.1294268917 |
|
|
Jan 10 12:45:07 PM PST 24 |
Jan 10 12:47:48 PM PST 24 |
253824008 ps |
| T26 |
/workspace/coverage/default/37.sram_ctrl_alert_test.4227200624 |
|
|
Jan 10 12:46:44 PM PST 24 |
Jan 10 12:47:59 PM PST 24 |
10884946 ps |
| T83 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.193029335 |
|
|
Jan 10 12:46:38 PM PST 24 |
Jan 10 12:54:21 PM PST 24 |
5911662081 ps |
| T113 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2299382059 |
|
|
Jan 10 12:46:40 PM PST 24 |
Jan 10 12:52:56 PM PST 24 |
3187272651 ps |
| T154 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.4215661767 |
|
|
Jan 10 12:47:09 PM PST 24 |
Jan 10 12:48:27 PM PST 24 |
84405147 ps |
| T114 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.4059676714 |
|
|
Jan 10 12:46:20 PM PST 24 |
Jan 10 12:52:20 PM PST 24 |
3021600657 ps |
| T133 |
/workspace/coverage/default/13.sram_ctrl_executable.557633351 |
|
|
Jan 10 12:45:17 PM PST 24 |
Jan 10 12:52:23 PM PST 24 |
2079903168 ps |
| T155 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.400049748 |
|
|
Jan 10 12:46:26 PM PST 24 |
Jan 10 12:47:57 PM PST 24 |
103024814 ps |
| T156 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.560095270 |
|
|
Jan 10 12:45:21 PM PST 24 |
Jan 10 01:05:04 PM PST 24 |
14222352958 ps |
| T157 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.149435825 |
|
|
Jan 10 12:45:12 PM PST 24 |
Jan 10 12:46:53 PM PST 24 |
143962695 ps |
| T158 |
/workspace/coverage/default/29.sram_ctrl_bijection.3533548123 |
|
|
Jan 10 12:46:13 PM PST 24 |
Jan 10 12:48:52 PM PST 24 |
4182755859 ps |
| T159 |
/workspace/coverage/default/24.sram_ctrl_smoke.3932828667 |
|
|
Jan 10 12:46:00 PM PST 24 |
Jan 10 12:48:59 PM PST 24 |
136109317 ps |
| T160 |
/workspace/coverage/default/27.sram_ctrl_smoke.2032082208 |
|
|
Jan 10 12:46:08 PM PST 24 |
Jan 10 12:47:36 PM PST 24 |
142584790 ps |
| T33 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1180634616 |
|
|
Jan 10 12:47:10 PM PST 24 |
Jan 10 12:48:41 PM PST 24 |
946751401 ps |
| T84 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.715669252 |
|
|
Jan 10 12:45:39 PM PST 24 |
Jan 10 12:47:02 PM PST 24 |
63426658 ps |
| T161 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2841840182 |
|
|
Jan 10 12:47:10 PM PST 24 |
Jan 10 12:48:44 PM PST 24 |
1133299125 ps |
| T162 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.2419041198 |
|
|
Jan 10 12:46:08 PM PST 24 |
Jan 10 12:47:29 PM PST 24 |
92799631 ps |
| T115 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1388738474 |
|
|
Jan 10 12:46:29 PM PST 24 |
Jan 10 12:55:34 PM PST 24 |
25290670792 ps |
| T116 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.23023819 |
|
|
Jan 10 12:44:33 PM PST 24 |
Jan 10 12:49:10 PM PST 24 |
4192594772 ps |
| T163 |
/workspace/coverage/default/43.sram_ctrl_bijection.1379160724 |
|
|
Jan 10 12:46:40 PM PST 24 |
Jan 10 12:48:45 PM PST 24 |
2960940646 ps |
| T27 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3107595651 |
|
|
Jan 10 12:46:00 PM PST 24 |
Jan 10 12:47:24 PM PST 24 |
14572049 ps |
| T85 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1011755036 |
|
|
Jan 10 12:45:23 PM PST 24 |
Jan 10 01:02:31 PM PST 24 |
2727107978 ps |
| T117 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3613861746 |
|
|
Jan 10 12:45:06 PM PST 24 |
Jan 10 12:51:20 PM PST 24 |
8503403998 ps |
| T86 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1907354040 |
|
|
Jan 10 12:46:35 PM PST 24 |
Jan 10 12:51:29 PM PST 24 |
3121086971 ps |
| T164 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2437486377 |
|
|
Jan 10 12:45:55 PM PST 24 |
Jan 10 12:47:41 PM PST 24 |
2593020142 ps |
| T165 |
/workspace/coverage/default/40.sram_ctrl_stress_all.2693060508 |
|
|
Jan 10 12:47:00 PM PST 24 |
Jan 10 01:03:30 PM PST 24 |
11614219837 ps |
| T166 |
/workspace/coverage/default/24.sram_ctrl_stress_all.2592906208 |
|
|
Jan 10 12:45:54 PM PST 24 |
Jan 10 12:58:06 PM PST 24 |
53929227843 ps |
| T167 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.453011112 |
|
|
Jan 10 12:45:53 PM PST 24 |
Jan 10 01:02:35 PM PST 24 |
11397277080 ps |
| T144 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3195961052 |
|
|
Jan 10 12:46:46 PM PST 24 |
Jan 10 12:48:11 PM PST 24 |
290004092 ps |
| T168 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2119711120 |
|
|
Jan 10 12:45:57 PM PST 24 |
Jan 10 12:49:48 PM PST 24 |
6000288722 ps |
| T140 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3457691759 |
|
|
Jan 10 12:47:01 PM PST 24 |
Jan 10 12:55:34 PM PST 24 |
99678613215 ps |
| T169 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1652269910 |
|
|
Jan 10 12:45:57 PM PST 24 |
Jan 10 12:47:27 PM PST 24 |
73774754 ps |
| T87 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2334955606 |
|
|
Jan 10 12:45:57 PM PST 24 |
Jan 10 01:02:39 PM PST 24 |
10860216265 ps |
| T170 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.840618751 |
|
|
Jan 10 12:47:10 PM PST 24 |
Jan 10 12:48:31 PM PST 24 |
97522446 ps |
| T135 |
/workspace/coverage/default/38.sram_ctrl_executable.1805412471 |
|
|
Jan 10 12:46:39 PM PST 24 |
Jan 10 01:02:52 PM PST 24 |
3569403097 ps |
| T171 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.200765543 |
|
|
Jan 10 12:46:46 PM PST 24 |
Jan 10 12:49:09 PM PST 24 |
116361372 ps |
| T172 |
/workspace/coverage/default/48.sram_ctrl_alert_test.4145890558 |
|
|
Jan 10 12:47:09 PM PST 24 |
Jan 10 12:48:27 PM PST 24 |
11656783 ps |
| T173 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.392311568 |
|
|
Jan 10 12:45:12 PM PST 24 |
Jan 10 12:47:04 PM PST 24 |
504556040 ps |
| T174 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2910987868 |
|
|
Jan 10 12:46:15 PM PST 24 |
Jan 10 12:47:40 PM PST 24 |
136632239 ps |
| T134 |
/workspace/coverage/default/1.sram_ctrl_executable.2450537270 |
|
|
Jan 10 12:44:42 PM PST 24 |
Jan 10 01:00:40 PM PST 24 |
33722752181 ps |
| T175 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.840600803 |
|
|
Jan 10 12:47:13 PM PST 24 |
Jan 10 12:48:37 PM PST 24 |
43225739 ps |
| T34 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3264335308 |
|
|
Jan 10 12:46:49 PM PST 24 |
Jan 10 01:16:26 PM PST 24 |
3035794787 ps |
| T63 |
/workspace/coverage/default/39.sram_ctrl_alert_test.251209985 |
|
|
Jan 10 12:46:43 PM PST 24 |
Jan 10 12:48:10 PM PST 24 |
15381566 ps |
| T64 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.2613028326 |
|
|
Jan 10 12:46:33 PM PST 24 |
Jan 10 12:47:51 PM PST 24 |
50666804 ps |
| T65 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1835666723 |
|
|
Jan 10 12:46:36 PM PST 24 |
Jan 10 12:48:11 PM PST 24 |
372363198 ps |
| T109 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3461780653 |
|
|
Jan 10 12:54:52 PM PST 24 |
Jan 10 12:55:58 PM PST 24 |
18087189 ps |
| T68 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.180632526 |
|
|
Jan 10 12:54:32 PM PST 24 |
Jan 10 12:55:38 PM PST 24 |
575350256 ps |
| T35 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2564593157 |
|
|
Jan 10 12:55:04 PM PST 24 |
Jan 10 12:56:12 PM PST 24 |
36009255 ps |
| T69 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3355863118 |
|
|
Jan 10 12:54:54 PM PST 24 |
Jan 10 12:56:04 PM PST 24 |
1656774700 ps |
| T52 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1691518438 |
|
|
Jan 10 12:54:37 PM PST 24 |
Jan 10 12:55:44 PM PST 24 |
115491578 ps |
| T110 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.519272973 |
|
|
Jan 10 12:54:41 PM PST 24 |
Jan 10 12:55:47 PM PST 24 |
15680619 ps |
| T70 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2150212177 |
|
|
Jan 10 12:57:05 PM PST 24 |
Jan 10 12:58:18 PM PST 24 |
20704173 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.518727269 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:33 PM PST 24 |
32281036 ps |
| T51 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1175094162 |
|
|
Jan 10 12:54:45 PM PST 24 |
Jan 10 12:55:52 PM PST 24 |
142302835 ps |
| T71 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3823447510 |
|
|
Jan 10 12:54:51 PM PST 24 |
Jan 10 12:55:57 PM PST 24 |
26566102 ps |
| T119 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.670251788 |
|
|
Jan 10 12:54:36 PM PST 24 |
Jan 10 12:55:42 PM PST 24 |
10663161 ps |
| T54 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3315533296 |
|
|
Jan 10 12:54:37 PM PST 24 |
Jan 10 12:55:44 PM PST 24 |
45932198 ps |
| T72 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4167655149 |
|
|
Jan 10 12:54:43 PM PST 24 |
Jan 10 12:55:49 PM PST 24 |
25187534 ps |
| T53 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3059269520 |
|
|
Jan 10 12:54:56 PM PST 24 |
Jan 10 12:56:03 PM PST 24 |
154242091 ps |
| T55 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2519601627 |
|
|
Jan 10 12:54:51 PM PST 24 |
Jan 10 12:55:58 PM PST 24 |
214100884 ps |
| T56 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2415512295 |
|
|
Jan 10 12:54:52 PM PST 24 |
Jan 10 12:55:58 PM PST 24 |
56246076 ps |
| T57 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.898513851 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:33 PM PST 24 |
27918015 ps |
| T58 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1774846016 |
|
|
Jan 10 12:54:47 PM PST 24 |
Jan 10 12:55:57 PM PST 24 |
294167857 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1991386518 |
|
|
Jan 10 12:54:41 PM PST 24 |
Jan 10 12:55:52 PM PST 24 |
1655585896 ps |
| T74 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.949865288 |
|
|
Jan 10 12:54:32 PM PST 24 |
Jan 10 12:55:36 PM PST 24 |
54564741 ps |
| T75 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3438912240 |
|
|
Jan 10 12:54:50 PM PST 24 |
Jan 10 12:56:01 PM PST 24 |
761311441 ps |
| T76 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3287668933 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:32 PM PST 24 |
61521553 ps |
| T59 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4079702629 |
|
|
Jan 10 12:54:29 PM PST 24 |
Jan 10 12:55:36 PM PST 24 |
260796769 ps |
| T81 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3373124317 |
|
|
Jan 10 12:54:49 PM PST 24 |
Jan 10 12:55:56 PM PST 24 |
42127002 ps |
| T82 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.667895981 |
|
|
Jan 10 12:54:53 PM PST 24 |
Jan 10 12:55:59 PM PST 24 |
40020805 ps |
| T60 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3694561076 |
|
|
Jan 10 12:54:37 PM PST 24 |
Jan 10 12:55:45 PM PST 24 |
36367825 ps |
| T61 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2134092966 |
|
|
Jan 10 12:54:51 PM PST 24 |
Jan 10 12:55:59 PM PST 24 |
87732285 ps |
| T78 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2960783469 |
|
|
Jan 10 12:54:38 PM PST 24 |
Jan 10 12:55:44 PM PST 24 |
14796830 ps |
| T66 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2151846478 |
|
|
Jan 10 12:54:53 PM PST 24 |
Jan 10 12:56:02 PM PST 24 |
88305315 ps |
| T79 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2340766817 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:33 PM PST 24 |
19099877 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.659618369 |
|
|
Jan 10 12:54:27 PM PST 24 |
Jan 10 12:55:32 PM PST 24 |
17187763 ps |
| T67 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3715332412 |
|
|
Jan 10 12:54:26 PM PST 24 |
Jan 10 12:55:33 PM PST 24 |
32180357 ps |
| T126 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.566262233 |
|
|
Jan 10 12:54:31 PM PST 24 |
Jan 10 12:55:36 PM PST 24 |
143921119 ps |
| T124 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1346617628 |
|
|
Jan 10 12:54:45 PM PST 24 |
Jan 10 12:55:51 PM PST 24 |
672506124 ps |
| T121 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1410399145 |
|
|
Jan 10 12:55:02 PM PST 24 |
Jan 10 12:56:08 PM PST 24 |
38641905 ps |
| T145 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2431992889 |
|
|
Jan 10 12:54:34 PM PST 24 |
Jan 10 12:55:40 PM PST 24 |
122916716 ps |
| T88 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2025919268 |
|
|
Jan 10 12:56:49 PM PST 24 |
Jan 10 12:58:03 PM PST 24 |
795216917 ps |
| T123 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1476006293 |
|
|
Jan 10 12:54:30 PM PST 24 |
Jan 10 12:55:35 PM PST 24 |
345574777 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2556873665 |
|
|
Jan 10 12:54:32 PM PST 24 |
Jan 10 12:55:37 PM PST 24 |
91358596 ps |
| T176 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.972472471 |
|
|
Jan 10 12:54:55 PM PST 24 |
Jan 10 12:56:05 PM PST 24 |
400203381 ps |
| T177 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2193067451 |
|
|
Jan 10 12:54:37 PM PST 24 |
Jan 10 12:55:43 PM PST 24 |
36473480 ps |
| T178 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4082333485 |
|
|
Jan 10 12:54:29 PM PST 24 |
Jan 10 12:55:34 PM PST 24 |
17844866 ps |
| T179 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.29282279 |
|
|
Jan 10 12:54:42 PM PST 24 |
Jan 10 12:55:50 PM PST 24 |
283734601 ps |
| T180 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4235785294 |
|
|
Jan 10 12:54:55 PM PST 24 |
Jan 10 12:56:01 PM PST 24 |
19731589 ps |
| T181 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.758915713 |
|
|
Jan 10 12:54:42 PM PST 24 |
Jan 10 12:55:50 PM PST 24 |
35026653 ps |
| T131 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.51368293 |
|
|
Jan 10 12:54:53 PM PST 24 |
Jan 10 12:56:00 PM PST 24 |
973823915 ps |
| T89 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1271911377 |
|
|
Jan 10 12:54:36 PM PST 24 |
Jan 10 12:55:50 PM PST 24 |
863653053 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4166265322 |
|
|
Jan 10 12:54:33 PM PST 24 |
Jan 10 12:55:38 PM PST 24 |
71467882 ps |
| T182 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1078409581 |
|
|
Jan 10 12:54:40 PM PST 24 |
Jan 10 12:55:47 PM PST 24 |
33651576 ps |
| T183 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4102085746 |
|
|
Jan 10 12:54:54 PM PST 24 |
Jan 10 12:56:01 PM PST 24 |
88608212 ps |
| T100 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2902582630 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:35 PM PST 24 |
456521342 ps |
| T184 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.638175354 |
|
|
Jan 10 12:54:35 PM PST 24 |
Jan 10 12:55:41 PM PST 24 |
12694499 ps |
| T185 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3074849566 |
|
|
Jan 10 12:54:50 PM PST 24 |
Jan 10 12:55:58 PM PST 24 |
124970406 ps |
| T101 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1063267119 |
|
|
Jan 10 12:54:35 PM PST 24 |
Jan 10 12:55:45 PM PST 24 |
904025266 ps |
| T186 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2651586460 |
|
|
Jan 10 12:54:58 PM PST 24 |
Jan 10 12:56:05 PM PST 24 |
70372666 ps |
| T90 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1381440667 |
|
|
Jan 10 12:54:37 PM PST 24 |
Jan 10 12:55:47 PM PST 24 |
221495201 ps |
| T187 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3096142506 |
|
|
Jan 10 12:57:04 PM PST 24 |
Jan 10 12:58:16 PM PST 24 |
36655622 ps |
| T91 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3994081635 |
|
|
Jan 10 12:54:29 PM PST 24 |
Jan 10 12:55:34 PM PST 24 |
29822196 ps |
| T103 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4167326397 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:34 PM PST 24 |
43295464 ps |
| T188 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1435020979 |
|
|
Jan 10 12:54:33 PM PST 24 |
Jan 10 12:55:38 PM PST 24 |
39771576 ps |
| T189 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3665874464 |
|
|
Jan 10 12:54:42 PM PST 24 |
Jan 10 12:55:48 PM PST 24 |
33838780 ps |
| T190 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.567376063 |
|
|
Jan 10 12:54:36 PM PST 24 |
Jan 10 12:55:42 PM PST 24 |
81931834 ps |
| T191 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1380982831 |
|
|
Jan 10 12:54:31 PM PST 24 |
Jan 10 12:55:35 PM PST 24 |
35678674 ps |
| T132 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1860402266 |
|
|
Jan 10 12:54:42 PM PST 24 |
Jan 10 12:55:49 PM PST 24 |
639502353 ps |
| T192 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1371517271 |
|
|
Jan 10 12:54:35 PM PST 24 |
Jan 10 12:55:40 PM PST 24 |
25889160 ps |
| T193 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.395892514 |
|
|
Jan 10 12:54:46 PM PST 24 |
Jan 10 12:55:54 PM PST 24 |
238616492 ps |
| T194 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3232341230 |
|
|
Jan 10 12:54:33 PM PST 24 |
Jan 10 12:55:37 PM PST 24 |
142869024 ps |
| T195 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3711309707 |
|
|
Jan 10 12:54:38 PM PST 24 |
Jan 10 12:55:44 PM PST 24 |
111804167 ps |
| T196 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.846539619 |
|
|
Jan 10 12:54:43 PM PST 24 |
Jan 10 12:55:50 PM PST 24 |
31162549 ps |
| T92 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2415498172 |
|
|
Jan 10 12:55:03 PM PST 24 |
Jan 10 12:56:09 PM PST 24 |
36651838 ps |
| T197 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3737967939 |
|
|
Jan 10 12:54:45 PM PST 24 |
Jan 10 12:55:53 PM PST 24 |
142356579 ps |
| T198 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2369765267 |
|
|
Jan 10 12:54:36 PM PST 24 |
Jan 10 12:55:42 PM PST 24 |
309573252 ps |
| T199 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.154051459 |
|
|
Jan 10 12:54:52 PM PST 24 |
Jan 10 12:56:03 PM PST 24 |
1240149097 ps |
| T200 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.26451414 |
|
|
Jan 10 12:54:45 PM PST 24 |
Jan 10 12:55:57 PM PST 24 |
3885535500 ps |
| T201 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2441725708 |
|
|
Jan 10 12:54:37 PM PST 24 |
Jan 10 12:55:42 PM PST 24 |
12136706 ps |
| T127 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1017187995 |
|
|
Jan 10 12:54:53 PM PST 24 |
Jan 10 12:56:00 PM PST 24 |
104041985 ps |
| T202 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.924628758 |
|
|
Jan 10 12:54:42 PM PST 24 |
Jan 10 12:55:48 PM PST 24 |
20551078 ps |
| T129 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.944965597 |
|
|
Jan 10 12:54:41 PM PST 24 |
Jan 10 12:55:49 PM PST 24 |
104703722 ps |
| T203 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1989636685 |
|
|
Jan 10 12:54:31 PM PST 24 |
Jan 10 12:55:36 PM PST 24 |
182463576 ps |
| T204 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2365594616 |
|
|
Jan 10 12:54:31 PM PST 24 |
Jan 10 12:55:39 PM PST 24 |
120851929 ps |
| T102 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.665148491 |
|
|
Jan 10 12:54:31 PM PST 24 |
Jan 10 12:55:37 PM PST 24 |
143792071 ps |
| T205 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2228997532 |
|
|
Jan 10 12:54:51 PM PST 24 |
Jan 10 12:55:58 PM PST 24 |
28142079 ps |
| T206 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2256568251 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:34 PM PST 24 |
136732412 ps |
| T207 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1892735580 |
|
|
Jan 10 12:57:05 PM PST 24 |
Jan 10 12:58:18 PM PST 24 |
26640242 ps |
| T208 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1423194789 |
|
|
Jan 10 12:54:35 PM PST 24 |
Jan 10 12:55:40 PM PST 24 |
99571226 ps |
| T209 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2380015388 |
|
|
Jan 10 12:54:35 PM PST 24 |
Jan 10 12:55:41 PM PST 24 |
247341008 ps |
| T93 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3101515076 |
|
|
Jan 10 12:54:36 PM PST 24 |
Jan 10 12:55:45 PM PST 24 |
485051490 ps |
| T210 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1264112283 |
|
|
Jan 10 12:54:27 PM PST 24 |
Jan 10 12:55:32 PM PST 24 |
45380289 ps |
| T211 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2082147918 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:33 PM PST 24 |
15419790 ps |
| T128 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2931426483 |
|
|
Jan 10 12:54:36 PM PST 24 |
Jan 10 12:55:43 PM PST 24 |
676279765 ps |
| T212 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.229247609 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:33 PM PST 24 |
589027211 ps |
| T94 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.34420374 |
|
|
Jan 10 12:54:46 PM PST 24 |
Jan 10 12:55:54 PM PST 24 |
222046514 ps |
| T213 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2484020618 |
|
|
Jan 10 12:56:49 PM PST 24 |
Jan 10 12:58:04 PM PST 24 |
418160835 ps |
| T214 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3909814533 |
|
|
Jan 10 12:54:35 PM PST 24 |
Jan 10 12:55:41 PM PST 24 |
187954986 ps |
| T215 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1020547399 |
|
|
Jan 10 12:54:49 PM PST 24 |
Jan 10 12:55:56 PM PST 24 |
105634743 ps |
| T216 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2327456622 |
|
|
Jan 10 12:54:40 PM PST 24 |
Jan 10 12:55:47 PM PST 24 |
38370295 ps |
| T217 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3894071158 |
|
|
Jan 10 12:54:30 PM PST 24 |
Jan 10 12:55:36 PM PST 24 |
258223640 ps |
| T218 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2933550548 |
|
|
Jan 10 12:54:46 PM PST 24 |
Jan 10 12:55:53 PM PST 24 |
61418895 ps |
| T130 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2885818256 |
|
|
Jan 10 12:55:03 PM PST 24 |
Jan 10 12:56:10 PM PST 24 |
389386354 ps |
| T219 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1619638349 |
|
|
Jan 10 12:54:53 PM PST 24 |
Jan 10 12:56:01 PM PST 24 |
59219000 ps |
| T220 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2291356232 |
|
|
Jan 10 12:54:30 PM PST 24 |
Jan 10 12:55:37 PM PST 24 |
597347495 ps |
| T221 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4037858714 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:37 PM PST 24 |
2071198644 ps |
| T222 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2113482094 |
|
|
Jan 10 12:57:06 PM PST 24 |
Jan 10 12:58:18 PM PST 24 |
24730878 ps |
| T104 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1065249099 |
|
|
Jan 10 12:54:30 PM PST 24 |
Jan 10 12:55:39 PM PST 24 |
456029481 ps |
| T105 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4128888366 |
|
|
Jan 10 12:54:41 PM PST 24 |
Jan 10 12:55:52 PM PST 24 |
841929148 ps |
| T223 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3930037875 |
|
|
Jan 10 12:54:51 PM PST 24 |
Jan 10 12:55:57 PM PST 24 |
14652981 ps |
| T224 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.628918306 |
|
|
Jan 10 12:54:59 PM PST 24 |
Jan 10 12:56:06 PM PST 24 |
245898460 ps |
| T225 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1752084226 |
|
|
Jan 10 12:54:57 PM PST 24 |
Jan 10 12:56:03 PM PST 24 |
124345145 ps |
| T226 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.220514700 |
|
|
Jan 10 12:54:43 PM PST 24 |
Jan 10 12:55:49 PM PST 24 |
364716513 ps |
| T227 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2522128167 |
|
|
Jan 10 12:54:52 PM PST 24 |
Jan 10 12:56:00 PM PST 24 |
26288335 ps |
| T228 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.715499492 |
|
|
Jan 10 12:56:49 PM PST 24 |
Jan 10 12:58:05 PM PST 24 |
819659686 ps |
| T106 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3388397703 |
|
|
Jan 10 12:54:31 PM PST 24 |
Jan 10 12:55:36 PM PST 24 |
37209194 ps |
| T229 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2226919905 |
|
|
Jan 10 12:54:48 PM PST 24 |
Jan 10 12:55:55 PM PST 24 |
16329903 ps |
| T230 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.723327493 |
|
|
Jan 10 12:54:50 PM PST 24 |
Jan 10 12:55:56 PM PST 24 |
22155493 ps |
| T231 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2435857601 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:33 PM PST 24 |
43475385 ps |
| T232 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.321057144 |
|
|
Jan 10 12:54:50 PM PST 24 |
Jan 10 12:55:57 PM PST 24 |
22382481 ps |
| T233 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1137132336 |
|
|
Jan 10 12:54:48 PM PST 24 |
Jan 10 12:55:55 PM PST 24 |
106819649 ps |
| T234 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2588373143 |
|
|
Jan 10 12:54:30 PM PST 24 |
Jan 10 12:55:35 PM PST 24 |
23036995 ps |
| T235 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4006993094 |
|
|
Jan 10 12:54:29 PM PST 24 |
Jan 10 12:55:34 PM PST 24 |
102517196 ps |
| T236 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3725401957 |
|
|
Jan 10 12:54:35 PM PST 24 |
Jan 10 12:55:42 PM PST 24 |
30032109 ps |
| T237 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.529454251 |
|
|
Jan 10 12:54:47 PM PST 24 |
Jan 10 12:55:54 PM PST 24 |
230415646 ps |
| T238 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3028391345 |
|
|
Jan 10 12:54:27 PM PST 24 |
Jan 10 12:55:32 PM PST 24 |
56995788 ps |
| T239 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1434827076 |
|
|
Jan 10 12:54:52 PM PST 24 |
Jan 10 12:56:07 PM PST 24 |
1424322841 ps |
| T240 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3310366464 |
|
|
Jan 10 12:54:52 PM PST 24 |
Jan 10 12:56:00 PM PST 24 |
317058954 ps |
| T107 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2162770628 |
|
|
Jan 10 12:54:50 PM PST 24 |
Jan 10 12:56:06 PM PST 24 |
1511993807 ps |
| T241 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3579375550 |
|
|
Jan 10 12:54:32 PM PST 24 |
Jan 10 12:55:36 PM PST 24 |
18150006 ps |
| T242 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1400993610 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:42 PM PST 24 |
2132351502 ps |
| T243 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1860680660 |
|
|
Jan 10 12:54:30 PM PST 24 |
Jan 10 12:55:35 PM PST 24 |
20024660 ps |
| T244 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3651273520 |
|
|
Jan 10 12:54:36 PM PST 24 |
Jan 10 12:55:41 PM PST 24 |
46661860 ps |
| T245 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4127819036 |
|
|
Jan 10 12:54:32 PM PST 24 |
Jan 10 12:55:37 PM PST 24 |
36365524 ps |
| T246 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.414392282 |
|
|
Jan 10 12:54:43 PM PST 24 |
Jan 10 12:55:50 PM PST 24 |
1282472017 ps |
| T247 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3865500781 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:35 PM PST 24 |
329946188 ps |
| T248 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3969591305 |
|
|
Jan 10 12:54:28 PM PST 24 |
Jan 10 12:55:33 PM PST 24 |
13373761 ps |
| T249 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2648928808 |
|
|
Jan 10 12:54:30 PM PST 24 |
Jan 10 12:55:37 PM PST 24 |
111691701 ps |
| T250 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.570080202 |
|
|
Jan 10 12:54:31 PM PST 24 |
Jan 10 12:55:37 PM PST 24 |
27166875 ps |
| T251 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2393916551 |
|
|
Jan 10 12:46:50 PM PST 24 |
Jan 10 12:48:08 PM PST 24 |
43722476 ps |
| T252 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2873042346 |
|
|
Jan 10 12:45:00 PM PST 24 |
Jan 10 12:46:30 PM PST 24 |
548660860 ps |
| T253 |
/workspace/coverage/default/12.sram_ctrl_bijection.935016953 |
|
|
Jan 10 12:45:08 PM PST 24 |
Jan 10 12:47:28 PM PST 24 |
9842208901 ps |
| T254 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.985289088 |
|
|
Jan 10 12:45:47 PM PST 24 |
Jan 10 12:49:43 PM PST 24 |
1741994855 ps |
| T255 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3848029084 |
|
|
Jan 10 12:45:00 PM PST 24 |
Jan 10 12:46:28 PM PST 24 |
171305039 ps |
| T256 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.152999820 |
|
|
Jan 10 12:46:13 PM PST 24 |
Jan 10 12:53:56 PM PST 24 |
2524210786 ps |
| T28 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.187642309 |
|
|
Jan 10 12:44:47 PM PST 24 |
Jan 10 12:46:08 PM PST 24 |
722267910 ps |
| T39 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3895152807 |
|
|
Jan 10 12:47:12 PM PST 24 |
Jan 10 12:49:40 PM PST 24 |
4195371994 ps |
| T40 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3367737109 |
|
|
Jan 10 12:45:06 PM PST 24 |
Jan 10 12:52:11 PM PST 24 |
5532002245 ps |
| T41 |
/workspace/coverage/default/4.sram_ctrl_smoke.685508407 |
|
|
Jan 10 12:44:52 PM PST 24 |
Jan 10 12:46:23 PM PST 24 |
146399630 ps |
| T42 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.4217779821 |
|
|
Jan 10 12:46:01 PM PST 24 |
Jan 10 01:00:10 PM PST 24 |
36329733789 ps |
| T43 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3033400245 |
|
|
Jan 10 12:46:46 PM PST 24 |
Jan 10 12:48:09 PM PST 24 |
83736034 ps |
| T44 |
/workspace/coverage/default/19.sram_ctrl_smoke.3339459619 |
|
|
Jan 10 12:45:52 PM PST 24 |
Jan 10 12:48:24 PM PST 24 |
417684653 ps |
| T45 |
/workspace/coverage/default/47.sram_ctrl_stress_all.339821517 |
|
|
Jan 10 12:47:06 PM PST 24 |
Jan 10 01:19:47 PM PST 24 |
5882246795 ps |
| T46 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1922537640 |
|
|
Jan 10 12:45:37 PM PST 24 |
Jan 10 12:48:42 PM PST 24 |
1594694337 ps |
| T47 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1767861208 |
|
|
Jan 10 12:45:00 PM PST 24 |
Jan 10 12:46:28 PM PST 24 |
721777328 ps |
| T257 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.4293863415 |
|
|
Jan 10 12:45:19 PM PST 24 |
Jan 10 12:46:45 PM PST 24 |
111214958 ps |
| T258 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3770990174 |
|
|
Jan 10 12:47:13 PM PST 24 |
Jan 10 01:13:42 PM PST 24 |
37879693982 ps |
| T259 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.4044088863 |
|
|
Jan 10 12:46:25 PM PST 24 |
Jan 10 12:50:59 PM PST 24 |
2200105223 ps |
| T260 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3714088193 |
|
|
Jan 10 12:45:07 PM PST 24 |
Jan 10 12:47:02 PM PST 24 |
104943775 ps |
| T31 |
/workspace/coverage/default/18.sram_ctrl_stress_all.1583607045 |
|
|
Jan 10 12:45:53 PM PST 24 |
Jan 10 01:53:07 PM PST 24 |
13716885337 ps |
| T48 |
/workspace/coverage/default/45.sram_ctrl_executable.3101815001 |
|
|
Jan 10 12:46:56 PM PST 24 |
Jan 10 01:03:52 PM PST 24 |
73614454049 ps |
| T261 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.3723070389 |
|
|
Jan 10 12:46:20 PM PST 24 |
Jan 10 12:47:44 PM PST 24 |
225774858 ps |
| T138 |
/workspace/coverage/default/29.sram_ctrl_regwen.1311140097 |
|
|
Jan 10 12:46:14 PM PST 24 |
Jan 10 01:00:41 PM PST 24 |
22847564961 ps |
| T262 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3984888539 |
|
|
Jan 10 12:45:23 PM PST 24 |
Jan 10 12:47:50 PM PST 24 |
283649102 ps |
| T263 |
/workspace/coverage/default/39.sram_ctrl_bijection.105458531 |
|
|
Jan 10 12:47:05 PM PST 24 |
Jan 10 12:49:50 PM PST 24 |
9381921249 ps |
| T264 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1751620161 |
|
|
Jan 10 12:46:19 PM PST 24 |
Jan 10 12:47:36 PM PST 24 |
48181790 ps |
| T120 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3341226099 |
|
|
Jan 10 12:44:35 PM PST 24 |
Jan 10 02:08:13 PM PST 24 |
4760998267 ps |
| T265 |
/workspace/coverage/default/31.sram_ctrl_partial_access.412040253 |
|
|
Jan 10 12:46:24 PM PST 24 |
Jan 10 12:48:42 PM PST 24 |
991794751 ps |