Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42549087	1			T1	102729		T2	9162		T3	6142
triple_byte_access	2486871	1			T1	2023		T4	2407		T5	151
halfword_access	3733497	1			T1	3081		T4	3600		T5	235
byte_access	4986646	1			T1	4100		T4	4722		T5	322
zero_access	1255844	1			T1	1024		T4	1183		T5	62

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27446877

1

T1

56372

T2

4577

T3

2048

auto[1]

27565068

1

T1

56585

T2

4585

T3

4094

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21223126	1			T1	51236		T2	4577		T3	2048
auto[0]	triple_byte_access	1238855	1			T1	999		T4	1192		T5	78
auto[0]	halfword_access	1862495	1			T1	1522		T4	1797		T5	104
auto[0]	byte_access	2491104	1			T1	2094		T4	2304		T5	166
auto[0]	zero_access	631297	1			T1	521		T4	554		T5	32
auto[1]	word_access	21325961	1			T1	51493		T2	4585		T3	4094
auto[1]	triple_byte_access	1248016	1			T1	1024		T4	1215		T5	73
auto[1]	halfword_access	1871002	1			T1	1559		T4	1803		T5	131
auto[1]	byte_access	2495542	1			T1	2006		T4	2418		T5	156
auto[1]	zero_access	624547	1			T1	503		T4	629		T5	30