Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13917614	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58698000

1

T1

53

T2

12288

T3

524916

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36203293	1			T1	384		T2	6144		T3	287885
values[0x0]	16818364	1			T1	204		T2	3066		T3	138910
values[0x1]	19593957	1			T1	431		T2	3078		T3	148443

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6936010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65679604

1

T1

490

T2

12288

T3

550143

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	293744	1			T1	4		T2	29		T3	1140
valid_sources[0x01]	304573	1			T1	1		T2	46		T3	1181
valid_sources[0x02]	247069	1			T1	8		T2	71		T3	988
valid_sources[0x03]	281418	1			T2	62		T3	1152		T4	11
valid_sources[0x04]	263635	1			T1	2		T2	41		T3	995
valid_sources[0x05]	268359	1			T1	6		T2	75		T3	1036
valid_sources[0x06]	271963	1			T1	5		T2	46		T3	1109
valid_sources[0x07]	291751	1			T1	4		T2	49		T3	826
valid_sources[0x08]	279641	1			T1	3		T2	39		T3	944
valid_sources[0x09]	326557	1			T1	8		T2	44		T3	32417
valid_sources[0x0a]	240153	1			T1	4		T2	60		T3	1038
valid_sources[0x0b]	330760	1			T1	3		T2	65		T3	1045
valid_sources[0x0c]	274290	1			T1	3		T2	50		T3	869
valid_sources[0x0d]	247537	1			T1	4		T2	60		T3	894
valid_sources[0x0e]	254344	1			T1	4		T2	65		T3	887
valid_sources[0x0f]	240715	1			T1	4		T2	47		T3	1052
valid_sources[0x10]	297541	1			T1	2		T2	45		T3	904
valid_sources[0x11]	249873	1			T1	4		T2	41		T3	1014
valid_sources[0x12]	318797	1			T1	2		T2	60		T3	840
valid_sources[0x13]	274523	1			T1	1		T2	50		T3	899
valid_sources[0x14]	345059	1			T2	40		T3	991		T4	14
valid_sources[0x15]	262849	1			T1	3		T2	47		T3	984
valid_sources[0x16]	291623	1			T1	2		T2	42		T3	859
valid_sources[0x17]	339184	1			T1	5		T2	52		T3	1027
valid_sources[0x18]	281104	1			T1	2		T2	75		T3	914
valid_sources[0x19]	237377	1			T1	5		T2	43		T3	1086
valid_sources[0x1a]	280365	1			T1	3		T2	35		T3	1050
valid_sources[0x1b]	267084	1			T1	5		T2	30		T3	1678
valid_sources[0x1c]	285242	1			T1	6		T2	58		T3	959
valid_sources[0x1d]	277580	1			T1	5		T2	33		T3	1061
valid_sources[0x1e]	273293	1			T1	3		T2	39		T3	985
valid_sources[0x1f]	292721	1			T1	5		T2	57		T3	994
valid_sources[0x20]	278185	1			T1	4		T2	45		T3	1091
valid_sources[0x21]	293170	1			T1	3		T2	35		T3	1064
valid_sources[0x22]	274378	1			T1	2		T2	70		T3	1030
valid_sources[0x23]	302465	1			T1	8		T2	62		T3	17986
valid_sources[0x24]	330547	1			T1	7		T2	50		T3	956
valid_sources[0x25]	247638	1			T1	5		T2	51		T3	1021
valid_sources[0x26]	345526	1			T1	4		T2	28		T3	1169
valid_sources[0x27]	274451	1			T1	5		T2	50		T3	22711
valid_sources[0x28]	284729	1			T1	6		T2	56		T3	848
valid_sources[0x29]	261218	1			T1	3		T2	54		T3	1081
valid_sources[0x2a]	296608	1			T1	2		T2	41		T3	1190
valid_sources[0x2b]	296024	1			T1	1		T2	47		T3	1245
valid_sources[0x2c]	302346	1			T1	7		T2	47		T3	978
valid_sources[0x2d]	295677	1			T1	2		T2	37		T3	1033
valid_sources[0x2e]	281263	1			T1	1		T2	76		T3	1020
valid_sources[0x2f]	340754	1			T1	3		T2	69		T3	1132
valid_sources[0x30]	305205	1			T1	3		T2	38		T3	4190
valid_sources[0x31]	281624	1			T2	41		T3	969		T4	14
valid_sources[0x32]	248580	1			T1	3		T2	36		T3	950
valid_sources[0x33]	275213	1			T1	5		T2	35		T3	849
valid_sources[0x34]	236545	1			T1	6		T2	57		T3	947
valid_sources[0x35]	277804	1			T1	1		T2	79		T3	10672
valid_sources[0x36]	301607	1			T1	2		T2	44		T3	1057
valid_sources[0x37]	318256	1			T1	10		T2	51		T3	19068
valid_sources[0x38]	333156	1			T1	6		T2	28		T3	950
valid_sources[0x39]	264622	1			T1	9		T2	48		T3	1033
valid_sources[0x3a]	270614	1			T1	6		T2	46		T3	894
valid_sources[0x3b]	307866	1			T1	7		T2	72		T3	1028
valid_sources[0x3c]	264885	1			T1	5		T2	46		T3	1120
valid_sources[0x3d]	263518	1			T1	3		T2	25		T3	1019
valid_sources[0x3e]	356869	1			T1	6		T2	50		T3	10675
valid_sources[0x3f]	285080	1			T1	4		T2	55		T3	1080
valid_sources[0x40]	254005	1			T1	7		T2	54		T3	951
valid_sources[0x41]	286037	1			T1	7		T2	54		T3	999
valid_sources[0x42]	266337	1			T1	3		T2	34		T3	983
valid_sources[0x43]	317104	1			T1	3		T2	35		T3	919
valid_sources[0x44]	315108	1			T1	7		T2	41		T3	1135
valid_sources[0x45]	285532	1			T1	5		T2	24		T3	1011
valid_sources[0x46]	267038	1			T1	3		T2	42		T3	1159
valid_sources[0x47]	277379	1			T1	2		T2	41		T3	1202
valid_sources[0x48]	264419	1			T1	3		T2	62		T3	932
valid_sources[0x49]	312135	1			T1	4		T2	34		T3	980
valid_sources[0x4a]	258261	1			T1	3		T2	62		T3	1015
valid_sources[0x4b]	285009	1			T2	53		T3	1135		T4	8
valid_sources[0x4c]	283152	1			T1	9		T2	38		T3	5862
valid_sources[0x4d]	247711	1			T1	1		T2	38		T3	958
valid_sources[0x4e]	268476	1			T1	6		T2	41		T3	1011
valid_sources[0x4f]	237440	1			T1	6		T2	53		T3	848
valid_sources[0x50]	276075	1			T1	6		T2	54		T3	19391
valid_sources[0x51]	242002	1			T1	1		T2	49		T3	1097
valid_sources[0x52]	250738	1			T1	8		T2	63		T3	1056
valid_sources[0x53]	254980	1			T1	5		T2	41		T3	968
valid_sources[0x54]	304162	1			T1	6		T2	53		T3	928
valid_sources[0x55]	260200	1			T1	2		T2	46		T3	1064
valid_sources[0x56]	355345	1			T1	3		T2	24		T3	895
valid_sources[0x57]	296377	1			T1	4		T2	55		T3	1086
valid_sources[0x58]	268663	1			T1	2		T2	54		T3	1099
valid_sources[0x59]	297519	1			T1	2		T2	58		T3	1016
valid_sources[0x5a]	320779	1			T1	6		T2	53		T3	954
valid_sources[0x5b]	303266	1			T1	3		T2	64		T3	952
valid_sources[0x5c]	273998	1			T1	3		T2	41		T3	1018
valid_sources[0x5d]	325700	1			T1	1		T2	28		T3	1214
valid_sources[0x5e]	285562	1			T1	3		T2	29		T3	14325
valid_sources[0x5f]	288039	1			T1	7		T2	54		T3	972
valid_sources[0x60]	332003	1			T1	2		T2	54		T3	1052
valid_sources[0x61]	258329	1			T1	3		T2	46		T3	962
valid_sources[0x62]	344163	1			T1	6		T2	80		T3	1028
valid_sources[0x63]	334673	1			T1	5		T2	45		T3	960
valid_sources[0x64]	271034	1			T1	3		T2	26		T3	902
valid_sources[0x65]	261337	1			T1	2		T2	36		T3	1097
valid_sources[0x66]	332360	1			T1	5		T2	61		T3	1103
valid_sources[0x67]	247680	1			T1	1		T2	67		T3	934
valid_sources[0x68]	270910	1			T1	2		T2	33		T3	923
valid_sources[0x69]	267004	1			T1	4		T2	24		T3	1065
valid_sources[0x6a]	329632	1			T1	4		T2	71		T3	1194
valid_sources[0x6b]	272914	1			T1	7		T2	48		T3	801
valid_sources[0x6c]	344405	1			T1	7		T2	38		T3	972
valid_sources[0x6d]	305982	1			T1	3		T2	41		T3	871
valid_sources[0x6e]	356367	1			T1	7		T2	57		T3	964
valid_sources[0x6f]	279569	1			T1	3		T2	40		T3	1063
valid_sources[0x70]	261844	1			T1	4		T2	35		T3	1098
valid_sources[0x71]	282484	1			T1	6		T2	41		T3	1061
valid_sources[0x72]	316339	1			T1	6		T2	36		T3	1174
valid_sources[0x73]	263763	1			T1	6		T2	21		T3	1051
valid_sources[0x74]	246392	1			T1	3		T2	41		T3	811
valid_sources[0x75]	324077	1			T1	3		T2	59		T3	1252
valid_sources[0x76]	308258	1			T1	10		T2	70		T3	1065
valid_sources[0x77]	273539	1			T1	7		T2	41		T3	1019
valid_sources[0x78]	239898	1			T1	6		T2	71		T3	1066
valid_sources[0x79]	301004	1			T1	3		T2	50		T3	831
valid_sources[0x7a]	276499	1			T1	4		T2	60		T3	9957
valid_sources[0x7b]	254031	1			T1	4		T2	60		T3	1184
valid_sources[0x7c]	261452	1			T1	1		T2	65		T3	1022
valid_sources[0x7d]	240482	1			T1	1		T2	39		T3	1144
valid_sources[0x7e]	250308	1			T1	3		T2	73		T3	1136
valid_sources[0x7f]	276674	1			T1	2		T2	82		T3	1255
valid_sources[0x80]	248383	1			T1	2		T2	57		T3	851

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29249366

1

T1

3

T2

6144

T3

262659

values[0x0]

all_enables

biggest_size

14728553

1

T1

22

T2

3066

T3

131235

values[0x1]

all_enables

biggest_size

14720081

1

T1

28

T2

3078

T3

131022

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2266583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140295

1

T1

1

T2

1

T3

105

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2285249	1			T1	148		T2	1322		T3	6120
values[0x0]	58960	1			T2	2		T3	104		T4	11
values[0x1]	62669	1			T1	1		T2	4		T3	120

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1514572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

892306

1

T1

44

T2

436

T3

2202

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7703	1			T1	1		T2	4		T3	25
valid_sources[0x01]	7006	1			T2	8		T3	20		T5	23
valid_sources[0x02]	7957	1			T1	2		T2	6		T3	22
valid_sources[0x03]	7765	1			T2	2		T3	14		T5	1
valid_sources[0x04]	17565	1			T2	4		T3	15		T5	10
valid_sources[0x05]	9366	1			T2	4		T3	19		T5	4
valid_sources[0x06]	52928	1			T2	8		T3	16		T5	6
valid_sources[0x07]	7381	1			T1	1		T2	7		T3	23
valid_sources[0x08]	14415	1			T2	1		T3	20		T5	16
valid_sources[0x09]	8173	1			T2	7		T3	23		T5	10
valid_sources[0x0a]	7797	1			T2	4		T3	25		T5	12
valid_sources[0x0b]	7543	1			T1	2		T2	5		T3	26
valid_sources[0x0c]	6909	1			T2	8		T3	23		T5	1
valid_sources[0x0d]	7309	1			T2	2		T3	21		T5	12
valid_sources[0x0e]	10880	1			T2	3		T3	23		T5	5
valid_sources[0x0f]	7060	1			T1	2		T2	4		T3	51
valid_sources[0x10]	11033	1			T2	10		T3	31		T5	15
valid_sources[0x11]	9667	1			T2	4		T3	22		T5	4
valid_sources[0x12]	8094	1			T2	6		T3	27		T5	13
valid_sources[0x13]	9956	1			T2	5		T3	14		T5	2
valid_sources[0x14]	18844	1			T1	3		T2	6		T3	32
valid_sources[0x15]	9250	1			T2	2		T3	27		T5	3
valid_sources[0x16]	7169	1			T2	6		T3	29		T5	6
valid_sources[0x17]	20137	1			T2	2		T3	18		T5	10
valid_sources[0x18]	7796	1			T2	4		T3	22		T5	18
valid_sources[0x19]	22372	1			T1	1		T2	7		T3	28
valid_sources[0x1a]	7889	1			T2	2		T3	21		T5	7
valid_sources[0x1b]	7816	1			T2	5		T3	23		T5	18
valid_sources[0x1c]	7583	1			T1	2		T2	3		T3	22
valid_sources[0x1d]	8849	1			T2	4		T3	27		T5	11
valid_sources[0x1e]	9464	1			T2	9		T3	27		T5	6
valid_sources[0x1f]	8556	1			T2	7		T3	28		T5	6
valid_sources[0x20]	8418	1			T1	1		T2	7		T3	22
valid_sources[0x21]	11259	1			T2	2		T3	43		T5	4
valid_sources[0x22]	8118	1			T2	4		T3	15		T5	7
valid_sources[0x23]	7952	1			T2	1		T3	26		T5	22
valid_sources[0x24]	8765	1			T1	4		T2	3		T3	32
valid_sources[0x25]	8792	1			T1	4		T2	4		T3	18
valid_sources[0x26]	8190	1			T2	13		T3	42		T5	17
valid_sources[0x27]	20187	1			T1	2		T2	16		T3	21
valid_sources[0x28]	17031	1			T2	4		T3	15		T5	9
valid_sources[0x29]	7495	1			T1	1		T2	2		T3	28
valid_sources[0x2a]	12617	1			T1	1		T2	2		T3	26
valid_sources[0x2b]	7258	1			T1	2		T2	4		T3	15
valid_sources[0x2c]	7804	1			T2	2		T3	19		T5	8
valid_sources[0x2d]	8206	1			T1	1		T2	12		T3	17
valid_sources[0x2e]	8414	1			T2	6		T3	21		T5	8
valid_sources[0x2f]	7589	1			T2	4		T3	32		T5	13
valid_sources[0x30]	9815	1			T1	1		T2	4		T3	23
valid_sources[0x31]	7174	1			T1	2		T2	2		T3	14
valid_sources[0x32]	6934	1			T1	3		T2	5		T3	24
valid_sources[0x33]	8953	1			T2	2		T3	26		T5	10
valid_sources[0x34]	7549	1			T1	2		T2	5		T3	22
valid_sources[0x35]	8345	1			T1	1		T2	10		T3	40
valid_sources[0x36]	7024	1			T2	7		T3	17		T5	9
valid_sources[0x37]	7316	1			T1	2		T2	2		T3	26
valid_sources[0x38]	7243	1			T2	2		T3	14		T5	25
valid_sources[0x39]	9831	1			T1	1		T2	2		T3	23
valid_sources[0x3a]	7103	1			T1	1		T2	3		T3	23
valid_sources[0x3b]	7340	1			T1	1		T2	3		T3	20
valid_sources[0x3c]	14178	1			T2	7		T3	19		T5	10
valid_sources[0x3d]	7617	1			T2	5		T3	29		T5	1
valid_sources[0x3e]	7138	1			T1	5		T2	1		T3	24
valid_sources[0x3f]	7836	1			T1	1		T2	7		T3	39
valid_sources[0x40]	7872	1			T2	6		T3	21		T5	18
valid_sources[0x41]	17436	1			T1	1		T2	7		T3	28
valid_sources[0x42]	7202	1			T1	1		T2	8		T3	13
valid_sources[0x43]	6645	1			T2	12		T3	20		T5	7
valid_sources[0x44]	7154	1			T1	1		T2	9		T3	20
valid_sources[0x45]	10022	1			T1	1		T2	4		T3	28
valid_sources[0x46]	7809	1			T2	11		T3	25		T5	6
valid_sources[0x47]	7279	1			T2	6		T3	35		T5	11
valid_sources[0x48]	9452	1			T2	6		T3	18		T5	8
valid_sources[0x49]	7358	1			T1	1		T2	7		T3	32
valid_sources[0x4a]	15944	1			T1	4		T2	3		T3	20
valid_sources[0x4b]	6961	1			T2	5		T3	26		T5	7
valid_sources[0x4c]	7685	1			T2	12		T3	25		T5	5
valid_sources[0x4d]	8371	1			T2	5		T3	18		T5	13
valid_sources[0x4e]	7800	1			T2	8		T3	22		T5	16
valid_sources[0x4f]	8804	1			T1	2		T2	4		T3	26
valid_sources[0x50]	7757	1			T2	3		T3	33		T5	11
valid_sources[0x51]	7664	1			T1	3		T2	10		T3	21
valid_sources[0x52]	7162	1			T2	6		T3	22		T5	10
valid_sources[0x53]	8384	1			T1	1		T2	4		T3	20
valid_sources[0x54]	8534	1			T1	1		T2	5		T3	27
valid_sources[0x55]	7982	1			T2	4		T3	20		T5	10
valid_sources[0x56]	8008	1			T1	1		T2	6		T3	28
valid_sources[0x57]	7618	1			T2	9		T3	36		T5	5
valid_sources[0x58]	7440	1			T1	1		T2	4		T3	28
valid_sources[0x59]	9314	1			T2	11		T3	28		T5	4
valid_sources[0x5a]	7490	1			T2	9		T3	36		T5	23
valid_sources[0x5b]	7700	1			T2	8		T3	20		T5	9
valid_sources[0x5c]	7811	1			T1	2		T2	3		T3	33
valid_sources[0x5d]	15233	1			T2	3		T3	22		T5	9
valid_sources[0x5e]	7227	1			T2	7		T3	21		T5	7
valid_sources[0x5f]	8563	1			T2	5		T3	29		T6	5
valid_sources[0x60]	24629	1			T2	2		T3	30		T5	6
valid_sources[0x61]	7980	1			T1	4		T2	5		T3	26
valid_sources[0x62]	9282	1			T2	1		T3	17		T5	16
valid_sources[0x63]	6814	1			T2	3		T3	31		T5	16
valid_sources[0x64]	7306	1			T1	2		T2	9		T3	25
valid_sources[0x65]	9090	1			T1	3		T2	9		T3	24
valid_sources[0x66]	7707	1			T2	6		T3	28		T5	9
valid_sources[0x67]	7154	1			T2	7		T3	26		T5	17
valid_sources[0x68]	8706	1			T2	6		T3	31		T5	10
valid_sources[0x69]	11085	1			T2	6		T3	37		T5	14
valid_sources[0x6a]	9504	1			T2	8		T3	20		T5	8
valid_sources[0x6b]	7434	1			T1	1		T2	2		T3	44
valid_sources[0x6c]	7997	1			T2	11		T3	20		T5	12
valid_sources[0x6d]	9135	1			T2	6		T3	20		T5	10
valid_sources[0x6e]	7045	1			T2	5		T3	26		T5	14
valid_sources[0x6f]	7122	1			T1	1		T2	11		T3	21
valid_sources[0x70]	13648	1			T1	2		T2	1		T3	15
valid_sources[0x71]	7490	1			T1	1		T2	4		T3	29
valid_sources[0x72]	8835	1			T1	1		T2	5		T3	16
valid_sources[0x73]	7992	1			T2	4		T3	29		T5	2
valid_sources[0x74]	7309	1			T2	7		T3	31		T5	13
valid_sources[0x75]	7181	1			T2	9		T3	30		T5	1
valid_sources[0x76]	10023	1			T2	4		T3	52		T5	5
valid_sources[0x77]	13411	1			T2	5		T3	35		T5	7
valid_sources[0x78]	9132	1			T1	1		T2	8		T3	26
valid_sources[0x79]	8154	1			T2	7		T3	21		T5	2
valid_sources[0x7a]	8065	1			T2	2		T3	22		T5	4
valid_sources[0x7b]	15411	1			T1	1		T2	5		T3	30
valid_sources[0x7c]	8825	1			T2	5		T3	15		T5	10
valid_sources[0x7d]	8603	1			T2	5		T3	23		T5	18
valid_sources[0x7e]	18015	1			T2	9		T3	23		T5	4
valid_sources[0x7f]	7036	1			T2	4		T3	23		T5	4
valid_sources[0x80]	9091	1			T2	9		T3	22		T5	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37984

1

T3

52

T4

10

T5

10

values[0x0]

all_enables

biggest_size

51858

1

T2

1

T3

37

T4

1

values[0x1]

all_enables

biggest_size

50453

1

T1

1

T3

16

T4

2