Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13618052

1

T1

966

T3

42926

T4

66

full_word

53764416

1

T1

53

T2

12288

T3

452026

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67382188	1			T1	1019		T2	12288		T3	494952
auto[TlIntgErrCmd]	81	1			T37	5		T38	6		T39	7
auto[TlIntgErrData]	107	1			T37	5		T38	2		T39	6
auto[TlIntgErrBoth]	92	1			T38	2		T39	7		T107	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30894221

1

T1

384

T2

6144

T3

209962

auto[1]

36488247

1

T1

635

T2

6144

T3

284990

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6506991	1			T1	381		T3	18051		T4	35
auto[TlIntgErrNone]	partial	auto[1]	7110812	1			T1	585		T3	24875		T4	31
auto[TlIntgErrNone]	full_word	auto[0]	24387105	1			T1	3		T2	6144		T3	191911
auto[TlIntgErrNone]	full_word	auto[1]	29377280	1			T1	50		T2	6144		T3	260115
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T37	2		T38	3		T39	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T37	3		T38	3		T39	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T104	1		T109	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T102	1		T109	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T39	3		T102	2		T113	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T37	4		T38	2		T39	2
auto[TlIntgErrData]	full_word	auto[0]	11	1			T37	1		T39	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T102	1		T112	2		T108	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T38	1		T39	3		T107	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T38	1		T39	2		T107	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T102	1		T106	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T39	2		T102	2		T114	1