Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	730400	1			T3	7508		T5	6350		T11	21
auto[1]	10521457	1			T1	48		T3	5068		T4	266
auto[2]	611648	1			T3	4752		T5	5907		T11	23
auto[3]	10409594	1			T1	106		T3	2670		T4	237

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14521895	1			T1	1		T3	15551		T4	400
auto[1]	2150709	1			T1	7		T3	1820		T4	50
auto[2]	2130344	1			T1	8		T3	2374		T4	45
auto[3]	3470151	1			T1	138		T3	253		T4	8

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8619837

1

T1

153

T3

19982

T4

503

auto[1]

13653262

1

T1

1

T3

16

T5

15

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	390609	1			T3	6238		T5	5249		T13	7
auto[0]	auto[0]	auto[1]	39897	1			T3	592		T5	520		T11	4
auto[0]	auto[0]	auto[2]	39930	1			T3	629		T5	519		T11	1
auto[0]	auto[0]	auto[3]	9008	1			T3	41		T5	55		T11	16
auto[0]	auto[1]	auto[0]	3159756	1			T3	3898		T4	209		T5	814
auto[0]	auto[1]	auto[1]	342852	1			T1	1		T3	690		T4	25
auto[0]	auto[1]	auto[2]	318082	1			T1	1		T3	398		T4	26
auto[0]	auto[1]	auto[3]	68067	1			T1	46		T3	79		T4	6
auto[0]	auto[2]	auto[0]	345882	1			T3	3726		T5	4921		T13	8
auto[0]	auto[2]	auto[1]	35398	1			T3	378		T5	484		T11	10
auto[0]	auto[2]	auto[2]	30790	1			T3	584		T5	457		T11	2
auto[0]	auto[2]	auto[3]	6916	1			T3	60		T5	38		T11	11
auto[0]	auto[3]	auto[0]	3113012	1			T1	1		T3	1678		T4	191
auto[0]	auto[3]	auto[1]	313277	1			T1	6		T3	157		T4	25
auto[0]	auto[3]	auto[2]	335331	1			T1	7		T3	761		T4	19
auto[0]	auto[3]	auto[3]	71030	1			T1	91		T3	73		T4	2
auto[1]	auto[0]	auto[0]	8649	1			T3	6		T5	7		T63	584
auto[1]	auto[0]	auto[1]	37040	1			T3	2		T63	2566		T125	1
auto[1]	auto[0]	auto[2]	37185	1			T63	2559		T121	1		T126	4
auto[1]	auto[0]	auto[3]	168082	1			T63	11438		T73	2		T122	1
auto[1]	auto[1]	auto[0]	3749443	1			T3	1		T8	8		T9	45
auto[1]	auto[1]	auto[1]	684148	1			T3	1		T5	1		T9	5
auto[1]	auto[1]	auto[2]	666988	1			T3	1		T9	3		T12	5
auto[1]	auto[1]	auto[3]	1532121	1			T9	1		T63	11692		T87	46550
auto[1]	auto[2]	auto[0]	7930	1			T3	4		T5	5		T63	495
auto[1]	auto[2]	auto[1]	33866	1			T63	2365		T122	2		T127	5
auto[1]	auto[2]	auto[2]	27593	1			T5	2		T63	1716		T122	1
auto[1]	auto[2]	auto[3]	123273	1			T63	7840		T128	1		T127	1
auto[1]	auto[3]	auto[0]	3746614	1			T8	12		T9	38		T12	28
auto[1]	auto[3]	auto[1]	664231	1			T9	5		T12	5		T63	239
auto[1]	auto[3]	auto[2]	674445	1			T3	1		T9	8		T12	5
auto[1]	auto[3]	auto[3]	1491654	1			T1	1		T11	1		T63	7844