Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	332135133	162477	0	0
ctrl_regwen_rd_A	332135133	7331	0	0
exec_rd_A	332135133	6766	0	0
exec_regwen_rd_A	332135133	6878	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332135133	162477	0	0
T14	37107	2271	0	0
T22	659367	0	0	0
T23	89311	2326	0	0
T24	96997	2168	0	0
T25	1791	0	0	0
T37	0	5	0	0
T40	0	202	0	0
T41	0	2151	0	0
T42	0	225	0	0
T43	0	67	0	0
T44	0	504	0	0
T45	0	14	0	0
T47	12965	0	0	0
T48	8712	0	0	0
T49	106730	0	0	0
T50	323988	0	0	0
T51	203031	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332135133	7331	0	0
T22	659367	0	0	0
T23	89311	477	0	0
T24	96997	521	0	0
T25	1791	0	0	0
T40	0	16	0	0
T42	0	43	0	0
T47	12965	0	0	0
T48	8712	0	0	0
T49	106730	0	0	0
T50	323988	0	0	0
T51	203031	0	0	0
T52	0	4	0	0
T55	0	5	0	0
T65	0	7	0	0
T70	0	35	0	0
T93	0	29	0	0
T100	0	3	0	0
T101	2937	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332135133	6766	0	0
T22	659367	0	0	0
T23	89311	493	0	0
T24	96997	461	0	0
T25	1791	0	0	0
T40	0	26	0	0
T42	0	49	0	0
T47	12965	0	0	0
T48	8712	0	0	0
T49	106730	0	0	0
T50	323988	0	0	0
T51	203031	0	0	0
T55	0	8	0	0
T65	0	17	0	0
T66	0	8	0	0
T70	0	34	0	0
T93	0	45	0	0
T100	0	6	0	0
T101	2937	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332135133	6878	0	0
T22	659367	0	0	0
T23	89311	471	0	0
T24	96997	448	0	0
T25	1791	0	0	0
T40	0	40	0	0
T42	0	69	0	0
T47	12965	0	0	0
T48	8712	0	0	0
T49	106730	0	0	0
T50	323988	0	0	0
T51	203031	0	0	0
T55	0	5	0	0
T65	0	7	0	0
T66	0	4	0	0
T70	0	8	0	0
T93	0	8	0	0
T100	0	4	0	0
T101	2937	0	0	0