Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151775646	1			T1	3836		T2	134955		T4	404148
instr_valid_dis	115528944	1			T1	3836		T2	937420		T4	404148
instr_en	24419777	1			T2	208488		T17	227342		T19	169590

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12270179	1			T2	148354		T17	117686		T19	32384
sram_ifetch_valid_disable	116121616	1			T1	3836		T2	807628		T4	404148
sram_ifetch_enable	23383851	1			T2	393574		T17	145984		T19	117828

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151775646	1			T1	3836		T2	134955		T4	404148
hw_debug_en_valid_off	116183456	1			T1	3836		T2	888756		T4	404148
hw_debug_en_on	23291979	1			T2	383012		T17	235458		T19	59268

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116121616	1			T1	3836		T2	807628		T4	404148
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101954039	1			T1	3836		T2	609798		T4	404148
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9188615	1			T2	96488		T17	53504		T19	149590
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4359453	1			T2	27764		T17	7862		T19	32384
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1798688	1			T2	15674		T17	7862		T19	32384
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1658751	1			T43	9992		T6	37546		T122	3312
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4907815	1			T2	119410		T17	109824		T14	85958
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1979948	1			T2	47224		T17	81970		T14	85958
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2053576	1			T2	1970		T17	27854		T37	2334
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8873226	1			T2	81850		T17	35674		T19	44822
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3961997	1			T2	48362		T19	13774		T14	35620
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3400280	1			T17	35674		T43	24922		T37	3934

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10392749	1			T2	110030		T17	145984		T19	20000
lc_exec_en	9510938	1			T2	181752		T17	89960		T19	14446
valid_exec_dis	110851727	1			T1	3836		T2	963248		T4	404148
invalid_exec_dis	35654030	1			T2	541928		T17	263670		T19	150212