Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 100.00 98.13 100.00 100.00 99.71 99.70 100.00


Total tests in report: 1025
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.88 87.88 98.48 98.48 83.26 83.26 95.71 95.71 100.00 100.00 92.92 92.92 94.90 94.90 49.91 49.91 /workspace/coverage/default/45.sram_ctrl_stress_all.1934802510
95.53 7.65 99.34 0.85 92.21 8.95 96.35 0.64 100.00 0.00 96.76 3.83 96.25 1.35 87.80 37.90 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4023876340
96.85 1.32 99.62 0.28 94.08 1.88 96.92 0.57 100.00 0.00 98.23 1.47 96.25 0.00 92.87 5.07 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.277619611
97.69 0.83 99.81 0.19 96.54 2.45 98.25 1.32 100.00 0.00 99.12 0.88 96.85 0.60 93.25 0.38 /workspace/coverage/default/4.sram_ctrl_sec_cm.2210762950
98.08 0.39 99.91 0.09 97.26 0.72 98.25 0.00 100.00 0.00 99.71 0.59 96.85 0.00 94.56 1.31 /workspace/coverage/default/25.sram_ctrl_stress_all.1011846068
98.36 0.29 99.91 0.00 97.26 0.00 98.25 0.00 100.00 0.00 99.71 0.00 97.75 0.90 95.68 1.13 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2378158667
98.64 0.28 99.91 0.00 97.26 0.00 99.28 1.04 100.00 0.00 99.71 0.00 97.90 0.15 96.44 0.75 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1696427293
98.88 0.24 99.91 0.00 97.26 0.00 99.28 0.00 100.00 0.00 99.71 0.00 99.55 1.65 96.44 0.00 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.68938946
99.01 0.13 99.91 0.00 97.26 0.00 99.28 0.00 100.00 0.00 99.71 0.00 99.55 0.00 97.37 0.94 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4128302352
99.14 0.13 99.91 0.00 97.40 0.14 99.28 0.00 100.00 0.00 99.71 0.00 99.55 0.00 98.12 0.75 /workspace/coverage/default/14.sram_ctrl_stress_all.3919602446
99.25 0.12 100.00 0.09 97.40 0.00 100.00 0.72 100.00 0.00 99.71 0.00 99.55 0.00 98.12 0.00 /workspace/coverage/default/0.sram_ctrl_ram_cfg.1802826030
99.36 0.11 100.00 0.00 97.40 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 98.87 0.75 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1683177199
99.42 0.05 100.00 0.00 97.40 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.25 0.38 /workspace/coverage/default/24.sram_ctrl_stress_all.4207530411
99.46 0.04 100.00 0.00 97.69 0.29 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.25 0.00 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3609856002
99.50 0.04 100.00 0.00 97.98 0.29 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.25 0.00 /workspace/coverage/default/12.sram_ctrl_alert_test.4274608989
99.52 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.44 0.19 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2965260204
99.55 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.62 0.19 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1863764501
99.58 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.81 0.19 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2396134942
99.61 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 100.00 0.19 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1435349691
99.63 0.02 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.15 100.00 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1693263845

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3910382250
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3606427660
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3078025295
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.792984883
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3789919649
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.416741238
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1387597499
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3664577921
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3240432818
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2277940680
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.278195469
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1471513362
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2803541338
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3797207372
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.573012444
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1596709190
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.27410691
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.179781636
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1464690070
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3287407149
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3625739050
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1206463590
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.154398525
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1581565360
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.563359265
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3800815173
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.97821222
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3688650669
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3279882669
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1504511224
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.631214
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3193570535
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.886867375
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3123645130
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4194195325
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1971397407
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1977879520
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2710013101
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1337392196
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1056057423
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1795228319
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2100375531
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.937163650
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.734911229
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1039330246
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.615840812
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1708799753
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2388094986
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1523002082
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.971543084
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3467412880
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3831844182
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1046450376
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3099354652
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2027381267
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4048394750
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4140967387
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1326193365
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2488859343
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.401780963
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3649092314
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.913499167
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1749025942
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3588968152
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2429121526
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3587079816
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1663048619
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1050380834
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4018395900
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3099589764
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2354517232
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1869663766
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1956881752
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3705176663
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.618144944
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2403704364
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2373532850
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4252564875
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1208318441
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.353439339
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3463711783
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1058929412
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2772437781
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2317534515
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3257029118
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1069536146
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2516211131
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2811659935
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2320394480
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3472030941
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3540750985
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1509363776
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4114453730
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.758724643
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2827553480
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2823224894
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4080794400
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.912038521
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.880285329
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1556001958
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1842310132
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.370659264
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1694206810
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.979078191
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1980141576
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2826635540
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3743963724
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3110656690
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4223075493
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.553170007
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2165198237
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3358846230
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4053326496
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2026032335
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1102478777
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1907486870
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1678540941
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3979527570
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3003408648
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2876097426
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3787893492
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2309787453
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3143653771
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2694710485
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.579443642
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2800246838
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1178482693
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2091095562
/workspace/coverage/default/0.sram_ctrl_alert_test.3855680586
/workspace/coverage/default/0.sram_ctrl_bijection.2957947273
/workspace/coverage/default/0.sram_ctrl_executable.1337209095
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1375312440
/workspace/coverage/default/0.sram_ctrl_max_throughput.3798348981
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3219196986
/workspace/coverage/default/0.sram_ctrl_mem_walk.2184373989
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3857623543
/workspace/coverage/default/0.sram_ctrl_partial_access.3861157829
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.4235207812
/workspace/coverage/default/0.sram_ctrl_regwen.2057658533
/workspace/coverage/default/0.sram_ctrl_sec_cm.2070360913
/workspace/coverage/default/0.sram_ctrl_smoke.1844264966
/workspace/coverage/default/0.sram_ctrl_stress_all.4012204727
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1211973521
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.4074783887
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1162318231
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.949119163
/workspace/coverage/default/1.sram_ctrl_alert_test.902328626
/workspace/coverage/default/1.sram_ctrl_bijection.2573700420
/workspace/coverage/default/1.sram_ctrl_executable.933121906
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3563505508
/workspace/coverage/default/1.sram_ctrl_max_throughput.3339557010
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3368988243
/workspace/coverage/default/1.sram_ctrl_mem_walk.2557993125
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2515176399
/workspace/coverage/default/1.sram_ctrl_partial_access.958535623
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.132378317
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3287912537
/workspace/coverage/default/1.sram_ctrl_regwen.1678524404
/workspace/coverage/default/1.sram_ctrl_sec_cm.4088757876
/workspace/coverage/default/1.sram_ctrl_smoke.2056741163
/workspace/coverage/default/1.sram_ctrl_stress_all.701442794
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2569256764
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.719295251
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1181910531
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1357842512
/workspace/coverage/default/10.sram_ctrl_alert_test.2988911809
/workspace/coverage/default/10.sram_ctrl_bijection.1248327656
/workspace/coverage/default/10.sram_ctrl_executable.486448347
/workspace/coverage/default/10.sram_ctrl_max_throughput.2610071521
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2445774563
/workspace/coverage/default/10.sram_ctrl_mem_walk.2274776459
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2750864162
/workspace/coverage/default/10.sram_ctrl_partial_access.3093661622
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.144219841
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2965266371
/workspace/coverage/default/10.sram_ctrl_regwen.278627690
/workspace/coverage/default/10.sram_ctrl_smoke.670837924
/workspace/coverage/default/10.sram_ctrl_stress_all.2226719730
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2124372068
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.416806826
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2626250061
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2018363123
/workspace/coverage/default/11.sram_ctrl_alert_test.4078865454
/workspace/coverage/default/11.sram_ctrl_bijection.2304973337
/workspace/coverage/default/11.sram_ctrl_executable.2922519314
/workspace/coverage/default/11.sram_ctrl_max_throughput.350802408
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.509888019
/workspace/coverage/default/11.sram_ctrl_mem_walk.1961652975
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3242342458
/workspace/coverage/default/11.sram_ctrl_partial_access.1834283516
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.363768444
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3118019775
/workspace/coverage/default/11.sram_ctrl_regwen.2843780863
/workspace/coverage/default/11.sram_ctrl_smoke.4188218385
/workspace/coverage/default/11.sram_ctrl_stress_all.1735434755
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4085646421
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3240935242
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.661243042
/workspace/coverage/default/12.sram_ctrl_bijection.3952779119
/workspace/coverage/default/12.sram_ctrl_executable.2375681283
/workspace/coverage/default/12.sram_ctrl_lc_escalation.4143987952
/workspace/coverage/default/12.sram_ctrl_max_throughput.1620919459
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3373693244
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/workspace/coverage/default/43.sram_ctrl_bijection.4115285531
/workspace/coverage/default/43.sram_ctrl_executable.3330454534
/workspace/coverage/default/43.sram_ctrl_max_throughput.230544908
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2218088576
/workspace/coverage/default/43.sram_ctrl_mem_walk.2152821090
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3808336633
/workspace/coverage/default/43.sram_ctrl_partial_access.3359300685
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1728238611
/workspace/coverage/default/43.sram_ctrl_ram_cfg.96955699
/workspace/coverage/default/43.sram_ctrl_regwen.1911451565
/workspace/coverage/default/43.sram_ctrl_smoke.707074460
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2273124302
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.857520280
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2495095450
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.4073746900
/workspace/coverage/default/44.sram_ctrl_alert_test.4014293893
/workspace/coverage/default/44.sram_ctrl_bijection.2920747635
/workspace/coverage/default/44.sram_ctrl_executable.238917274
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2600850729
/workspace/coverage/default/44.sram_ctrl_max_throughput.3378527172
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1240783350
/workspace/coverage/default/44.sram_ctrl_mem_walk.3134658560
/workspace/coverage/default/44.sram_ctrl_multiple_keys.805346851
/workspace/coverage/default/44.sram_ctrl_partial_access.2720285480
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2960387716
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2843244932
/workspace/coverage/default/44.sram_ctrl_regwen.351928506
/workspace/coverage/default/44.sram_ctrl_smoke.3631058005
/workspace/coverage/default/44.sram_ctrl_stress_all.1701942733
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2350674623
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3646915315
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1508700126
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2675285335
/workspace/coverage/default/45.sram_ctrl_alert_test.1057050048
/workspace/coverage/default/45.sram_ctrl_bijection.3397000353
/workspace/coverage/default/45.sram_ctrl_executable.2213428612
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3546432654
/workspace/coverage/default/45.sram_ctrl_max_throughput.298106653
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3308637808
/workspace/coverage/default/45.sram_ctrl_mem_walk.2101929504
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1442140145
/workspace/coverage/default/45.sram_ctrl_partial_access.873116964
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.803866604
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2949258745
/workspace/coverage/default/45.sram_ctrl_regwen.372229115
/workspace/coverage/default/45.sram_ctrl_smoke.67449082
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4273366528
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.429428737
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2529578182
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2471816705
/workspace/coverage/default/46.sram_ctrl_alert_test.217758084
/workspace/coverage/default/46.sram_ctrl_bijection.1771879589
/workspace/coverage/default/46.sram_ctrl_executable.2696071282
/workspace/coverage/default/46.sram_ctrl_lc_escalation.281157204
/workspace/coverage/default/46.sram_ctrl_max_throughput.3318038751
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2349473422
/workspace/coverage/default/46.sram_ctrl_mem_walk.1206578612
/workspace/coverage/default/46.sram_ctrl_multiple_keys.228126291
/workspace/coverage/default/46.sram_ctrl_partial_access.1878691373
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.35994392
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2223812983
/workspace/coverage/default/46.sram_ctrl_regwen.1220481771
/workspace/coverage/default/46.sram_ctrl_smoke.925147096
/workspace/coverage/default/46.sram_ctrl_stress_all.35831965
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1703284668
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2965371299
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3902303987
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1597516582
/workspace/coverage/default/47.sram_ctrl_alert_test.4007272454
/workspace/coverage/default/47.sram_ctrl_bijection.2419041981
/workspace/coverage/default/47.sram_ctrl_executable.113349995
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3940713718
/workspace/coverage/default/47.sram_ctrl_max_throughput.2534915469
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3415391321
/workspace/coverage/default/47.sram_ctrl_mem_walk.3911272957
/workspace/coverage/default/47.sram_ctrl_multiple_keys.4242435415
/workspace/coverage/default/47.sram_ctrl_partial_access.2216463237
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.428301559
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2787269297
/workspace/coverage/default/47.sram_ctrl_regwen.2462399323
/workspace/coverage/default/47.sram_ctrl_smoke.2583682684
/workspace/coverage/default/47.sram_ctrl_stress_all.305261805
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2336270472
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1686415255
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2742500429
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2010597495
/workspace/coverage/default/48.sram_ctrl_alert_test.1624624560
/workspace/coverage/default/48.sram_ctrl_bijection.2492034084
/workspace/coverage/default/48.sram_ctrl_executable.1820659987
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1230290895
/workspace/coverage/default/48.sram_ctrl_max_throughput.1087566267
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2290100589
/workspace/coverage/default/48.sram_ctrl_mem_walk.2371069145
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1720329469
/workspace/coverage/default/48.sram_ctrl_partial_access.2470506597
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1048362767
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1996158839
/workspace/coverage/default/48.sram_ctrl_regwen.545950916
/workspace/coverage/default/48.sram_ctrl_smoke.2907985844
/workspace/coverage/default/48.sram_ctrl_stress_all.1817856580
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3932728046
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3558462365
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2276120019
/workspace/coverage/default/49.sram_ctrl_alert_test.788133584
/workspace/coverage/default/49.sram_ctrl_bijection.3675523674
/workspace/coverage/default/49.sram_ctrl_executable.1112861621
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2765799355
/workspace/coverage/default/49.sram_ctrl_max_throughput.2127805977
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3350686608
/workspace/coverage/default/49.sram_ctrl_mem_walk.976154854
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1282257940
/workspace/coverage/default/49.sram_ctrl_partial_access.3358055805
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.456203155
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1712594996
/workspace/coverage/default/49.sram_ctrl_regwen.4161511829
/workspace/coverage/default/49.sram_ctrl_smoke.3654306393
/workspace/coverage/default/49.sram_ctrl_stress_all.1922109506
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3084095277
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.546648142
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3801657593
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4045900831
/workspace/coverage/default/5.sram_ctrl_alert_test.93501544
/workspace/coverage/default/5.sram_ctrl_bijection.4013628439
/workspace/coverage/default/5.sram_ctrl_executable.1491539138
/workspace/coverage/default/5.sram_ctrl_max_throughput.4101907856
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.19106179
/workspace/coverage/default/5.sram_ctrl_mem_walk.2755157294
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2685617244
/workspace/coverage/default/5.sram_ctrl_partial_access.3122889521
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3477755358
/workspace/coverage/default/5.sram_ctrl_ram_cfg.4188774315
/workspace/coverage/default/5.sram_ctrl_regwen.2517554314
/workspace/coverage/default/5.sram_ctrl_smoke.534941078
/workspace/coverage/default/5.sram_ctrl_stress_all.108691510
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1661270594
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3660422488
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2986656768
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3220879849
/workspace/coverage/default/6.sram_ctrl_alert_test.3844115238
/workspace/coverage/default/6.sram_ctrl_bijection.1657587089
/workspace/coverage/default/6.sram_ctrl_executable.2384646559
/workspace/coverage/default/6.sram_ctrl_max_throughput.1113376255
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.4015079879
/workspace/coverage/default/6.sram_ctrl_mem_walk.205176174
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1815776865
/workspace/coverage/default/6.sram_ctrl_partial_access.3084777115
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2419090575
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1613142607
/workspace/coverage/default/6.sram_ctrl_regwen.4018978303
/workspace/coverage/default/6.sram_ctrl_smoke.2615002923
/workspace/coverage/default/6.sram_ctrl_stress_all.803690092
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4251765571
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1403313211
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.875800059
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2537309184
/workspace/coverage/default/7.sram_ctrl_alert_test.2893513481
/workspace/coverage/default/7.sram_ctrl_bijection.2622178952
/workspace/coverage/default/7.sram_ctrl_executable.1440595444
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2631146754
/workspace/coverage/default/7.sram_ctrl_max_throughput.46219149
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.264948211
/workspace/coverage/default/7.sram_ctrl_mem_walk.1715512670
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2594476859
/workspace/coverage/default/7.sram_ctrl_partial_access.92115357
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3073832994
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3750078955
/workspace/coverage/default/7.sram_ctrl_regwen.747862969
/workspace/coverage/default/7.sram_ctrl_smoke.695774078
/workspace/coverage/default/7.sram_ctrl_stress_all.1495554078
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.385133864
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3270797705
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.456024518
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3547871381
/workspace/coverage/default/8.sram_ctrl_alert_test.2428116598
/workspace/coverage/default/8.sram_ctrl_bijection.3307456221
/workspace/coverage/default/8.sram_ctrl_executable.1750728296
/workspace/coverage/default/8.sram_ctrl_max_throughput.3764874112
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3686694529
/workspace/coverage/default/8.sram_ctrl_mem_walk.3042562156
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3098415641
/workspace/coverage/default/8.sram_ctrl_partial_access.404785082
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1007251719
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1286316805
/workspace/coverage/default/8.sram_ctrl_regwen.2615263523
/workspace/coverage/default/8.sram_ctrl_smoke.2567567665
/workspace/coverage/default/8.sram_ctrl_stress_all.1942067797
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3496336413
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.369488646
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.682467347
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.4281287062
/workspace/coverage/default/9.sram_ctrl_alert_test.3181018030
/workspace/coverage/default/9.sram_ctrl_bijection.2597954422
/workspace/coverage/default/9.sram_ctrl_executable.2488445330
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1977696160
/workspace/coverage/default/9.sram_ctrl_max_throughput.997464366
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1329958437
/workspace/coverage/default/9.sram_ctrl_mem_walk.1661874655
/workspace/coverage/default/9.sram_ctrl_multiple_keys.4154090328
/workspace/coverage/default/9.sram_ctrl_partial_access.1262854670
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2744409146
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3989931426
/workspace/coverage/default/9.sram_ctrl_regwen.1464703637
/workspace/coverage/default/9.sram_ctrl_smoke.267096151
/workspace/coverage/default/9.sram_ctrl_stress_all.1532881338
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2431779247
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2033406543
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3840086364



Total test records in report: 1025
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/21.sram_ctrl_partial_access.3495676898 Jan 17 01:27:11 PM PST 24 Jan 17 01:27:20 PM PST 24 476944145 ps
T2 /workspace/coverage/default/45.sram_ctrl_stress_all.1934802510 Jan 17 01:34:13 PM PST 24 Jan 17 02:44:59 PM PST 24 49961618625 ps
T3 /workspace/coverage/default/34.sram_ctrl_ram_cfg.1423037298 Jan 17 01:31:02 PM PST 24 Jan 17 01:31:04 PM PST 24 52388657 ps
T4 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1696427293 Jan 17 01:31:55 PM PST 24 Jan 17 01:35:57 PM PST 24 4991236813 ps
T8 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3609856002 Jan 17 01:25:05 PM PST 24 Jan 17 01:37:07 PM PST 24 6463302800 ps
T5 /workspace/coverage/default/45.sram_ctrl_lc_escalation.3546432654 Jan 17 01:33:59 PM PST 24 Jan 17 01:34:06 PM PST 24 177222361 ps
T9 /workspace/coverage/default/29.sram_ctrl_mem_walk.2314777986 Jan 17 01:29:32 PM PST 24 Jan 17 01:29:38 PM PST 24 638246362 ps
T10 /workspace/coverage/default/34.sram_ctrl_alert_test.2429394616 Jan 17 01:31:18 PM PST 24 Jan 17 01:31:22 PM PST 24 44386243 ps
T11 /workspace/coverage/default/16.sram_ctrl_mem_walk.2639275762 Jan 17 01:25:58 PM PST 24 Jan 17 01:26:05 PM PST 24 233940582 ps
T12 /workspace/coverage/default/12.sram_ctrl_mem_walk.3320334611 Jan 17 01:25:09 PM PST 24 Jan 17 01:25:22 PM PST 24 1745013120 ps
T15 /workspace/coverage/default/10.sram_ctrl_smoke.670837924 Jan 17 01:24:20 PM PST 24 Jan 17 01:24:36 PM PST 24 2124705204 ps
T16 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3270797705 Jan 17 01:23:36 PM PST 24 Jan 17 01:28:42 PM PST 24 12979763770 ps
T17 /workspace/coverage/default/29.sram_ctrl_executable.2059837919 Jan 17 01:29:31 PM PST 24 Jan 17 01:48:44 PM PST 24 3383141046 ps
T73 /workspace/coverage/default/42.sram_ctrl_mem_walk.2693712122 Jan 17 01:33:08 PM PST 24 Jan 17 01:33:17 PM PST 24 152102820 ps
T18 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2994734186 Jan 17 01:23:13 PM PST 24 Jan 17 01:30:36 PM PST 24 52087288706 ps
T132 /workspace/coverage/default/43.sram_ctrl_mem_walk.2152821090 Jan 17 01:33:33 PM PST 24 Jan 17 01:33:39 PM PST 24 77912815 ps
T19 /workspace/coverage/default/26.sram_ctrl_executable.2738072311 Jan 17 01:28:41 PM PST 24 Jan 17 01:43:12 PM PST 24 2915460872 ps
T133 /workspace/coverage/default/29.sram_ctrl_smoke.3805273004 Jan 17 01:29:31 PM PST 24 Jan 17 01:29:42 PM PST 24 171158798 ps
T13 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4023876340 Jan 17 01:35:00 PM PST 24 Jan 17 02:21:08 PM PST 24 5085047553 ps
T52 /workspace/coverage/default/40.sram_ctrl_bijection.878993381 Jan 17 01:32:26 PM PST 24 Jan 17 01:33:07 PM PST 24 2499980436 ps
T14 /workspace/coverage/default/19.sram_ctrl_regwen.4257541770 Jan 17 01:26:55 PM PST 24 Jan 17 01:44:48 PM PST 24 68910340029 ps
T30 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1783475431 Jan 17 01:27:56 PM PST 24 Jan 17 02:07:26 PM PST 24 574989621 ps
T53 /workspace/coverage/default/39.sram_ctrl_multiple_keys.3932987862 Jan 17 01:32:12 PM PST 24 Jan 17 01:46:55 PM PST 24 4288315241 ps
T54 /workspace/coverage/default/35.sram_ctrl_partial_access.1289347845 Jan 17 01:31:18 PM PST 24 Jan 17 01:31:53 PM PST 24 1410078379 ps
T32 /workspace/coverage/default/0.sram_ctrl_ram_cfg.1802826030 Jan 17 01:22:31 PM PST 24 Jan 17 01:22:36 PM PST 24 108355528 ps
T22 /workspace/coverage/default/30.sram_ctrl_alert_test.2164701180 Jan 17 01:29:48 PM PST 24 Jan 17 01:29:54 PM PST 24 12335441 ps
T55 /workspace/coverage/default/13.sram_ctrl_smoke.3388161761 Jan 17 01:25:11 PM PST 24 Jan 17 01:25:15 PM PST 24 181422111 ps
T56 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.755393192 Jan 17 01:29:11 PM PST 24 Jan 17 01:35:20 PM PST 24 21495885479 ps
T57 /workspace/coverage/default/9.sram_ctrl_max_throughput.997464366 Jan 17 01:24:10 PM PST 24 Jan 17 01:25:14 PM PST 24 410458058 ps
T43 /workspace/coverage/default/24.sram_ctrl_stress_all.4207530411 Jan 17 01:28:21 PM PST 24 Jan 17 02:14:06 PM PST 24 75566999868 ps
T126 /workspace/coverage/default/18.sram_ctrl_smoke.839774049 Jan 17 01:26:17 PM PST 24 Jan 17 01:27:18 PM PST 24 2106630922 ps
T33 /workspace/coverage/default/29.sram_ctrl_ram_cfg.3625098766 Jan 17 01:29:33 PM PST 24 Jan 17 01:29:34 PM PST 24 71352096 ps
T74 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3219196986 Jan 17 01:22:48 PM PST 24 Jan 17 01:22:51 PM PST 24 157533846 ps
T134 /workspace/coverage/default/20.sram_ctrl_ram_cfg.442305071 Jan 17 01:27:04 PM PST 24 Jan 17 01:27:06 PM PST 24 38928897 ps
T20 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.4073746900 Jan 17 01:33:44 PM PST 24 Jan 17 01:48:50 PM PST 24 4009518701 ps
T7 /workspace/coverage/default/4.sram_ctrl_sec_cm.2210762950 Jan 17 01:23:21 PM PST 24 Jan 17 01:23:26 PM PST 24 1064804453 ps
T36 /workspace/coverage/default/29.sram_ctrl_multiple_keys.4252999596 Jan 17 01:29:25 PM PST 24 Jan 17 01:42:15 PM PST 24 25323221037 ps
T37 /workspace/coverage/default/28.sram_ctrl_executable.615162076 Jan 17 01:29:24 PM PST 24 Jan 17 01:41:04 PM PST 24 24177921626 ps
T31 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4273366528 Jan 17 01:33:59 PM PST 24 Jan 17 02:19:18 PM PST 24 1488673316 ps
T38 /workspace/coverage/default/36.sram_ctrl_regwen.3082680586 Jan 17 01:31:27 PM PST 24 Jan 17 01:42:25 PM PST 24 2293717176 ps
T23 /workspace/coverage/default/9.sram_ctrl_alert_test.3181018030 Jan 17 01:24:19 PM PST 24 Jan 17 01:24:22 PM PST 24 11147370 ps
T135 /workspace/coverage/default/46.sram_ctrl_bijection.1771879589 Jan 17 01:34:10 PM PST 24 Jan 17 01:35:11 PM PST 24 5660629671 ps
T6 /workspace/coverage/default/8.sram_ctrl_stress_all.1942067797 Jan 17 01:24:19 PM PST 24 Jan 17 01:54:19 PM PST 24 20692676891 ps
T96 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.684030546 Jan 17 01:25:27 PM PST 24 Jan 17 01:32:07 PM PST 24 22118817022 ps
T136 /workspace/coverage/default/5.sram_ctrl_ram_cfg.4188774315 Jan 17 01:23:22 PM PST 24 Jan 17 01:23:25 PM PST 24 248459352 ps
T106 /workspace/coverage/default/26.sram_ctrl_lc_escalation.1023690540 Jan 17 01:28:40 PM PST 24 Jan 17 01:28:48 PM PST 24 2401254354 ps
T137 /workspace/coverage/default/6.sram_ctrl_bijection.1657587089 Jan 17 01:23:28 PM PST 24 Jan 17 01:24:16 PM PST 24 12883648478 ps
T21 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1645147962 Jan 17 01:28:11 PM PST 24 Jan 17 01:31:24 PM PST 24 1083345129 ps
T138 /workspace/coverage/default/45.sram_ctrl_max_throughput.298106653 Jan 17 01:34:01 PM PST 24 Jan 17 01:35:19 PM PST 24 138960056 ps
T121 /workspace/coverage/default/19.sram_ctrl_stress_all.3276877764 Jan 17 01:27:01 PM PST 24 Jan 17 02:04:20 PM PST 24 32095331203 ps
T28 /workspace/coverage/default/46.sram_ctrl_lc_escalation.281157204 Jan 17 01:34:06 PM PST 24 Jan 17 01:34:17 PM PST 24 589539105 ps
T26 /workspace/coverage/default/14.sram_ctrl_stress_all.3919602446 Jan 17 01:25:32 PM PST 24 Jan 17 02:15:31 PM PST 24 184181188168 ps
T27 /workspace/coverage/default/28.sram_ctrl_regwen.2971559575 Jan 17 01:29:19 PM PST 24 Jan 17 01:51:09 PM PST 24 53167450786 ps
T122 /workspace/coverage/default/48.sram_ctrl_stress_all.1817856580 Jan 17 01:35:00 PM PST 24 Jan 17 03:03:30 PM PST 24 188592647299 ps
T139 /workspace/coverage/default/5.sram_ctrl_multiple_keys.2685617244 Jan 17 01:23:20 PM PST 24 Jan 17 01:41:01 PM PST 24 3553623236 ps
T140 /workspace/coverage/default/19.sram_ctrl_ram_cfg.1331929879 Jan 17 01:27:01 PM PST 24 Jan 17 01:27:04 PM PST 24 44401288 ps
T29 /workspace/coverage/default/28.sram_ctrl_stress_all.1830283404 Jan 17 01:29:24 PM PST 24 Jan 17 02:58:45 PM PST 24 16470743627 ps
T141 /workspace/coverage/default/4.sram_ctrl_lc_escalation.1343369606 Jan 17 01:23:21 PM PST 24 Jan 17 01:23:31 PM PST 24 1824123772 ps
T142 /workspace/coverage/default/21.sram_ctrl_lc_escalation.3841070387 Jan 17 01:27:12 PM PST 24 Jan 17 01:27:20 PM PST 24 517668155 ps
T97 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.363768444 Jan 17 01:24:35 PM PST 24 Jan 17 01:30:28 PM PST 24 14018168262 ps
T143 /workspace/coverage/default/7.sram_ctrl_stress_all.1495554078 Jan 17 01:23:59 PM PST 24 Jan 17 02:05:27 PM PST 24 7550277413 ps
T144 /workspace/coverage/default/43.sram_ctrl_multiple_keys.3808336633 Jan 17 01:33:15 PM PST 24 Jan 17 02:02:29 PM PST 24 21275821104 ps
T98 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2965371299 Jan 17 01:34:12 PM PST 24 Jan 17 01:37:14 PM PST 24 1817338331 ps
T107 /workspace/coverage/default/35.sram_ctrl_lc_escalation.4211440959 Jan 17 01:31:23 PM PST 24 Jan 17 01:31:26 PM PST 24 897708213 ps
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T146 /workspace/coverage/default/18.sram_ctrl_partial_access.1828874664 Jan 17 01:26:26 PM PST 24 Jan 17 01:26:30 PM PST 24 780162477 ps
T99 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2033406543 Jan 17 01:24:18 PM PST 24 Jan 17 01:28:02 PM PST 24 4684102853 ps
T100 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2920700653 Jan 17 01:27:56 PM PST 24 Jan 17 01:30:26 PM PST 24 2601873807 ps
T147 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1508700126 Jan 17 01:33:42 PM PST 24 Jan 17 01:33:54 PM PST 24 130300808 ps
T75 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2378158667 Jan 17 01:25:27 PM PST 24 Jan 17 01:25:33 PM PST 24 182362030 ps
T148 /workspace/coverage/default/40.sram_ctrl_lc_escalation.2956945528 Jan 17 01:32:42 PM PST 24 Jan 17 01:32:49 PM PST 24 445211627 ps
T76 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.714198733 Jan 17 01:30:19 PM PST 24 Jan 17 01:30:27 PM PST 24 694206125 ps
T149 /workspace/coverage/default/9.sram_ctrl_executable.2488445330 Jan 17 01:24:20 PM PST 24 Jan 17 01:40:19 PM PST 24 5578595342 ps
T150 /workspace/coverage/default/12.sram_ctrl_ram_cfg.1591385524 Jan 17 01:25:04 PM PST 24 Jan 17 01:25:14 PM PST 24 116968691 ps
T151 /workspace/coverage/default/39.sram_ctrl_smoke.3873678223 Jan 17 01:32:04 PM PST 24 Jan 17 01:32:21 PM PST 24 703694333 ps
T152 /workspace/coverage/default/9.sram_ctrl_mem_walk.1661874655 Jan 17 01:24:23 PM PST 24 Jan 17 01:24:29 PM PST 24 1252853928 ps
T153 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.35994392 Jan 17 01:34:10 PM PST 24 Jan 17 01:37:35 PM PST 24 15101736456 ps
T154 /workspace/coverage/default/26.sram_ctrl_ram_cfg.61385919 Jan 17 01:28:40 PM PST 24 Jan 17 01:28:42 PM PST 24 27413182 ps
T155 /workspace/coverage/default/23.sram_ctrl_smoke.1491899348 Jan 17 01:27:48 PM PST 24 Jan 17 01:27:53 PM PST 24 223661702 ps
T77 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3268022551 Jan 17 01:32:49 PM PST 24 Jan 17 01:44:43 PM PST 24 5436256063 ps
T156 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3248160037 Jan 17 01:32:25 PM PST 24 Jan 17 01:40:16 PM PST 24 35910914439 ps
T78 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2411065060 Jan 17 01:26:07 PM PST 24 Jan 17 01:26:13 PM PST 24 94836542 ps
T157 /workspace/coverage/default/42.sram_ctrl_lc_escalation.2652502456 Jan 17 01:33:05 PM PST 24 Jan 17 01:33:13 PM PST 24 457582935 ps
T158 /workspace/coverage/default/38.sram_ctrl_max_throughput.4255939232 Jan 17 01:32:02 PM PST 24 Jan 17 01:34:04 PM PST 24 542837961 ps
T159 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1484399954 Jan 17 01:30:27 PM PST 24 Jan 17 01:31:08 PM PST 24 556304700 ps
T160 /workspace/coverage/default/12.sram_ctrl_partial_access.1649606230 Jan 17 01:25:00 PM PST 24 Jan 17 01:25:13 PM PST 24 597612024 ps
T79 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3706465288 Jan 17 01:23:20 PM PST 24 Jan 17 01:37:32 PM PST 24 8979147491 ps
T161 /workspace/coverage/default/38.sram_ctrl_bijection.4105647492 Jan 17 01:31:55 PM PST 24 Jan 17 01:32:16 PM PST 24 1167809792 ps
T162 /workspace/coverage/default/7.sram_ctrl_multiple_keys.2594476859 Jan 17 01:23:37 PM PST 24 Jan 17 01:25:06 PM PST 24 8440145052 ps
T163 /workspace/coverage/default/30.sram_ctrl_max_throughput.550949557 Jan 17 01:29:33 PM PST 24 Jan 17 01:30:08 PM PST 24 118928257 ps
T44 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.277619611 Jan 17 12:35:58 PM PST 24 Jan 17 12:36:00 PM PST 24 538633142 ps
T46 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1596709190 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:43 PM PST 24 63145007 ps
T62 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1693263845 Jan 17 12:35:38 PM PST 24 Jan 17 12:35:42 PM PST 24 20604412 ps
T63 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3358846230 Jan 17 12:35:48 PM PST 24 Jan 17 12:35:55 PM PST 24 960736849 ps
T101 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4018395900 Jan 17 12:35:54 PM PST 24 Jan 17 12:35:55 PM PST 24 23391907 ps
T47 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2800246838 Jan 17 12:35:55 PM PST 24 Jan 17 12:35:59 PM PST 24 91963363 ps
T48 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3257029118 Jan 17 12:35:39 PM PST 24 Jan 17 12:35:43 PM PST 24 53541568 ps
T95 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1842310132 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:46 PM PST 24 77242807 ps
T64 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3910382250 Jan 17 12:35:37 PM PST 24 Jan 17 12:35:43 PM PST 24 151822146 ps
T45 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.27410691 Jan 17 12:35:41 PM PST 24 Jan 17 12:35:44 PM PST 24 172556237 ps
T49 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.154398525 Jan 17 12:35:54 PM PST 24 Jan 17 12:35:58 PM PST 24 580187418 ps
T65 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1956881752 Jan 17 12:35:50 PM PST 24 Jan 17 12:35:53 PM PST 24 28692504 ps
T66 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.278195469 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:42 PM PST 24 84495366 ps
T67 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2388094986 Jan 17 12:35:50 PM PST 24 Jan 17 12:35:54 PM PST 24 61706499 ps
T68 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.68938946 Jan 17 12:35:38 PM PST 24 Jan 17 12:35:46 PM PST 24 1612263099 ps
T50 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3110656690 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:50 PM PST 24 522465601 ps
T51 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2876097426 Jan 17 12:35:56 PM PST 24 Jan 17 12:35:59 PM PST 24 83678713 ps
T58 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3078025295 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:45 PM PST 24 36051222 ps
T69 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.758724643 Jan 17 12:35:44 PM PST 24 Jan 17 12:35:47 PM PST 24 44991702 ps
T61 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2027381267 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:47 PM PST 24 802837545 ps
T59 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1039330246 Jan 17 12:35:52 PM PST 24 Jan 17 12:35:56 PM PST 24 32165774 ps
T70 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2826635540 Jan 17 12:35:35 PM PST 24 Jan 17 12:35:44 PM PST 24 231582761 ps
T60 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3688650669 Jan 17 12:35:45 PM PST 24 Jan 17 12:35:50 PM PST 24 573101260 ps
T71 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2165198237 Jan 17 12:35:45 PM PST 24 Jan 17 12:35:48 PM PST 24 13529203 ps
T94 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2429121526 Jan 17 12:35:51 PM PST 24 Jan 17 12:35:54 PM PST 24 15794354 ps
T72 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2100375531 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:52 PM PST 24 19175887 ps
T111 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.886867375 Jan 17 12:35:48 PM PST 24 Jan 17 12:35:51 PM PST 24 422323239 ps
T80 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.792984883 Jan 17 12:35:26 PM PST 24 Jan 17 12:35:28 PM PST 24 23024301 ps
T164 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1206463590 Jan 17 12:35:53 PM PST 24 Jan 17 12:35:56 PM PST 24 117021722 ps
T112 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4128302352 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:53 PM PST 24 690427522 ps
T81 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3099589764 Jan 17 12:35:53 PM PST 24 Jan 17 12:36:00 PM PST 24 1583733935 ps
T165 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2710013101 Jan 17 12:35:44 PM PST 24 Jan 17 12:35:48 PM PST 24 23951294 ps
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T131 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2403704364 Jan 17 12:35:30 PM PST 24 Jan 17 12:35:33 PM PST 24 29659886 ps
T166 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.937163650 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:45 PM PST 24 41052740 ps
T167 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4053326496 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:52 PM PST 24 19190710 ps
T168 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3099354652 Jan 17 12:35:44 PM PST 24 Jan 17 12:35:50 PM PST 24 524496282 ps
T169 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.618144944 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:42 PM PST 24 31061674 ps
T170 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2317534515 Jan 17 12:35:46 PM PST 24 Jan 17 12:35:49 PM PST 24 42083922 ps
T171 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1869663766 Jan 17 12:35:56 PM PST 24 Jan 17 12:35:59 PM PST 24 24221144 ps
T108 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3787893492 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:53 PM PST 24 312008169 ps
T172 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1504511224 Jan 17 12:35:54 PM PST 24 Jan 17 12:36:00 PM PST 24 1633316247 ps
T173 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2309787453 Jan 17 12:35:55 PM PST 24 Jan 17 12:35:57 PM PST 24 29485311 ps
T82 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2694710485 Jan 17 12:35:37 PM PST 24 Jan 17 12:35:58 PM PST 24 650110010 ps
T83 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1971397407 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:53 PM PST 24 285690727 ps
T103 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.401780963 Jan 17 12:35:42 PM PST 24 Jan 17 12:35:46 PM PST 24 293656547 ps
T174 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1708799753 Jan 17 12:35:57 PM PST 24 Jan 17 12:36:16 PM PST 24 1766397723 ps
T89 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2772437781 Jan 17 12:35:50 PM PST 24 Jan 17 12:35:54 PM PST 24 569210590 ps
T105 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.563359265 Jan 17 12:35:41 PM PST 24 Jan 17 12:35:44 PM PST 24 20233837 ps
T175 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3472030941 Jan 17 12:35:42 PM PST 24 Jan 17 12:35:45 PM PST 24 79760774 ps
T176 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1907486870 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:46 PM PST 24 63983616 ps
T177 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.615840812 Jan 17 12:35:57 PM PST 24 Jan 17 12:35:59 PM PST 24 35834182 ps
T178 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1050380834 Jan 17 12:35:58 PM PST 24 Jan 17 12:36:01 PM PST 24 32836131 ps
T114 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1863764501 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:47 PM PST 24 207381262 ps
T104 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.734911229 Jan 17 12:35:54 PM PST 24 Jan 17 12:35:57 PM PST 24 295108968 ps
T179 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2320394480 Jan 17 12:35:37 PM PST 24 Jan 17 12:35:43 PM PST 24 77286491 ps
T84 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3789919649 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:47 PM PST 24 1855695164 ps
T180 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1523002082 Jan 17 12:35:58 PM PST 24 Jan 17 12:36:03 PM PST 24 86078022 ps
T181 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2965260204 Jan 17 12:35:44 PM PST 24 Jan 17 12:35:48 PM PST 24 227212508 ps
T182 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3467412880 Jan 17 12:35:53 PM PST 24 Jan 17 12:36:00 PM PST 24 14033782 ps
T113 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3463711783 Jan 17 12:35:33 PM PST 24 Jan 17 12:35:43 PM PST 24 272717253 ps
T183 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1046450376 Jan 17 12:35:46 PM PST 24 Jan 17 12:35:49 PM PST 24 22486748 ps
T184 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1069536146 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:52 PM PST 24 24885578 ps
T185 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.631214 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:46 PM PST 24 173442342 ps
T85 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4140967387 Jan 17 12:35:44 PM PST 24 Jan 17 12:35:47 PM PST 24 14977103 ps
T86 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2803541338 Jan 17 12:35:31 PM PST 24 Jan 17 12:35:33 PM PST 24 24591089 ps
T186 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2373532850 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:43 PM PST 24 40491401 ps
T187 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3743963724 Jan 17 12:35:42 PM PST 24 Jan 17 12:35:44 PM PST 24 18322286 ps
T116 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3664577921 Jan 17 12:35:41 PM PST 24 Jan 17 12:35:45 PM PST 24 620303800 ps
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T189 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3800815173 Jan 17 12:35:54 PM PST 24 Jan 17 12:36:00 PM PST 24 2494431196 ps
T190 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4048394750 Jan 17 12:35:56 PM PST 24 Jan 17 12:36:00 PM PST 24 31415485 ps
T90 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3287407149 Jan 17 12:35:55 PM PST 24 Jan 17 12:35:59 PM PST 24 1082767266 ps
T109 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1178482693 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:44 PM PST 24 1116734871 ps
T91 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1556001958 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:52 PM PST 24 40609093 ps
T92 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3979527570 Jan 17 12:35:51 PM PST 24 Jan 17 12:36:15 PM PST 24 694246710 ps
T93 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2827553480 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:56 PM PST 24 859756673 ps
T191 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.913499167 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:56 PM PST 24 80322473 ps
T192 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.573012444 Jan 17 12:35:37 PM PST 24 Jan 17 12:35:42 PM PST 24 36745627 ps
T110 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2396134942 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:52 PM PST 24 196801166 ps
T193 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1102478777 Jan 17 12:35:46 PM PST 24 Jan 17 12:35:49 PM PST 24 126542080 ps
T194 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1980141576 Jan 17 12:35:46 PM PST 24 Jan 17 12:35:49 PM PST 24 14499693 ps
T195 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1795228319 Jan 17 12:35:47 PM PST 24 Jan 17 12:36:03 PM PST 24 588204058 ps
T117 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3649092314 Jan 17 12:35:42 PM PST 24 Jan 17 12:35:45 PM PST 24 485398805 ps
T196 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1326193365 Jan 17 12:35:50 PM PST 24 Jan 17 12:35:55 PM PST 24 211252209 ps
T197 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3003408648 Jan 17 12:35:46 PM PST 24 Jan 17 12:35:49 PM PST 24 173360160 ps
T198 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1464690070 Jan 17 12:35:56 PM PST 24 Jan 17 12:35:57 PM PST 24 11768281 ps
T199 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3193570535 Jan 17 12:35:48 PM PST 24 Jan 17 12:35:54 PM PST 24 149388412 ps
T200 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3831844182 Jan 17 12:35:54 PM PST 24 Jan 17 12:36:05 PM PST 24 384563561 ps
T201 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4114453730 Jan 17 12:35:57 PM PST 24 Jan 17 12:36:00 PM PST 24 102071442 ps
T202 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2026032335 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:45 PM PST 24 127535803 ps
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T204 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.579443642 Jan 17 12:35:42 PM PST 24 Jan 17 12:35:45 PM PST 24 44764679 ps
T205 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1749025942 Jan 17 12:35:46 PM PST 24 Jan 17 12:35:49 PM PST 24 15001478 ps
T206 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3240432818 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:45 PM PST 24 41238442 ps
T207 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.353439339 Jan 17 12:35:40 PM PST 24 Jan 17 12:35:45 PM PST 24 213747976 ps
T115 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1694206810 Jan 17 12:35:42 PM PST 24 Jan 17 12:35:46 PM PST 24 155146727 ps
T119 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.912038521 Jan 17 12:35:44 PM PST 24 Jan 17 12:35:48 PM PST 24 1011008212 ps
T208 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1056057423 Jan 17 12:35:51 PM PST 24 Jan 17 12:35:54 PM PST 24 45543400 ps
T209 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2277940680 Jan 17 12:35:38 PM PST 24 Jan 17 12:35:43 PM PST 24 631782884 ps
T210 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1977879520 Jan 17 12:35:52 PM PST 24 Jan 17 12:35:54 PM PST 24 17105947 ps
T211 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.553170007 Jan 17 12:35:35 PM PST 24 Jan 17 12:35:42 PM PST 24 74940900 ps
T212 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3588968152 Jan 17 12:35:48 PM PST 24 Jan 17 12:35:55 PM PST 24 829444072 ps
T213 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2354517232 Jan 17 12:35:54 PM PST 24 Jan 17 12:35:56 PM PST 24 15410929 ps
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T215 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2488859343 Jan 17 12:35:44 PM PST 24 Jan 17 12:35:47 PM PST 24 63539655 ps
T216 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.880285329 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:47 PM PST 24 112831701 ps
T118 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1663048619 Jan 17 12:35:58 PM PST 24 Jan 17 12:36:01 PM PST 24 369213590 ps
T217 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1337392196 Jan 17 12:35:51 PM PST 24 Jan 17 12:35:55 PM PST 24 131034533 ps
T120 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1683177199 Jan 17 12:35:46 PM PST 24 Jan 17 12:35:50 PM PST 24 116560162 ps
T218 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3797207372 Jan 17 12:35:35 PM PST 24 Jan 17 12:35:46 PM PST 24 205958578 ps
T219 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.979078191 Jan 17 12:35:55 PM PST 24 Jan 17 12:35:58 PM PST 24 27125644 ps
T220 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.97821222 Jan 17 12:35:41 PM PST 24 Jan 17 12:35:44 PM PST 24 50767061 ps
T221 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1471513362 Jan 17 12:35:37 PM PST 24 Jan 17 12:35:44 PM PST 24 73250016 ps
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T223 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3279882669 Jan 17 12:35:46 PM PST 24 Jan 17 12:35:48 PM PST 24 32205804 ps
T224 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3143653771 Jan 17 12:35:48 PM PST 24 Jan 17 12:35:51 PM PST 24 12418302 ps
T225 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2811659935 Jan 17 12:35:50 PM PST 24 Jan 17 12:35:53 PM PST 24 78425130 ps
T226 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1581565360 Jan 17 12:35:44 PM PST 24 Jan 17 12:35:47 PM PST 24 38742787 ps
T227 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4252564875 Jan 17 12:35:38 PM PST 24 Jan 17 12:35:48 PM PST 24 470704185 ps
T228 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3123645130 Jan 17 12:35:48 PM PST 24 Jan 17 12:35:51 PM PST 24 157317829 ps
T229 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4194195325 Jan 17 12:35:55 PM PST 24 Jan 17 12:35:57 PM PST 24 23365546 ps
T230 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.370659264 Jan 17 12:35:42 PM PST 24 Jan 17 12:35:47 PM PST 24 126571976 ps
T231 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.179781636 Jan 17 12:35:48 PM PST 24 Jan 17 12:35:55 PM PST 24 109055725 ps
T232 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3540750985 Jan 17 12:35:42 PM PST 24 Jan 17 12:35:44 PM PST 24 209608206 ps
T233 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3705176663 Jan 17 12:35:39 PM PST 24 Jan 17 12:35:42 PM PST 24 61500915 ps
T234 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1058929412 Jan 17 12:35:50 PM PST 24 Jan 17 12:35:53 PM PST 24 32054491 ps
T235 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.971543084 Jan 17 12:35:50 PM PST 24 Jan 17 12:35:53 PM PST 24 118500411 ps
T236 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3625739050 Jan 17 12:35:42 PM PST 24 Jan 17 12:35:45 PM PST 24 49709818 ps
T237 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1678540941 Jan 17 12:35:41 PM PST 24 Jan 17 12:35:44 PM PST 24 13054397 ps
T238 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3587079816 Jan 17 12:35:50 PM PST 24 Jan 17 12:35:58 PM PST 24 153270439 ps
T239 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3606427660 Jan 17 12:35:35 PM PST 24 Jan 17 12:35:41 PM PST 24 39035304 ps
T240 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2516211131 Jan 17 12:35:54 PM PST 24 Jan 17 12:35:58 PM PST 24 463440973 ps
T241 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1387597499 Jan 17 12:35:43 PM PST 24 Jan 17 12:35:48 PM PST 24 38126994 ps
T242 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2823224894 Jan 17 12:35:49 PM PST 24 Jan 17 12:35:52 PM PST 24 19552277 ps
T243 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1180735353 Jan 17 01:28:35 PM PST 24 Jan 17 01:37:36 PM PST 24 23366597593 ps
T125 /workspace/coverage/default/8.sram_ctrl_multiple_keys.3098415641 Jan 17 01:23:59 PM PST 24 Jan 17 01:38:37 PM PST 24 50468466715 ps
T244 /workspace/coverage/default/37.sram_ctrl_partial_access.852364075 Jan 17 01:31:44 PM PST 24 Jan 17 01:32:04 PM PST 24 1229668241 ps
T245 /workspace/coverage/default/34.sram_ctrl_bijection.2847401952 Jan 17 01:30:42 PM PST 24 Jan 17 01:31:26 PM PST 24 9803058156 ps
T246 /workspace/coverage/default/17.sram_ctrl_bijection.3230383825 Jan 17 01:26:03 PM PST 24 Jan 17 01:26:41 PM PST 24 5861658967 ps
T247 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1661270594 Jan 17 01:23:21 PM PST 24 Jan 17 02:26:19 PM PST 24 1802488177 ps
T248 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3287912537 Jan 17 01:22:54 PM PST 24 Jan 17 01:23:02 PM PST 24 89441874 ps
T249 /workspace/coverage/default/45.sram_ctrl_alert_test.1057050048 Jan 17 01:34:10 PM PST 24 Jan 17 01:34:25 PM PST 24 65591127 ps
T250 /workspace/coverage/default/24.sram_ctrl_lc_escalation.2120414229 Jan 17 01:28:15 PM PST 24 Jan 17 01:28:20 PM PST 24 1420494821 ps
T251 /workspace/coverage/default/32.sram_ctrl_bijection.2736926716 Jan 17 01:30:18 PM PST 24 Jan 17 01:31:01 PM PST 24 1389615023 ps
T252 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2168355329 Jan 17 01:22:56 PM PST 24 Jan 17 01:26:09 PM PST 24 4487123124 ps
T253 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2626250061 Jan 17 01:24:23 PM PST 24 Jan 17 01:24:46 PM PST 24 206790833 ps
T254 /workspace/coverage/default/36.sram_ctrl_executable.278396151 Jan 17 01:31:25 PM PST 24 Jan 17 02:00:02 PM PST 24 4318564879 ps
T255 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2495095450 Jan 17 01:33:32 PM PST 24 Jan 17 01:35:11 PM PST 24 139313901 ps
T256 /workspace/coverage/default/38.sram_ctrl_partial_access.226764999 Jan 17 01:32:03 PM PST 24 Jan 17 01:32:08 PM PST 24 77867754 ps
T127 /workspace/coverage/default/25.sram_ctrl_multiple_keys.2976244789 Jan 17 01:28:15 PM PST 24 Jan 17 01:42:23 PM PST 24 62850205760 ps
T257 /workspace/coverage/default/35.sram_ctrl_bijection.1238796794 Jan 17 01:31:17 PM PST 24 Jan 17 01:31:43 PM PST 24 421203798 ps
T258 /workspace/coverage/default/14.sram_ctrl_max_throughput.2896032680 Jan 17 01:25:32 PM PST 24 Jan 17 01:25:48 PM PST 24 68935250 ps
T259 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3111266460 Jan 17 01:28:34 PM PST 24 Jan 17 01:32:56 PM PST 24 10622016310 ps
T124 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3200806284 Jan 17 01:30:25 PM PST 24 Jan 17 01:37:54 PM PST 24 83067382507 ps
T260 /workspace/coverage/default/46.sram_ctrl_alert_test.217758084 Jan 17 01:34:30 PM PST 24 Jan 17 01:34:32 PM PST 24 23635294 ps
T261 /workspace/coverage/default/33.sram_ctrl_executable.930832089 Jan 17 01:30:31 PM PST 24 Jan 17 01:33:03 PM PST 24 3791884677 ps
T262 /workspace/coverage/default/35.sram_ctrl_multiple_keys.462989268 Jan 17 01:31:17 PM PST 24 Jan 17 01:59:34 PM PST 24 3894341385 ps
T123 /workspace/coverage/default/31.sram_ctrl_regwen.929815923 Jan 17 01:30:18 PM PST 24 Jan 17 01:50:41 PM PST 24 23435760514 ps
T263 /workspace/coverage/default/14.sram_ctrl_alert_test.2825071259 Jan 17 01:25:33 PM PST 24 Jan 17 01:25:37 PM PST 24 16029540 ps
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