Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44818033	1			T1	357		T2	374813		T4	183621
triple_byte_access	2592597	1			T1	309		T2	7412		T4	3685
halfword_access	3891686	1			T1	442		T2	11319		T4	5550
byte_access	5202374	1			T1	650		T2	15024		T4	7359
zero_access	1307591	1			T1	160		T2	3717		T4	1859

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28850645

1

T1

940

T2

205928

T4

100962

auto[1]

28961636

1

T1

978

T2

206357

T4

101112

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22357915	1			T1	171		T2	187258		T4	91723
auto[0]	triple_byte_access	1292767	1			T1	146		T2	3738		T4	1860
auto[0]	halfword_access	1941765	1			T1	222		T2	5587		T4	2742
auto[0]	byte_access	2600108	1			T1	317		T2	7488		T4	3724
auto[0]	zero_access	658090	1			T1	84		T2	1857		T4	913
auto[1]	word_access	22460118	1			T1	186		T2	187555		T4	91898
auto[1]	triple_byte_access	1299830	1			T1	163		T2	3674		T4	1825
auto[1]	halfword_access	1949921	1			T1	220		T2	5732		T4	2808
auto[1]	byte_access	2602266	1			T1	333		T2	7536		T4	3635
auto[1]	zero_access	649501	1			T1	76		T2	1860		T4	946