Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13116756

1

T1

209

T2

1867

T3

13812

full_word

51834812

1

T1

979

T2

122

T3

136037

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64951288	1			T1	1188		T2	1989		T3	149849
auto[TlIntgErrCmd]	85	1			T37	3		T38	2		T40	2
auto[TlIntgErrData]	97	1			T37	4		T38	2		T40	5
auto[TlIntgErrBoth]	98	1			T37	3		T38	6		T40	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29805427

1

T1

589

T2

863

T3

74963

auto[1]

35146141

1

T1

599

T2

1126

T3

74886

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6265703	1			T1	82		T2	855		T3	6873
auto[TlIntgErrNone]	partial	auto[1]	6850795	1			T1	127		T2	1012		T3	6939
auto[TlIntgErrNone]	full_word	auto[0]	23539588	1			T1	507		T2	8		T3	68090
auto[TlIntgErrNone]	full_word	auto[1]	28295202	1			T1	472		T2	114		T3	67947
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T37	2		T40	2		T55	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T37	1		T38	2		T55	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T49	1		T66	1		T115	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T55	1		T112	1		T116	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T37	3		T38	2		T40	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T37	1		T40	2		T55	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T66	2		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T117	1		T113	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T37	1		T38	3		T40	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T37	1		T38	1		T40	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T38	2		T104	2		T77	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T37	1		T55	1		T49	1