Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	520912	1			T2	123		T5	777		T9	49
auto[1]	10795618	1			T1	588		T2	124		T3	23651
auto[2]	449589	1			T2	82		T5	467		T9	43
auto[3]	10730951	1			T1	598		T2	184		T3	23463

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14637873	1			T1	770		T3	39122		T4	55
auto[1]	2149668	1			T1	207		T2	6		T3	3883
auto[2]	2148698	1			T1	163		T2	42		T3	3734
auto[3]	3560831	1			T1	46		T2	465		T3	375

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9099297

1

T1

1186

T2

511

T3

47065

auto[1]

13397773

1

T2

2

T3

49

T6

9

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	225124	1			T5	635		T9	42		T7	11
auto[0]	auto[0]	auto[1]	23358	1			T2	1		T5	75		T9	3
auto[0]	auto[0]	auto[2]	23209	1			T5	59		T9	4		T7	3
auto[0]	auto[0]	auto[3]	8608	1			T2	120		T5	6		T58	94
auto[0]	auto[1]	auto[0]	3509217	1			T1	396		T3	19660		T4	24
auto[0]	auto[1]	auto[1]	358753	1			T1	110		T3	1863		T4	10
auto[0]	auto[1]	auto[2]	354991	1			T1	65		T2	9		T3	1928
auto[0]	auto[1]	auto[3]	81862	1			T1	17		T2	115		T3	176
auto[0]	auto[2]	auto[0]	196531	1			T5	361		T9	30		T7	14
auto[0]	auto[2]	auto[1]	20800	1			T2	3		T5	38		T9	7
auto[0]	auto[2]	auto[2]	18442	1			T2	3		T5	60		T9	6
auto[0]	auto[2]	auto[3]	6842	1			T2	76		T5	7		T58	71
auto[0]	auto[3]	auto[0]	3478968	1			T1	374		T3	19424		T4	31
auto[0]	auto[3]	auto[1]	352354	1			T1	97		T2	2		T3	2013
auto[0]	auto[3]	auto[2]	355990	1			T1	98		T2	30		T3	1802
auto[0]	auto[3]	auto[3]	84248	1			T1	29		T2	152		T3	199
auto[1]	auto[0]	auto[0]	8065	1			T84	404		T122	6		T18	8
auto[1]	auto[0]	auto[1]	35766	1			T5	1		T84	1816		T18	2
auto[1]	auto[0]	auto[2]	35784	1			T5	1		T84	1844		T96	3192
auto[1]	auto[0]	auto[3]	160998	1			T2	2		T58	1		T84	8611
auto[1]	auto[1]	auto[0]	3606364	1			T3	18		T6	1		T5	1
auto[1]	auto[1]	auto[1]	677302	1			T3	3		T6	1		T83	6911
auto[1]	auto[1]	auto[2]	657597	1			T3	3		T6	1		T11	1
auto[1]	auto[1]	auto[3]	1549532	1			T46	8		T83	719		T84	10064
auto[1]	auto[2]	auto[0]	6753	1			T5	1		T84	247		T122	3
auto[1]	auto[2]	auto[1]	30079	1			T84	1139		T18	2		T96	1902
auto[1]	auto[2]	auto[2]	30689	1			T84	2047		T122	1		T96	3098
auto[1]	auto[2]	auto[3]	139453	1			T84	9483		T96	13815		T123	8207
auto[1]	auto[3]	auto[0]	3606851	1			T3	20		T6	5		T10	5
auto[1]	auto[3]	auto[1]	651256	1			T3	4		T6	1		T10	1
auto[1]	auto[3]	auto[2]	671996	1			T3	1		T46	2		T83	7037
auto[1]	auto[3]	auto[3]	1529288	1			T46	1		T83	714		T84	10895