Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	279286376	139206	0	0
ctrl_regwen_rd_A	279286376	5645	0	0
exec_rd_A	279286376	5047	0	0
exec_regwen_rd_A	279286376	5277	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279286376	139206	0	0
T4	130591	2791	0	0
T5	198391	0	0	0
T6	366430	0	0	0
T7	37426	0	0	0
T9	168019	4018	0	0
T10	12012	0	0	0
T11	41999	0	0	0
T22	37003	0	0	0
T23	0	2824	0	0
T37	0	1	0	0
T38	0	4	0	0
T39	0	1424	0	0
T41	0	170	0	0
T42	0	518	0	0
T43	0	93	0	0
T44	0	144	0	0
T46	17978	0	0	0
T47	112966	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279286376	5645	0	0
T23	164239	292	0	0
T26	2166	0	0	0
T37	21471	65	0	0
T38	0	22	0	0
T39	63004	0	0	0
T42	0	113	0	0
T48	0	4	0	0
T50	0	10	0	0
T54	0	9	0	0
T56	0	14	0	0
T92	1182	4	0	0
T104	0	89	0	0
T105	103855	0	0	0
T106	10618	0	0	0
T107	224807	0	0	0
T108	17038	0	0	0
T109	143060	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279286376	5047	0	0
T23	164239	330	0	0
T26	2166	0	0	0
T37	21471	27	0	0
T38	0	27	0	0
T39	63004	0	0	0
T42	0	64	0	0
T48	0	7	0	0
T50	0	8	0	0
T54	0	4	0	0
T56	0	37	0	0
T92	1182	2	0	0
T104	0	77	0	0
T105	103855	0	0	0
T106	10618	0	0	0
T107	224807	0	0	0
T108	17038	0	0	0
T109	143060	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279286376	5277	0	0
T23	164239	318	0	0
T26	2166	0	0	0
T37	21471	35	0	0
T38	0	32	0	0
T39	63004	0	0	0
T42	0	77	0	0
T48	0	9	0	0
T50	0	1	0	0
T54	0	10	0	0
T56	0	23	0	0
T92	1182	4	0	0
T104	0	87	0	0
T105	103855	0	0	0
T106	10618	0	0	0
T107	224807	0	0	0
T108	17038	0	0	0
T109	143060	0	0	0