Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14193240	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

56611526

1

T1

11470

T2

99

T4

132367

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35286277	1			T1	4083		T2	846		T4	72939
values[0x0]	16343329	1			T1	3756		T2	350		T4	34831
values[0x1]	19175160	1			T1	3754		T2	743		T4	37927

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7073444	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63731322

1

T1

11530

T2

873

T4

139065

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	327060	1			T1	7		T2	1		T4	587
valid_sources[0x01]	284721	1			T1	21		T4	641		T9	23
valid_sources[0x02]	300237	1			T1	91		T2	15		T4	570
valid_sources[0x03]	255787	1			T1	38		T2	13		T4	612
valid_sources[0x04]	263792	1			T1	24		T2	13		T4	503
valid_sources[0x05]	248694	1			T1	26		T2	6		T4	595
valid_sources[0x06]	254407	1			T1	65		T2	3		T4	498
valid_sources[0x07]	234032	1			T1	30		T2	7		T4	609
valid_sources[0x08]	257661	1			T1	35		T2	5		T4	517
valid_sources[0x09]	245055	1			T1	88		T2	15		T4	617
valid_sources[0x0a]	303162	1			T1	11		T2	5		T4	602
valid_sources[0x0b]	246137	1			T1	38		T2	5		T4	603
valid_sources[0x0c]	302851	1			T1	74		T2	3		T4	596
valid_sources[0x0d]	298974	1			T1	40		T2	3		T4	512
valid_sources[0x0e]	257250	1			T1	33		T2	2		T4	541
valid_sources[0x0f]	249117	1			T1	71		T4	553		T9	10
valid_sources[0x10]	312184	1			T1	53		T2	8		T4	471
valid_sources[0x11]	237706	1			T1	52		T2	5		T4	714
valid_sources[0x12]	276804	1			T1	75		T2	7		T4	537
valid_sources[0x13]	271342	1			T1	55		T4	611		T9	14
valid_sources[0x14]	247406	1			T1	80		T2	5		T4	498
valid_sources[0x15]	261618	1			T1	66		T2	8		T4	464
valid_sources[0x16]	314647	1			T1	36		T2	2		T4	701
valid_sources[0x17]	321760	1			T1	21		T2	9		T4	585
valid_sources[0x18]	285656	1			T1	52		T2	17		T4	547
valid_sources[0x19]	252112	1			T1	147		T2	8		T4	526
valid_sources[0x1a]	273957	1			T1	19		T2	12		T4	573
valid_sources[0x1b]	273552	1			T1	56		T4	626		T9	7
valid_sources[0x1c]	341018	1			T1	17		T2	9		T4	593
valid_sources[0x1d]	246837	1			T1	47		T2	9		T4	580
valid_sources[0x1e]	248468	1			T1	15		T2	26		T4	622
valid_sources[0x1f]	237297	1			T1	83		T2	2		T4	492
valid_sources[0x20]	333997	1			T1	50		T2	3		T4	557
valid_sources[0x21]	251649	1			T1	24		T2	17		T4	523
valid_sources[0x22]	310885	1			T1	11		T4	536		T9	18
valid_sources[0x23]	260316	1			T1	23		T2	10		T4	436
valid_sources[0x24]	279058	1			T1	72		T2	3		T4	669
valid_sources[0x25]	302049	1			T1	74		T2	8		T4	593
valid_sources[0x26]	267804	1			T1	64		T2	2		T4	642
valid_sources[0x27]	313700	1			T1	37		T2	35		T4	560
valid_sources[0x28]	298087	1			T1	33		T2	12		T4	434
valid_sources[0x29]	245209	1			T1	24		T2	1		T4	601
valid_sources[0x2a]	249899	1			T1	25		T2	16		T4	569
valid_sources[0x2b]	250354	1			T1	17		T4	470		T9	11
valid_sources[0x2c]	252695	1			T1	26		T2	16		T4	643
valid_sources[0x2d]	267004	1			T1	54		T2	1		T4	567
valid_sources[0x2e]	365077	1			T1	40		T2	8		T4	638
valid_sources[0x2f]	281200	1			T1	37		T2	4		T4	570
valid_sources[0x30]	393659	1			T1	17		T2	29		T4	679
valid_sources[0x31]	307837	1			T1	2		T2	5		T4	516
valid_sources[0x32]	295891	1			T1	31		T2	9		T4	600
valid_sources[0x33]	245666	1			T1	46		T2	3		T4	571
valid_sources[0x34]	247014	1			T1	57		T4	595		T9	12
valid_sources[0x35]	289966	1			T1	32		T2	22		T4	576
valid_sources[0x36]	303947	1			T1	51		T2	7		T4	606
valid_sources[0x37]	295005	1			T1	6		T2	17		T4	496
valid_sources[0x38]	317022	1			T1	48		T2	5		T4	506
valid_sources[0x39]	332604	1			T1	42		T2	3		T4	584
valid_sources[0x3a]	248290	1			T1	49		T2	2		T4	551
valid_sources[0x3b]	322649	1			T1	81		T2	15		T4	519
valid_sources[0x3c]	278149	1			T1	45		T2	3		T4	732
valid_sources[0x3d]	266697	1			T1	81		T4	623		T9	9
valid_sources[0x3e]	265293	1			T1	21		T2	16		T4	556
valid_sources[0x3f]	303425	1			T1	45		T2	10		T4	551
valid_sources[0x40]	236132	1			T1	5		T2	12		T4	631
valid_sources[0x41]	330569	1			T1	68		T2	4		T4	593
valid_sources[0x42]	372516	1			T1	28		T2	20		T4	592
valid_sources[0x43]	278150	1			T1	22		T2	9		T4	541
valid_sources[0x44]	284855	1			T1	69		T2	23		T4	618
valid_sources[0x45]	254547	1			T1	10		T2	12		T4	634
valid_sources[0x46]	241561	1			T1	95		T2	12		T4	610
valid_sources[0x47]	234087	1			T1	26		T2	7		T4	527
valid_sources[0x48]	308328	1			T1	55		T2	9		T4	562
valid_sources[0x49]	273403	1			T1	72		T2	16		T4	554
valid_sources[0x4a]	255527	1			T1	35		T2	22		T4	601
valid_sources[0x4b]	245245	1			T1	27		T2	6		T4	520
valid_sources[0x4c]	258601	1			T1	45		T2	7		T4	588
valid_sources[0x4d]	265804	1			T1	61		T2	2		T4	545
valid_sources[0x4e]	274355	1			T1	50		T2	6		T4	552
valid_sources[0x4f]	317480	1			T1	42		T2	5		T4	584
valid_sources[0x50]	251013	1			T1	59		T2	12		T4	528
valid_sources[0x51]	251944	1			T1	6		T2	11		T4	560
valid_sources[0x52]	259643	1			T1	39		T2	4		T4	461
valid_sources[0x53]	294579	1			T1	34		T2	20		T4	569
valid_sources[0x54]	322250	1			T1	55		T2	3		T4	623
valid_sources[0x55]	263920	1			T1	35		T2	13		T4	586
valid_sources[0x56]	284427	1			T1	58		T2	2		T4	569
valid_sources[0x57]	261793	1			T1	19		T2	4		T4	543
valid_sources[0x58]	313519	1			T1	59		T2	1		T4	570
valid_sources[0x59]	234675	1			T1	33		T2	2		T4	593
valid_sources[0x5a]	265412	1			T1	40		T2	1		T4	631
valid_sources[0x5b]	242844	1			T1	72		T2	3		T4	564
valid_sources[0x5c]	244873	1			T1	19		T2	5		T4	518
valid_sources[0x5d]	254704	1			T1	61		T2	3		T4	484
valid_sources[0x5e]	236843	1			T1	48		T2	7		T4	585
valid_sources[0x5f]	252760	1			T1	63		T2	9		T4	535
valid_sources[0x60]	237251	1			T1	65		T2	5		T4	606
valid_sources[0x61]	279271	1			T1	79		T2	4		T4	568
valid_sources[0x62]	283250	1			T1	31		T2	9		T4	546
valid_sources[0x63]	262459	1			T1	60		T2	20		T4	505
valid_sources[0x64]	256519	1			T1	25		T2	3		T4	587
valid_sources[0x65]	244596	1			T1	46		T2	28		T4	522
valid_sources[0x66]	262427	1			T1	71		T4	502		T9	10
valid_sources[0x67]	284481	1			T1	62		T4	599		T9	23
valid_sources[0x68]	314329	1			T1	64		T4	534		T9	12
valid_sources[0x69]	234308	1			T1	65		T2	2		T4	493
valid_sources[0x6a]	245015	1			T1	13		T2	8		T4	662
valid_sources[0x6b]	267867	1			T1	16		T4	475		T9	33
valid_sources[0x6c]	275144	1			T1	49		T2	9		T4	477
valid_sources[0x6d]	253020	1			T1	25		T2	22		T4	581
valid_sources[0x6e]	272804	1			T1	35		T2	10		T4	625
valid_sources[0x6f]	244503	1			T1	62		T2	22		T4	535
valid_sources[0x70]	253419	1			T1	69		T2	10		T4	469
valid_sources[0x71]	255937	1			T1	50		T2	5		T4	622
valid_sources[0x72]	311725	1			T1	66		T2	4		T4	552
valid_sources[0x73]	341969	1			T1	60		T4	601		T9	8
valid_sources[0x74]	256296	1			T1	70		T2	4		T4	545
valid_sources[0x75]	232398	1			T1	36		T2	21		T4	637
valid_sources[0x76]	261621	1			T1	43		T2	1		T4	645
valid_sources[0x77]	289297	1			T1	61		T2	10		T4	612
valid_sources[0x78]	266116	1			T1	51		T2	2		T4	619
valid_sources[0x79]	300326	1			T1	32		T2	7		T4	536
valid_sources[0x7a]	268962	1			T1	23		T2	7		T4	521
valid_sources[0x7b]	292712	1			T1	19		T4	548		T9	10
valid_sources[0x7c]	267448	1			T1	54		T4	588		T9	10
valid_sources[0x7d]	313175	1			T1	7		T4	594		T9	4
valid_sources[0x7e]	262047	1			T1	21		T4	474		T9	18
valid_sources[0x7f]	303549	1			T1	87		T4	557		T9	6
valid_sources[0x80]	306674	1			T1	130		T2	12		T4	611

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28189155

1

T1

4030

T2

7

T4

66281

values[0x0]

all_enables

biggest_size

14211260

1

T1

3735

T2

37

T4

32886

values[0x1]

all_enables

biggest_size

14211111

1

T1

3705

T2

55

T4

33200

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1995793	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156358

1

T1

1299

T2

1

T4

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2017629	1			T1	1242		T2	128		T3	145
values[0x0]	64988	1			T1	488		T2	1		T4	22
values[0x1]	69534	1			T1	521		T3	1		T4	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1332964	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

819187

1

T1

1619

T2

50

T3

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7239	1			T1	2		T9	11		T5	4
valid_sources[0x01]	6717	1			T1	10		T9	8		T5	3
valid_sources[0x02]	6743	1			T1	5		T2	1		T9	5
valid_sources[0x03]	8635	1			T1	13		T9	4		T5	4
valid_sources[0x04]	8058	1			T1	1		T9	1		T5	4
valid_sources[0x05]	7401	1			T1	14		T2	1		T9	5
valid_sources[0x06]	6460	1			T1	18		T2	1		T9	3
valid_sources[0x07]	7024	1			T1	11		T9	12		T5	3
valid_sources[0x08]	6090	1			T1	9		T3	1		T9	5
valid_sources[0x09]	6407	1			T1	7		T5	1		T10	5
valid_sources[0x0a]	16009	1			T1	11		T3	1		T9	6
valid_sources[0x0b]	6870	1			T1	3		T3	1		T9	8
valid_sources[0x0c]	22093	1			T1	6		T3	1		T9	5
valid_sources[0x0d]	6292	1			T1	8		T9	3		T5	1
valid_sources[0x0e]	5925	1			T1	3		T9	4		T5	2
valid_sources[0x0f]	7367	1			T1	12		T9	3		T5	1
valid_sources[0x10]	6514	1			T1	7		T3	1		T9	2
valid_sources[0x11]	7332	1			T1	7		T2	1		T9	5
valid_sources[0x12]	11295	1			T1	4		T3	1		T9	3
valid_sources[0x13]	11001	1			T1	5		T9	5		T5	3
valid_sources[0x14]	6384	1			T1	8		T3	1		T9	5
valid_sources[0x15]	15206	1			T1	11		T9	2		T5	3
valid_sources[0x16]	5993	1			T1	7		T2	1		T3	1
valid_sources[0x17]	13806	1			T1	1		T2	1		T9	5
valid_sources[0x18]	6556	1			T1	14		T2	1		T9	6
valid_sources[0x19]	6003	1			T1	4		T2	1		T9	4
valid_sources[0x1a]	9267	1			T1	6		T9	2		T10	4
valid_sources[0x1b]	6317	1			T1	15		T2	1		T9	11
valid_sources[0x1c]	6910	1			T1	3		T9	3		T5	3
valid_sources[0x1d]	6898	1			T1	9		T3	4		T5	3
valid_sources[0x1e]	6181	1			T1	3		T9	5		T5	2
valid_sources[0x1f]	6165	1			T1	6		T9	3		T5	2
valid_sources[0x20]	6332	1			T1	8		T2	1		T3	2
valid_sources[0x21]	6521	1			T1	9		T2	1		T9	11
valid_sources[0x22]	6396	1			T1	8		T9	4		T11	6
valid_sources[0x23]	7686	1			T1	16		T2	1		T9	2
valid_sources[0x24]	6907	1			T1	9		T2	1		T9	2
valid_sources[0x25]	6791	1			T1	14		T3	2		T9	12
valid_sources[0x26]	6435	1			T1	14		T5	3		T10	3
valid_sources[0x27]	6839	1			T1	5		T3	1		T9	9
valid_sources[0x28]	6141	1			T1	15		T9	10		T5	5
valid_sources[0x29]	6849	1			T1	8		T9	6		T5	5
valid_sources[0x2a]	6430	1			T1	10		T2	1		T5	5
valid_sources[0x2b]	6456	1			T9	4		T5	1		T11	2
valid_sources[0x2c]	6961	1			T1	15		T9	5		T5	2
valid_sources[0x2d]	6766	1			T1	18		T2	1		T3	3
valid_sources[0x2e]	8276	1			T1	5		T9	6		T5	3
valid_sources[0x2f]	6079	1			T1	6		T2	1		T9	8
valid_sources[0x30]	6123	1			T1	8		T5	3		T11	1
valid_sources[0x31]	6468	1			T1	6		T2	1		T9	9
valid_sources[0x32]	6671	1			T1	6		T2	3		T9	3
valid_sources[0x33]	13246	1			T1	3		T5	1		T10	4
valid_sources[0x34]	6314	1			T1	6		T9	10		T5	3
valid_sources[0x35]	6545	1			T1	9		T5	3		T11	8
valid_sources[0x36]	7033	1			T1	18		T2	1		T9	8
valid_sources[0x37]	7907	1			T1	6		T3	2		T9	4
valid_sources[0x38]	13855	1			T1	8		T2	1		T9	1
valid_sources[0x39]	7205	1			T1	6		T9	7		T5	4
valid_sources[0x3a]	6127	1			T1	10		T3	3		T9	7
valid_sources[0x3b]	6251	1			T1	19		T2	1		T9	6
valid_sources[0x3c]	6108	1			T1	13		T9	5		T5	2
valid_sources[0x3d]	8635	1			T1	11		T2	2		T9	5
valid_sources[0x3e]	7370	1			T1	6		T9	4		T5	4
valid_sources[0x3f]	6081	1			T1	20		T2	2		T3	4
valid_sources[0x40]	6273	1			T1	16		T2	1		T9	4
valid_sources[0x41]	7782	1			T1	4		T2	2		T9	4
valid_sources[0x42]	6298	1			T1	15		T2	1		T9	7
valid_sources[0x43]	7166	1			T1	7		T2	1		T9	4
valid_sources[0x44]	6055	1			T1	22		T2	1		T9	5
valid_sources[0x45]	7298	1			T1	7		T5	3		T11	2
valid_sources[0x46]	6298	1			T1	3		T2	1		T9	7
valid_sources[0x47]	6548	1			T1	6		T9	6		T5	4
valid_sources[0x48]	6344	1			T1	8		T2	3		T3	5
valid_sources[0x49]	6146	1			T1	2		T2	1		T9	2
valid_sources[0x4a]	12333	1			T1	7		T9	9		T5	3
valid_sources[0x4b]	9734	1			T1	2		T3	6		T9	4
valid_sources[0x4c]	6023	1			T1	13		T2	1		T9	2
valid_sources[0x4d]	7326	1			T1	5		T2	2		T3	1
valid_sources[0x4e]	6099	1			T1	7		T9	3		T5	3
valid_sources[0x4f]	6649	1			T1	15		T2	1		T9	1
valid_sources[0x50]	6484	1			T1	7		T9	1		T5	1
valid_sources[0x51]	14022	1			T1	14		T9	5		T5	6
valid_sources[0x52]	6475	1			T1	8		T9	2		T5	6
valid_sources[0x53]	7355	1			T1	9		T9	5		T5	3
valid_sources[0x54]	6081	1			T1	6		T9	3		T5	1
valid_sources[0x55]	16424	1			T1	14		T9	4		T5	4
valid_sources[0x56]	9359	1			T1	18		T9	3		T5	2
valid_sources[0x57]	14152	1			T1	6		T9	3		T5	1
valid_sources[0x58]	7589	1			T1	1		T2	1		T9	6
valid_sources[0x59]	6149	1			T1	11		T2	1		T9	10
valid_sources[0x5a]	19137	1			T1	6		T2	1		T3	2
valid_sources[0x5b]	6026	1			T1	5		T9	2		T5	3
valid_sources[0x5c]	7840	1			T1	11		T4	629		T9	1
valid_sources[0x5d]	6034	1			T1	3		T9	10		T5	2
valid_sources[0x5e]	7095	1			T1	4		T9	4		T5	3
valid_sources[0x5f]	5911	1			T1	16		T2	1		T9	3
valid_sources[0x60]	8616	1			T1	8		T9	6		T5	3
valid_sources[0x61]	8048	1			T1	2		T3	1		T9	6
valid_sources[0x62]	8895	1			T1	6		T9	4		T5	1
valid_sources[0x63]	6663	1			T1	18		T2	1		T9	3
valid_sources[0x64]	6453	1			T1	4		T9	5		T5	5
valid_sources[0x65]	7391	1			T1	11		T2	1		T3	5
valid_sources[0x66]	9247	1			T1	23		T2	1		T9	5
valid_sources[0x67]	6742	1			T1	7		T2	1		T9	1
valid_sources[0x68]	7398	1			T1	9		T2	2		T3	1
valid_sources[0x69]	7576	1			T1	17		T2	3		T3	2
valid_sources[0x6a]	6711	1			T1	6		T9	8		T5	5
valid_sources[0x6b]	13101	1			T1	6		T2	1		T9	7
valid_sources[0x6c]	9870	1			T1	16		T2	1		T9	2
valid_sources[0x6d]	6342	1			T1	6		T9	1		T5	2
valid_sources[0x6e]	6709	1			T1	9		T9	2		T5	6
valid_sources[0x6f]	6304	1			T1	3		T9	1		T5	2
valid_sources[0x70]	6396	1			T1	13		T9	3		T5	2
valid_sources[0x71]	6822	1			T1	12		T9	7		T5	1
valid_sources[0x72]	7349	1			T1	8		T9	4		T5	6
valid_sources[0x73]	14010	1			T1	9		T2	1		T9	4
valid_sources[0x74]	21290	1			T1	6		T5	1		T10	13
valid_sources[0x75]	7321	1			T1	1		T3	3		T9	8
valid_sources[0x76]	8503	1			T1	11		T2	2		T3	2
valid_sources[0x77]	6714	1			T1	14		T9	5		T5	3
valid_sources[0x78]	11417	1			T1	12		T2	1		T9	2
valid_sources[0x79]	6429	1			T1	8		T2	2		T3	2
valid_sources[0x7a]	6498	1			T1	5		T2	3		T9	8
valid_sources[0x7b]	8057	1			T1	6		T9	5		T5	2
valid_sources[0x7c]	19757	1			T1	19		T9	9		T5	1
valid_sources[0x7d]	8815	1			T1	3		T2	1		T3	1
valid_sources[0x7e]	9067	1			T1	10		T9	2		T5	5
valid_sources[0x7f]	19381	1			T1	14		T9	9		T5	2
valid_sources[0x80]	7762	1			T1	6		T2	3		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42306

1

T1

325

T4

6

T14

286

values[0x0]

all_enables

biggest_size

57808

1

T1

486

T2

1

T4

7

values[0x1]

all_enables

biggest_size

56244

1

T1

488

T4

9

T10

3