Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13945975

1

T1

1626

T2

1840

T4

10651

full_word

51776046

1

T1

11492

T2

99

T4

105790

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65721681	1			T1	13118		T2	1939		T4	116441
auto[TlIntgErrCmd]	115	1			T42	8		T43	5		T44	5
auto[TlIntgErrData]	116	1			T42	4		T43	7		T44	6
auto[TlIntgErrBoth]	109	1			T42	8		T43	8		T44	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30074327

1

T1

4229

T2

846

T4

43683

auto[1]

35647694

1

T1

8889

T2

1093

T4

72758

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6665821	1			T1	323		T2	839		T4	3979
auto[TlIntgErrNone]	partial	auto[1]	7279840	1			T1	1303		T2	1001		T4	6672
auto[TlIntgErrNone]	full_word	auto[0]	23408352	1			T1	3906		T2	7		T4	39704
auto[TlIntgErrNone]	full_word	auto[1]	28367668	1			T1	7586		T2	92		T4	66086
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T42	1		T44	1		T70	1
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T42	6		T43	3		T44	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T43	2		T81	1		T96	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T42	1		T96	1		T99	1
auto[TlIntgErrData]	partial	auto[0]	59	1			T42	2		T43	2		T44	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T42	2		T43	4		T44	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T44	1		T70	2		T96	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T43	1		T95	1		T100	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T42	6		T43	2		T44	4
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T42	1		T43	6		T44	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T44	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T42	1		T97	1		T101	1