Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	824752	1			T2	232		T5	29888		T13	14741
auto[1]	9806337	1			T2	210		T4	399		T9	1809
auto[2]	688710	1			T2	173		T5	21681		T13	10720
auto[3]	9672129	1			T2	250		T4	362		T9	1833

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13121979	1			T4	542		T9	2423		T5	2133
auto[1]	2049708	1			T2	24		T4	99		T9	538
auto[2]	2033460	1			T2	20		T4	103		T9	545
auto[3]	3786781	1			T2	821		T4	17		T9	136

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7695226

1

T2

865

T4

760

T9

3637

auto[1]

13296702

1

T4

1

T9

5

T5

94484

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	289966	1			T14	24		T7	4735		T21	485
auto[0]	auto[0]	auto[1]	29909	1			T2	4		T13	2		T14	6
auto[0]	auto[0]	auto[2]	29932	1			T2	2		T13	1		T14	3
auto[0]	auto[0]	auto[3]	8561	1			T2	226		T13	3		T7	45
auto[0]	auto[1]	auto[0]	2874814	1			T4	289		T9	1208		T11	203
auto[0]	auto[1]	auto[1]	307266	1			T4	70		T9	266		T11	59
auto[0]	auto[1]	auto[2]	289745	1			T2	4		T4	28		T9	272
auto[0]	auto[1]	auto[3]	58831	1			T2	206		T4	11		T9	59
auto[0]	auto[2]	auto[0]	257109	1			T14	11		T7	2885		T21	290
auto[0]	auto[2]	auto[1]	26616	1			T2	19		T14	1		T7	312
auto[0]	auto[2]	auto[2]	22129	1			T2	2		T13	1		T14	1
auto[0]	auto[2]	auto[3]	6904	1			T2	152		T13	3		T7	52
auto[0]	auto[3]	auto[0]	2845699	1			T4	252		T9	1213		T11	242
auto[0]	auto[3]	auto[1]	285311	1			T2	1		T4	29		T9	271
auto[0]	auto[3]	auto[2]	301225	1			T2	12		T4	75		T9	271
auto[0]	auto[3]	auto[3]	61209	1			T2	237		T4	6		T9	77
auto[1]	auto[0]	auto[0]	15774	1			T5	1006		T13	479		T52	644
auto[1]	auto[0]	auto[1]	69393	1			T5	4549		T13	2173		T52	2963
auto[1]	auto[0]	auto[2]	69564	1			T5	4499		T13	2221		T52	3112
auto[1]	auto[0]	auto[3]	311653	1			T5	19834		T13	9862		T52	13574
auto[1]	auto[1]	auto[0]	3414859	1			T4	1		T9	2		T5	160
auto[1]	auto[1]	auto[1]	660362	1			T5	4506		T13	2215		T15	1
auto[1]	auto[1]	auto[2]	621174	1			T9	2		T5	789		T13	368
auto[1]	auto[1]	auto[3]	1579286	1			T5	20112		T13	10081		T52	13466
auto[1]	auto[2]	auto[0]	13895	1			T5	858		T13	438		T52	652
auto[1]	auto[2]	auto[1]	60764	1			T5	4192		T13	2061		T52	2796
auto[1]	auto[2]	auto[2]	54619	1			T5	3003		T13	1463		T52	2012
auto[1]	auto[2]	auto[3]	246674	1			T5	13628		T13	6754		T52	9060
auto[1]	auto[3]	auto[0]	3409863	1			T5	109		T12	2		T13	46
auto[1]	auto[3]	auto[1]	610087	1			T9	1		T5	445		T13	202
auto[1]	auto[3]	auto[2]	645072	1			T5	3094		T12	1		T13	1502
auto[1]	auto[3]	auto[3]	1513663	1			T5	13700		T13	6594		T52	9417