Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	315320035	156303	0	0
ctrl_regwen_rd_A	315320035	7498	0	0
exec_rd_A	315320035	6440	0	0
exec_regwen_rd_A	315320035	7171	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315320035	156303	0	0
T1	26139	950	0	0
T2	16744	0	0	0
T3	1802	0	0	0
T4	940102	0	0	0
T5	202567	0	0	0
T9	7435	0	0	0
T10	104783	0	0	0
T11	945537	0	0	0
T12	9022	0	0	0
T13	990827	0	0	0
T14	0	521	0	0
T26	0	2528	0	0
T29	0	4969	0	0
T45	0	1445	0	0
T46	0	3061	0	0
T47	0	8	0	0
T48	0	19	0	0
T49	0	10	0	0
T50	0	157	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315320035	7498	0	0
T42	15834	93	0	0
T43	0	65	0	0
T47	2698	27	0	0
T49	3356	31	0	0
T50	8129	35	0	0
T51	7958	69	0	0
T54	1033	9	0	0
T56	17072	441	0	0
T58	1579	3	0	0
T59	2228	0	0	0
T88	1200	11	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315320035	6440	0	0
T42	0	87	0	0
T47	2698	24	0	0
T49	3356	20	0	0
T50	8129	24	0	0
T51	7958	40	0	0
T54	1033	5	0	0
T55	1123	5	0	0
T56	17072	459	0	0
T58	1579	2	0	0
T59	2228	0	0	0
T88	1200	4	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315320035	7171	0	0
T42	0	79	0	0
T47	2698	3	0	0
T49	3356	22	0	0
T50	8129	38	0	0
T51	7958	50	0	0
T54	1033	15	0	0
T55	1123	5	0	0
T56	17072	456	0	0
T58	1579	6	0	0
T59	2228	0	0	0
T88	1200	15	0	0