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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.50 100.00 98.18 100.00 100.00 99.71 99.70 98.89


Total test records in report: 982
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T752 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2615074105 Jan 24 06:12:52 PM PST 24 Jan 24 06:12:54 PM PST 24 83229769 ps
T753 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2918104882 Jan 24 06:24:27 PM PST 24 Jan 24 06:28:05 PM PST 24 12714516581 ps
T754 /workspace/coverage/default/37.sram_ctrl_stress_all.2097855726 Jan 24 06:26:26 PM PST 24 Jan 24 06:50:50 PM PST 24 27192037367 ps
T755 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2745974169 Jan 24 05:56:05 PM PST 24 Jan 24 05:56:15 PM PST 24 247803800 ps
T756 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.4262878381 Jan 24 07:50:39 PM PST 24 Jan 24 07:54:31 PM PST 24 1061880315 ps
T757 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3641789320 Jan 24 06:36:24 PM PST 24 Jan 24 06:36:39 PM PST 24 2394991583 ps
T758 /workspace/coverage/default/34.sram_ctrl_mem_walk.1833383473 Jan 24 07:27:25 PM PST 24 Jan 24 07:27:30 PM PST 24 285607325 ps
T759 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3614198051 Jan 24 07:08:34 PM PST 24 Jan 24 07:08:44 PM PST 24 579568739 ps
T760 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.4109928438 Jan 24 07:54:33 PM PST 24 Jan 24 07:58:41 PM PST 24 7257278980 ps
T761 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.4200901034 Jan 24 05:42:07 PM PST 24 Jan 24 05:46:11 PM PST 24 3373582067 ps
T762 /workspace/coverage/default/41.sram_ctrl_stress_all.3770469498 Jan 24 07:02:25 PM PST 24 Jan 24 08:17:26 PM PST 24 243456202663 ps
T763 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1757025202 Jan 24 06:40:51 PM PST 24 Jan 24 06:40:54 PM PST 24 41106380 ps
T764 /workspace/coverage/default/42.sram_ctrl_regwen.1414489948 Jan 24 06:31:48 PM PST 24 Jan 24 06:36:34 PM PST 24 8965382542 ps
T765 /workspace/coverage/default/41.sram_ctrl_smoke.1926354461 Jan 24 06:29:56 PM PST 24 Jan 24 06:30:11 PM PST 24 730562726 ps
T766 /workspace/coverage/default/7.sram_ctrl_mem_walk.2629259523 Jan 24 05:49:51 PM PST 24 Jan 24 05:49:56 PM PST 24 77770671 ps
T767 /workspace/coverage/default/2.sram_ctrl_alert_test.1745066558 Jan 24 05:45:34 PM PST 24 Jan 24 05:45:40 PM PST 24 16190757 ps
T768 /workspace/coverage/default/47.sram_ctrl_stress_all.1242636919 Jan 24 06:38:17 PM PST 24 Jan 24 07:04:40 PM PST 24 36712811383 ps
T769 /workspace/coverage/default/18.sram_ctrl_max_throughput.2246678707 Jan 24 05:59:27 PM PST 24 Jan 24 06:01:43 PM PST 24 126676061 ps
T770 /workspace/coverage/default/20.sram_ctrl_multiple_keys.100390180 Jan 24 06:01:39 PM PST 24 Jan 24 06:16:16 PM PST 24 20216656098 ps
T771 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1875996002 Jan 24 05:56:53 PM PST 24 Jan 24 05:59:22 PM PST 24 6243948066 ps
T772 /workspace/coverage/default/42.sram_ctrl_executable.2998011629 Jan 24 06:31:42 PM PST 24 Jan 24 07:04:33 PM PST 24 4539518320 ps
T773 /workspace/coverage/default/37.sram_ctrl_mem_walk.2036599875 Jan 24 06:26:12 PM PST 24 Jan 24 06:26:26 PM PST 24 1770276557 ps
T774 /workspace/coverage/default/45.sram_ctrl_alert_test.1464895219 Jan 24 06:35:36 PM PST 24 Jan 24 06:35:37 PM PST 24 27155999 ps
T775 /workspace/coverage/default/43.sram_ctrl_regwen.2613314669 Jan 24 06:32:38 PM PST 24 Jan 24 06:58:09 PM PST 24 6773221245 ps
T776 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3236409505 Jan 24 06:23:50 PM PST 24 Jan 24 06:59:08 PM PST 24 1497015830 ps
T777 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4255087234 Jan 24 05:58:17 PM PST 24 Jan 24 05:58:42 PM PST 24 433007446 ps
T778 /workspace/coverage/default/3.sram_ctrl_max_throughput.3321124881 Jan 24 05:55:17 PM PST 24 Jan 24 05:56:17 PM PST 24 192065961 ps
T779 /workspace/coverage/default/26.sram_ctrl_max_throughput.1207544055 Jan 24 06:10:45 PM PST 24 Jan 24 06:11:08 PM PST 24 883117429 ps
T780 /workspace/coverage/default/47.sram_ctrl_ram_cfg.135266691 Jan 24 06:37:58 PM PST 24 Jan 24 06:38:00 PM PST 24 81514210 ps
T781 /workspace/coverage/default/3.sram_ctrl_partial_access.382130013 Jan 24 08:17:43 PM PST 24 Jan 24 08:17:56 PM PST 24 488369638 ps
T782 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1939570013 Jan 24 06:06:47 PM PST 24 Jan 24 06:06:53 PM PST 24 304936790 ps
T783 /workspace/coverage/default/35.sram_ctrl_bijection.3495325979 Jan 24 06:22:48 PM PST 24 Jan 24 06:24:03 PM PST 24 4404612746 ps
T784 /workspace/coverage/default/10.sram_ctrl_ram_cfg.3764517820 Jan 24 05:52:29 PM PST 24 Jan 24 05:52:31 PM PST 24 45906965 ps
T785 /workspace/coverage/default/14.sram_ctrl_bijection.2362797590 Jan 24 05:54:54 PM PST 24 Jan 24 05:56:05 PM PST 24 9817989890 ps
T786 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2162293964 Jan 24 06:21:52 PM PST 24 Jan 24 06:47:12 PM PST 24 13293433502 ps
T787 /workspace/coverage/default/25.sram_ctrl_regwen.847509286 Jan 24 06:10:02 PM PST 24 Jan 24 06:20:41 PM PST 24 7065664431 ps
T788 /workspace/coverage/default/0.sram_ctrl_max_throughput.2730849667 Jan 24 05:42:04 PM PST 24 Jan 24 05:42:09 PM PST 24 89409923 ps
T789 /workspace/coverage/default/34.sram_ctrl_regwen.908894283 Jan 24 06:21:59 PM PST 24 Jan 24 06:50:53 PM PST 24 13443218426 ps
T790 /workspace/coverage/default/47.sram_ctrl_regwen.467767619 Jan 24 06:38:00 PM PST 24 Jan 24 06:50:10 PM PST 24 32097512108 ps
T791 /workspace/coverage/default/10.sram_ctrl_mem_walk.3203874412 Jan 24 05:52:28 PM PST 24 Jan 24 05:52:34 PM PST 24 927485199 ps
T792 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.925580572 Jan 24 06:24:46 PM PST 24 Jan 24 06:42:49 PM PST 24 3569879401 ps
T793 /workspace/coverage/default/28.sram_ctrl_lc_escalation.177535766 Jan 24 06:25:54 PM PST 24 Jan 24 06:26:09 PM PST 24 824607384 ps
T794 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.474398750 Jan 24 06:02:54 PM PST 24 Jan 24 06:08:12 PM PST 24 971913352 ps
T795 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3024921379 Jan 24 05:47:02 PM PST 24 Jan 24 05:48:33 PM PST 24 508080924 ps
T796 /workspace/coverage/default/5.sram_ctrl_stress_all.1958221067 Jan 24 05:48:30 PM PST 24 Jan 24 06:13:22 PM PST 24 19773197476 ps
T797 /workspace/coverage/default/42.sram_ctrl_mem_walk.2068443475 Jan 24 06:31:49 PM PST 24 Jan 24 06:31:58 PM PST 24 357283288 ps
T798 /workspace/coverage/default/20.sram_ctrl_mem_walk.2951138458 Jan 24 06:03:24 PM PST 24 Jan 24 06:03:30 PM PST 24 1344794076 ps
T799 /workspace/coverage/default/44.sram_ctrl_lc_escalation.2017411873 Jan 24 06:33:37 PM PST 24 Jan 24 06:33:52 PM PST 24 1955447146 ps
T800 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1856698673 Jan 24 07:16:12 PM PST 24 Jan 24 07:16:56 PM PST 24 485708790 ps
T801 /workspace/coverage/default/0.sram_ctrl_partial_access.874234693 Jan 24 08:02:14 PM PST 24 Jan 24 08:02:31 PM PST 24 3158051519 ps
T802 /workspace/coverage/default/5.sram_ctrl_mem_walk.2974868076 Jan 24 06:29:09 PM PST 24 Jan 24 06:29:15 PM PST 24 1231985666 ps
T803 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.4138125022 Jan 24 05:59:29 PM PST 24 Jan 24 06:00:49 PM PST 24 130168358 ps
T804 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.359289579 Jan 24 06:35:51 PM PST 24 Jan 24 06:40:04 PM PST 24 2670923288 ps
T805 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.4152452516 Jan 24 05:53:30 PM PST 24 Jan 24 05:53:34 PM PST 24 161226840 ps
T806 /workspace/coverage/default/32.sram_ctrl_regwen.3672267141 Jan 24 06:19:33 PM PST 24 Jan 24 06:37:08 PM PST 24 29418941361 ps
T807 /workspace/coverage/default/48.sram_ctrl_alert_test.1589905071 Jan 24 06:39:41 PM PST 24 Jan 24 06:39:44 PM PST 24 15439569 ps
T808 /workspace/coverage/default/4.sram_ctrl_stress_all.236875798 Jan 24 07:11:53 PM PST 24 Jan 24 09:29:00 PM PST 24 162292130095 ps
T809 /workspace/coverage/default/7.sram_ctrl_regwen.3487689169 Jan 24 05:49:54 PM PST 24 Jan 24 06:05:16 PM PST 24 10725809754 ps
T810 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3596991949 Jan 24 06:20:32 PM PST 24 Jan 24 06:27:32 PM PST 24 24811888220 ps
T811 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3902754268 Jan 24 05:44:56 PM PST 24 Jan 24 05:46:19 PM PST 24 193082236 ps
T812 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2769116114 Jan 24 06:38:13 PM PST 24 Jan 24 07:12:00 PM PST 24 1529325564 ps
T813 /workspace/coverage/default/40.sram_ctrl_bijection.1306363939 Jan 24 06:29:01 PM PST 24 Jan 24 06:29:26 PM PST 24 1088831749 ps
T814 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3774632029 Jan 24 05:53:20 PM PST 24 Jan 24 05:59:26 PM PST 24 64348312622 ps
T815 /workspace/coverage/default/20.sram_ctrl_bijection.2538352165 Jan 24 06:02:10 PM PST 24 Jan 24 06:03:20 PM PST 24 1106320055 ps
T816 /workspace/coverage/default/20.sram_ctrl_partial_access.987744926 Jan 24 06:02:19 PM PST 24 Jan 24 06:03:45 PM PST 24 190800943 ps
T817 /workspace/coverage/default/34.sram_ctrl_ram_cfg.727254183 Jan 24 06:22:12 PM PST 24 Jan 24 06:22:13 PM PST 24 26595277 ps
T818 /workspace/coverage/default/15.sram_ctrl_regwen.1412518605 Jan 24 05:56:33 PM PST 24 Jan 24 06:07:29 PM PST 24 31055747605 ps
T819 /workspace/coverage/default/36.sram_ctrl_ram_cfg.3189035973 Jan 24 07:04:53 PM PST 24 Jan 24 07:04:55 PM PST 24 28513477 ps
T820 /workspace/coverage/default/32.sram_ctrl_ram_cfg.2387455981 Jan 24 06:19:39 PM PST 24 Jan 24 06:19:40 PM PST 24 93679578 ps
T33 /workspace/coverage/default/2.sram_ctrl_sec_cm.802503253 Jan 24 05:45:33 PM PST 24 Jan 24 05:45:37 PM PST 24 562265881 ps
T821 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1041078174 Jan 24 05:52:16 PM PST 24 Jan 24 05:56:15 PM PST 24 16069772814 ps
T822 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.4048678149 Jan 24 05:58:11 PM PST 24 Jan 24 06:02:22 PM PST 24 9513478530 ps
T823 /workspace/coverage/default/16.sram_ctrl_bijection.2591111370 Jan 24 05:56:50 PM PST 24 Jan 24 05:58:07 PM PST 24 13940246009 ps
T824 /workspace/coverage/default/9.sram_ctrl_mem_walk.1995908786 Jan 24 05:52:11 PM PST 24 Jan 24 05:52:16 PM PST 24 145617184 ps
T825 /workspace/coverage/default/41.sram_ctrl_lc_escalation.1438534245 Jan 24 08:00:26 PM PST 24 Jan 24 08:00:42 PM PST 24 1896595589 ps
T826 /workspace/coverage/default/29.sram_ctrl_ram_cfg.1776734206 Jan 24 07:15:34 PM PST 24 Jan 24 07:15:36 PM PST 24 29947096 ps
T827 /workspace/coverage/default/45.sram_ctrl_regwen.1209063386 Jan 24 06:35:10 PM PST 24 Jan 24 06:45:36 PM PST 24 48153723072 ps
T828 /workspace/coverage/default/38.sram_ctrl_bijection.741375999 Jan 24 06:26:54 PM PST 24 Jan 24 06:27:51 PM PST 24 3415273458 ps
T829 /workspace/coverage/default/49.sram_ctrl_smoke.1992897653 Jan 24 06:39:40 PM PST 24 Jan 24 06:39:45 PM PST 24 46382273 ps
T830 /workspace/coverage/default/49.sram_ctrl_stress_all.3398090222 Jan 24 07:20:00 PM PST 24 Jan 24 08:16:00 PM PST 24 9505378828 ps
T831 /workspace/coverage/default/45.sram_ctrl_ram_cfg.3154015799 Jan 24 07:54:58 PM PST 24 Jan 24 07:55:04 PM PST 24 35926544 ps
T832 /workspace/coverage/default/47.sram_ctrl_alert_test.2258926612 Jan 24 06:38:25 PM PST 24 Jan 24 06:38:26 PM PST 24 67658381 ps
T833 /workspace/coverage/default/25.sram_ctrl_bijection.560332217 Jan 24 06:09:07 PM PST 24 Jan 24 06:10:07 PM PST 24 5598472014 ps
T834 /workspace/coverage/default/42.sram_ctrl_smoke.2952448772 Jan 24 07:00:16 PM PST 24 Jan 24 07:00:34 PM PST 24 1143017924 ps
T835 /workspace/coverage/default/9.sram_ctrl_lc_escalation.2666293868 Jan 24 05:51:49 PM PST 24 Jan 24 05:51:51 PM PST 24 322165118 ps
T836 /workspace/coverage/default/17.sram_ctrl_executable.3041349087 Jan 24 05:58:19 PM PST 24 Jan 24 06:20:06 PM PST 24 4928346623 ps
T837 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2287470948 Jan 24 05:58:22 PM PST 24 Jan 24 07:46:06 PM PST 24 985614673 ps
T838 /workspace/coverage/default/13.sram_ctrl_multiple_keys.1193941344 Jan 24 05:55:58 PM PST 24 Jan 24 06:07:41 PM PST 24 2256858044 ps
T839 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2669228797 Jan 24 05:51:21 PM PST 24 Jan 24 05:54:00 PM PST 24 159843825 ps
T840 /workspace/coverage/default/29.sram_ctrl_executable.1233611837 Jan 24 08:02:16 PM PST 24 Jan 24 08:28:38 PM PST 24 3243427754 ps
T841 /workspace/coverage/default/48.sram_ctrl_executable.3231725476 Jan 24 06:39:14 PM PST 24 Jan 24 06:51:31 PM PST 24 1792665689 ps
T842 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1956853404 Jan 24 05:49:36 PM PST 24 Jan 24 05:56:04 PM PST 24 7860553298 ps
T843 /workspace/coverage/default/29.sram_ctrl_multiple_keys.1229688244 Jan 24 06:14:44 PM PST 24 Jan 24 06:18:42 PM PST 24 6522606266 ps
T844 /workspace/coverage/default/17.sram_ctrl_ram_cfg.3393665252 Jan 24 06:44:29 PM PST 24 Jan 24 06:44:31 PM PST 24 51346651 ps
T845 /workspace/coverage/default/17.sram_ctrl_lc_escalation.1518762452 Jan 24 05:58:20 PM PST 24 Jan 24 05:58:28 PM PST 24 752474479 ps
T846 /workspace/coverage/default/48.sram_ctrl_bijection.657681337 Jan 24 06:38:32 PM PST 24 Jan 24 06:39:18 PM PST 24 12253601168 ps
T847 /workspace/coverage/default/2.sram_ctrl_regwen.2046479123 Jan 24 05:45:24 PM PST 24 Jan 24 06:07:12 PM PST 24 7210165752 ps
T848 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3846147654 Jan 24 06:30:14 PM PST 24 Jan 24 06:34:30 PM PST 24 22750936985 ps
T849 /workspace/coverage/default/31.sram_ctrl_mem_walk.3349407463 Jan 24 07:53:40 PM PST 24 Jan 24 07:53:49 PM PST 24 137462011 ps
T850 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3558164975 Jan 24 06:34:07 PM PST 24 Jan 24 06:37:03 PM PST 24 8301051926 ps
T851 /workspace/coverage/default/45.sram_ctrl_mem_walk.1980986122 Jan 24 06:35:18 PM PST 24 Jan 24 06:35:28 PM PST 24 891573487 ps
T852 /workspace/coverage/default/36.sram_ctrl_smoke.1194121532 Jan 24 06:24:02 PM PST 24 Jan 24 06:24:12 PM PST 24 969891162 ps
T853 /workspace/coverage/default/22.sram_ctrl_partial_access.4115251528 Jan 24 08:48:57 PM PST 24 Jan 24 08:49:15 PM PST 24 658951520 ps
T854 /workspace/coverage/default/32.sram_ctrl_mem_walk.1048599383 Jan 24 06:19:46 PM PST 24 Jan 24 06:19:56 PM PST 24 1903470291 ps
T855 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4023167436 Jan 24 06:45:07 PM PST 24 Jan 24 06:49:44 PM PST 24 47870323598 ps
T856 /workspace/coverage/default/28.sram_ctrl_stress_all.3611087374 Jan 24 06:29:17 PM PST 24 Jan 24 06:57:28 PM PST 24 20991539730 ps
T857 /workspace/coverage/default/30.sram_ctrl_alert_test.3432864476 Jan 24 07:12:55 PM PST 24 Jan 24 07:12:57 PM PST 24 14875913 ps
T858 /workspace/coverage/default/2.sram_ctrl_mem_walk.3640213361 Jan 24 05:52:47 PM PST 24 Jan 24 05:53:01 PM PST 24 135492751 ps
T859 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1951174458 Jan 24 07:21:29 PM PST 24 Jan 24 07:23:59 PM PST 24 6483180629 ps
T860 /workspace/coverage/default/9.sram_ctrl_alert_test.1274156327 Jan 24 05:52:13 PM PST 24 Jan 24 05:52:14 PM PST 24 133360011 ps
T861 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2167184050 Jan 24 06:22:23 PM PST 24 Jan 24 06:22:29 PM PST 24 176920267 ps
T862 /workspace/coverage/default/38.sram_ctrl_regwen.1082529974 Jan 24 06:27:25 PM PST 24 Jan 24 06:36:17 PM PST 24 7378660687 ps
T863 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.487475785 Jan 24 05:53:25 PM PST 24 Jan 24 05:53:29 PM PST 24 130013639 ps
T864 /workspace/coverage/default/1.sram_ctrl_regwen.175772471 Jan 24 05:43:42 PM PST 24 Jan 24 05:47:28 PM PST 24 12544501937 ps
T865 /workspace/coverage/default/30.sram_ctrl_ram_cfg.2803619332 Jan 24 06:17:05 PM PST 24 Jan 24 06:17:06 PM PST 24 28764373 ps
T866 /workspace/coverage/default/12.sram_ctrl_smoke.2694086728 Jan 24 07:32:48 PM PST 24 Jan 24 07:33:19 PM PST 24 2596022018 ps
T867 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2072652049 Jan 24 06:20:14 PM PST 24 Jan 24 06:24:29 PM PST 24 10655961973 ps
T868 /workspace/coverage/default/38.sram_ctrl_stress_all.3221723693 Jan 24 06:27:51 PM PST 24 Jan 24 07:15:20 PM PST 24 508650899324 ps
T869 /workspace/coverage/default/34.sram_ctrl_alert_test.1769864872 Jan 24 06:29:56 PM PST 24 Jan 24 06:29:57 PM PST 24 33539454 ps
T870 /workspace/coverage/default/24.sram_ctrl_smoke.636749523 Jan 24 07:41:56 PM PST 24 Jan 24 07:42:09 PM PST 24 266947501 ps
T871 /workspace/coverage/default/31.sram_ctrl_alert_test.2094221369 Jan 24 06:18:55 PM PST 24 Jan 24 06:19:02 PM PST 24 32742906 ps
T872 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.579851726 Jan 24 05:54:44 PM PST 24 Jan 24 07:12:47 PM PST 24 897996117 ps
T873 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3129626532 Jan 24 05:43:48 PM PST 24 Jan 24 05:43:49 PM PST 24 35301551 ps
T874 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.4174047067 Jan 24 06:21:02 PM PST 24 Jan 24 07:01:30 PM PST 24 3260748754 ps
T875 /workspace/coverage/default/31.sram_ctrl_regwen.3568437262 Jan 24 06:18:27 PM PST 24 Jan 24 06:45:15 PM PST 24 53446995192 ps
T876 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1128107555 Jan 24 06:06:51 PM PST 24 Jan 24 06:28:50 PM PST 24 1135281336 ps
T877 /workspace/coverage/default/6.sram_ctrl_alert_test.2439493469 Jan 24 05:49:33 PM PST 24 Jan 24 05:49:34 PM PST 24 18249239 ps
T878 /workspace/coverage/default/3.sram_ctrl_mem_walk.1746917305 Jan 24 06:19:11 PM PST 24 Jan 24 06:19:19 PM PST 24 1179342828 ps
T879 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.2832916133 Jan 24 05:47:01 PM PST 24 Jan 24 06:25:39 PM PST 24 13540376829 ps
T880 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3359848435 Jan 24 06:40:59 PM PST 24 Jan 24 07:01:44 PM PST 24 13919833336 ps
T881 /workspace/coverage/default/21.sram_ctrl_lc_escalation.93293273 Jan 24 07:15:57 PM PST 24 Jan 24 07:16:05 PM PST 24 1018466967 ps
T882 /workspace/coverage/default/3.sram_ctrl_alert_test.2679701042 Jan 24 08:38:29 PM PST 24 Jan 24 08:38:30 PM PST 24 75624964 ps
T883 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.504802957 Jan 24 05:51:12 PM PST 24 Jan 24 05:56:37 PM PST 24 12219564109 ps
T884 /workspace/coverage/default/43.sram_ctrl_alert_test.1691431925 Jan 24 06:32:56 PM PST 24 Jan 24 06:32:59 PM PST 24 35441185 ps
T885 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2600937920 Jan 24 06:29:51 PM PST 24 Jan 24 07:37:39 PM PST 24 11888526271 ps
T886 /workspace/coverage/default/5.sram_ctrl_lc_escalation.205826501 Jan 24 05:48:24 PM PST 24 Jan 24 05:48:40 PM PST 24 546466358 ps
T887 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2085073280 Jan 24 06:28:48 PM PST 24 Jan 24 06:28:54 PM PST 24 119961114 ps
T888 /workspace/coverage/default/35.sram_ctrl_lc_escalation.281438264 Jan 24 06:23:15 PM PST 24 Jan 24 06:23:21 PM PST 24 1452245086 ps
T889 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4119274775 Jan 24 07:58:24 PM PST 24 Jan 24 08:00:54 PM PST 24 21104104188 ps
T890 /workspace/coverage/default/35.sram_ctrl_alert_test.3865862801 Jan 24 07:02:14 PM PST 24 Jan 24 07:02:22 PM PST 24 14287355 ps
T891 /workspace/coverage/default/16.sram_ctrl_executable.3883960911 Jan 24 06:08:45 PM PST 24 Jan 24 06:20:40 PM PST 24 5894009491 ps
T892 /workspace/coverage/default/35.sram_ctrl_mem_walk.2879675909 Jan 24 06:23:36 PM PST 24 Jan 24 06:23:48 PM PST 24 3161176521 ps
T893 /workspace/coverage/default/28.sram_ctrl_smoke.447845525 Jan 24 06:13:12 PM PST 24 Jan 24 06:13:16 PM PST 24 368251006 ps
T894 /workspace/coverage/default/23.sram_ctrl_alert_test.533411464 Jan 24 07:37:21 PM PST 24 Jan 24 07:37:23 PM PST 24 13183149 ps
T895 /workspace/coverage/default/8.sram_ctrl_partial_access.1009526516 Jan 24 05:50:20 PM PST 24 Jan 24 05:50:37 PM PST 24 1888358698 ps
T896 /workspace/coverage/default/32.sram_ctrl_partial_access.189989455 Jan 24 06:19:22 PM PST 24 Jan 24 06:20:26 PM PST 24 7320404364 ps
T897 /workspace/coverage/default/40.sram_ctrl_alert_test.3944515030 Jan 24 06:42:26 PM PST 24 Jan 24 06:42:27 PM PST 24 45632624 ps
T898 /workspace/coverage/default/9.sram_ctrl_partial_access.3262677303 Jan 24 05:51:07 PM PST 24 Jan 24 05:51:09 PM PST 24 73283232 ps
T899 /workspace/coverage/default/19.sram_ctrl_partial_access.4140256057 Jan 24 05:59:47 PM PST 24 Jan 24 05:59:54 PM PST 24 1941317592 ps
T900 /workspace/coverage/default/16.sram_ctrl_multiple_keys.35068655 Jan 24 06:23:56 PM PST 24 Jan 24 06:39:02 PM PST 24 4392180142 ps
T901 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1553514482 Jan 24 06:31:27 PM PST 24 Jan 24 06:39:53 PM PST 24 19749599634 ps
T902 /workspace/coverage/default/38.sram_ctrl_ram_cfg.2796566932 Jan 24 06:27:31 PM PST 24 Jan 24 06:27:32 PM PST 24 53951234 ps
T903 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3932159338 Jan 24 06:06:58 PM PST 24 Jan 24 06:12:00 PM PST 24 11875149409 ps
T904 /workspace/coverage/default/36.sram_ctrl_mem_walk.3286836887 Jan 24 07:03:10 PM PST 24 Jan 24 07:03:22 PM PST 24 839096213 ps
T905 /workspace/coverage/default/6.sram_ctrl_partial_access.2790601282 Jan 24 05:48:41 PM PST 24 Jan 24 05:48:48 PM PST 24 229099345 ps
T906 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1660989805 Jan 24 06:47:09 PM PST 24 Jan 24 07:33:38 PM PST 24 951474210 ps
T907 /workspace/coverage/default/25.sram_ctrl_partial_access.147973104 Jan 24 06:09:21 PM PST 24 Jan 24 06:09:24 PM PST 24 66101573 ps
T908 /workspace/coverage/default/48.sram_ctrl_smoke.3072539873 Jan 24 07:32:49 PM PST 24 Jan 24 07:33:08 PM PST 24 9393072612 ps
T909 /workspace/coverage/default/45.sram_ctrl_max_throughput.510817474 Jan 24 06:41:52 PM PST 24 Jan 24 06:41:56 PM PST 24 75105154 ps
T910 /workspace/coverage/default/5.sram_ctrl_regwen.342325201 Jan 24 05:48:25 PM PST 24 Jan 24 06:07:21 PM PST 24 2716038470 ps
T911 /workspace/coverage/default/9.sram_ctrl_regwen.2523356477 Jan 24 05:51:49 PM PST 24 Jan 24 05:52:17 PM PST 24 1639829599 ps
T912 /workspace/coverage/default/21.sram_ctrl_ram_cfg.2904668721 Jan 24 06:06:09 PM PST 24 Jan 24 06:06:13 PM PST 24 25659030 ps
T913 /workspace/coverage/default/37.sram_ctrl_max_throughput.3219471634 Jan 24 06:47:00 PM PST 24 Jan 24 06:47:12 PM PST 24 165468066 ps
T914 /workspace/coverage/default/35.sram_ctrl_executable.4229975029 Jan 24 06:45:27 PM PST 24 Jan 24 07:10:23 PM PST 24 2822599868 ps
T915 /workspace/coverage/default/21.sram_ctrl_multiple_keys.1035812114 Jan 24 06:52:35 PM PST 24 Jan 24 07:07:35 PM PST 24 26827347538 ps
T916 /workspace/coverage/default/30.sram_ctrl_partial_access.3208290888 Jan 24 06:16:29 PM PST 24 Jan 24 06:16:41 PM PST 24 402170969 ps
T917 /workspace/coverage/default/11.sram_ctrl_bijection.1562324863 Jan 24 07:25:19 PM PST 24 Jan 24 07:25:55 PM PST 24 523617266 ps
T918 /workspace/coverage/default/4.sram_ctrl_multiple_keys.765644759 Jan 24 05:46:51 PM PST 24 Jan 24 05:49:54 PM PST 24 947404800 ps
T919 /workspace/coverage/default/21.sram_ctrl_alert_test.3203572871 Jan 24 06:06:13 PM PST 24 Jan 24 06:06:15 PM PST 24 13477426 ps
T920 /workspace/coverage/default/23.sram_ctrl_max_throughput.1576046106 Jan 24 06:51:25 PM PST 24 Jan 24 06:51:29 PM PST 24 96418987 ps
T921 /workspace/coverage/default/19.sram_ctrl_stress_all.3834893116 Jan 24 06:05:40 PM PST 24 Jan 24 06:27:21 PM PST 24 37760835961 ps
T922 /workspace/coverage/default/49.sram_ctrl_multiple_keys.718198771 Jan 24 06:39:46 PM PST 24 Jan 24 06:40:44 PM PST 24 973853524 ps
T923 /workspace/coverage/default/28.sram_ctrl_multiple_keys.3187760735 Jan 24 06:13:11 PM PST 24 Jan 24 06:14:17 PM PST 24 878764386 ps
T924 /workspace/coverage/default/42.sram_ctrl_alert_test.1358577711 Jan 24 06:32:08 PM PST 24 Jan 24 06:32:09 PM PST 24 32845829 ps
T925 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1035460189 Jan 24 07:41:15 PM PST 24 Jan 24 07:49:06 PM PST 24 43502298114 ps
T926 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.959915234 Jan 24 06:26:19 PM PST 24 Jan 24 07:51:22 PM PST 24 7844306865 ps
T927 /workspace/coverage/default/12.sram_ctrl_regwen.1194161847 Jan 24 05:53:46 PM PST 24 Jan 24 06:02:59 PM PST 24 3308030015 ps
T928 /workspace/coverage/default/22.sram_ctrl_alert_test.1268528977 Jan 24 06:12:24 PM PST 24 Jan 24 06:12:25 PM PST 24 16271460 ps
T929 /workspace/coverage/default/35.sram_ctrl_max_throughput.3157182257 Jan 24 06:23:13 PM PST 24 Jan 24 06:24:48 PM PST 24 131239792 ps
T930 /workspace/coverage/default/25.sram_ctrl_stress_all.3032334950 Jan 24 09:14:09 PM PST 24 Jan 24 09:42:21 PM PST 24 54813725982 ps
T931 /workspace/coverage/default/34.sram_ctrl_multiple_keys.1105044748 Jan 24 07:59:01 PM PST 24 Jan 24 08:08:22 PM PST 24 22554617256 ps
T932 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.4268265182 Jan 24 05:57:16 PM PST 24 Jan 24 05:57:22 PM PST 24 152547903 ps
T933 /workspace/coverage/default/23.sram_ctrl_executable.904978935 Jan 24 06:07:21 PM PST 24 Jan 24 06:29:09 PM PST 24 15448720265 ps
T934 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1290038979 Jan 24 10:04:41 PM PST 24 Jan 24 10:06:14 PM PST 24 1127226479 ps
T935 /workspace/coverage/default/22.sram_ctrl_bijection.1357444299 Jan 24 06:06:20 PM PST 24 Jan 24 06:06:40 PM PST 24 374095930 ps
T936 /workspace/coverage/default/12.sram_ctrl_mem_walk.2036108827 Jan 24 06:00:14 PM PST 24 Jan 24 06:00:26 PM PST 24 2391894300 ps
T937 /workspace/coverage/default/1.sram_ctrl_max_throughput.4038169715 Jan 24 06:45:59 PM PST 24 Jan 24 06:46:51 PM PST 24 1015871416 ps
T938 /workspace/coverage/default/44.sram_ctrl_alert_test.2065499383 Jan 24 10:41:01 PM PST 24 Jan 24 10:41:07 PM PST 24 11571929 ps
T939 /workspace/coverage/default/43.sram_ctrl_partial_access.847442847 Jan 24 06:32:21 PM PST 24 Jan 24 06:32:30 PM PST 24 1970486672 ps
T940 /workspace/coverage/default/40.sram_ctrl_mem_walk.1797680470 Jan 24 06:29:42 PM PST 24 Jan 24 06:29:53 PM PST 24 4112807175 ps
T941 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.508989305 Jan 24 06:26:56 PM PST 24 Jan 24 06:32:47 PM PST 24 5413671204 ps
T942 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2500597174 Jan 24 06:28:56 PM PST 24 Jan 24 07:41:02 PM PST 24 2248352908 ps
T943 /workspace/coverage/default/49.sram_ctrl_executable.1505757255 Jan 24 06:40:24 PM PST 24 Jan 24 06:44:42 PM PST 24 9558749842 ps
T944 /workspace/coverage/default/33.sram_ctrl_alert_test.846111462 Jan 24 06:21:17 PM PST 24 Jan 24 06:21:20 PM PST 24 26360941 ps
T945 /workspace/coverage/default/43.sram_ctrl_executable.1272771582 Jan 24 06:32:43 PM PST 24 Jan 24 06:48:20 PM PST 24 8683800656 ps
T946 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.334745608 Jan 24 06:34:47 PM PST 24 Jan 24 06:38:56 PM PST 24 22459697862 ps
T947 /workspace/coverage/default/41.sram_ctrl_bijection.2140985754 Jan 24 06:30:02 PM PST 24 Jan 24 06:30:48 PM PST 24 1476725103 ps
T948 /workspace/coverage/default/24.sram_ctrl_alert_test.4228046969 Jan 24 06:51:06 PM PST 24 Jan 24 06:51:07 PM PST 24 159855755 ps
T949 /workspace/coverage/default/43.sram_ctrl_multiple_keys.1426990976 Jan 24 06:32:14 PM PST 24 Jan 24 06:53:12 PM PST 24 29355926576 ps
T950 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1719523551 Jan 24 07:18:43 PM PST 24 Jan 24 07:22:19 PM PST 24 2291597766 ps
T951 /workspace/coverage/default/23.sram_ctrl_mem_walk.204528461 Jan 24 06:07:47 PM PST 24 Jan 24 06:08:00 PM PST 24 1382826585 ps
T952 /workspace/coverage/default/12.sram_ctrl_lc_escalation.109781867 Jan 24 05:53:42 PM PST 24 Jan 24 05:53:46 PM PST 24 494983671 ps
T953 /workspace/coverage/default/36.sram_ctrl_bijection.554299053 Jan 24 06:24:21 PM PST 24 Jan 24 06:24:51 PM PST 24 23259256411 ps
T954 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1629162534 Jan 24 05:52:13 PM PST 24 Jan 24 05:52:19 PM PST 24 180629671 ps
T955 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3581615755 Jan 24 05:41:53 PM PST 24 Jan 24 05:46:36 PM PST 24 4536228658 ps
T956 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.65177691 Jan 24 05:49:24 PM PST 24 Jan 24 06:17:59 PM PST 24 4111219778 ps
T957 /workspace/coverage/default/15.sram_ctrl_alert_test.2286976449 Jan 24 06:03:55 PM PST 24 Jan 24 06:03:56 PM PST 24 16269109 ps
T958 /workspace/coverage/default/12.sram_ctrl_bijection.2394609032 Jan 24 06:31:13 PM PST 24 Jan 24 06:32:20 PM PST 24 7592178751 ps
T959 /workspace/coverage/default/30.sram_ctrl_multiple_keys.3989997963 Jan 24 06:21:24 PM PST 24 Jan 24 06:31:32 PM PST 24 10604135003 ps
T960 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1133667991 Jan 24 05:53:41 PM PST 24 Jan 24 06:14:23 PM PST 24 6064853250 ps
T961 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2553868848 Jan 24 06:37:36 PM PST 24 Jan 24 06:42:00 PM PST 24 15182760792 ps
T962 /workspace/coverage/default/43.sram_ctrl_mem_walk.53985256 Jan 24 08:20:47 PM PST 24 Jan 24 08:20:57 PM PST 24 3617525213 ps
T963 /workspace/coverage/default/13.sram_ctrl_max_throughput.1798335937 Jan 24 05:54:22 PM PST 24 Jan 24 05:55:13 PM PST 24 106575517 ps
T964 /workspace/coverage/default/24.sram_ctrl_partial_access.2556925502 Jan 24 06:08:06 PM PST 24 Jan 24 06:08:16 PM PST 24 2719840645 ps
T965 /workspace/coverage/default/20.sram_ctrl_ram_cfg.3636352253 Jan 24 06:03:21 PM PST 24 Jan 24 06:03:23 PM PST 24 31808718 ps
T966 /workspace/coverage/default/18.sram_ctrl_executable.3422580374 Jan 24 06:10:43 PM PST 24 Jan 24 06:30:48 PM PST 24 46186558998 ps
T967 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.4271880970 Jan 24 06:12:09 PM PST 24 Jan 24 06:15:57 PM PST 24 9215023324 ps
T968 /workspace/coverage/default/1.sram_ctrl_partial_access.3110522328 Jan 24 05:43:13 PM PST 24 Jan 24 05:45:19 PM PST 24 200142828 ps
T969 /workspace/coverage/default/19.sram_ctrl_bijection.310017678 Jan 24 05:59:45 PM PST 24 Jan 24 06:00:03 PM PST 24 3969307252 ps
T970 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.750990525 Jan 24 05:57:02 PM PST 24 Jan 24 06:13:31 PM PST 24 3452141884 ps
T971 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.993714817 Jan 24 06:34:37 PM PST 24 Jan 24 06:40:03 PM PST 24 3310641707 ps
T972 /workspace/coverage/default/12.sram_ctrl_max_throughput.1852189734 Jan 24 05:53:36 PM PST 24 Jan 24 05:53:56 PM PST 24 95110741 ps
T973 /workspace/coverage/default/22.sram_ctrl_smoke.3159278738 Jan 24 06:06:17 PM PST 24 Jan 24 06:07:23 PM PST 24 493359881 ps
T974 /workspace/coverage/default/26.sram_ctrl_smoke.378729261 Jan 24 06:47:40 PM PST 24 Jan 24 06:47:48 PM PST 24 195734403 ps
T975 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3541862439 Jan 24 06:43:34 PM PST 24 Jan 24 06:43:53 PM PST 24 101782677 ps
T976 /workspace/coverage/default/17.sram_ctrl_partial_access.3084108285 Jan 24 05:58:11 PM PST 24 Jan 24 05:58:24 PM PST 24 196555050 ps
T977 /workspace/coverage/default/44.sram_ctrl_ram_cfg.3661376463 Jan 24 08:07:20 PM PST 24 Jan 24 08:07:25 PM PST 24 77645090 ps
T978 /workspace/coverage/default/2.sram_ctrl_multiple_keys.2039686908 Jan 24 05:43:58 PM PST 24 Jan 24 05:52:19 PM PST 24 2472411464 ps
T979 /workspace/coverage/default/15.sram_ctrl_executable.3667144876 Jan 24 05:56:30 PM PST 24 Jan 24 06:14:22 PM PST 24 3102651115 ps
T980 /workspace/coverage/default/17.sram_ctrl_mem_walk.736965310 Jan 24 05:58:21 PM PST 24 Jan 24 05:58:33 PM PST 24 3137706599 ps
T981 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2976482273 Jan 24 07:48:14 PM PST 24 Jan 24 08:15:36 PM PST 24 4243704325 ps
T982 /workspace/coverage/default/30.sram_ctrl_regwen.3983995689 Jan 24 06:16:57 PM PST 24 Jan 24 06:42:17 PM PST 24 4734925841 ps

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1987375241
Short name T1
Test name
Test status
Simulation time 1045620075 ps
CPU time 2732.73 seconds
Started Jan 24 06:27:48 PM PST 24
Finished Jan 24 07:13:21 PM PST 24
Peak memory 429716 kb
Host smart-a0fea440-4ba3-405e-88d2-63691bb18096
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1987375241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1987375241
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.2827690931
Short name T7
Test name
Test status
Simulation time 30937834580 ps
CPU time 2020.43 seconds
Started Jan 24 05:56:43 PM PST 24
Finished Jan 24 06:30:24 PM PST 24
Peak memory 380876 kb
Host smart-c647bf7b-fbc1-458f-a384-dc9982ac98b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827690931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.2827690931
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3389115505
Short name T5
Test name
Test status
Simulation time 96460537646 ps
CPU time 465.49 seconds
Started Jan 24 06:02:18 PM PST 24
Finished Jan 24 06:10:04 PM PST 24
Peak memory 201868 kb
Host smart-296f89a8-f6e9-47f7-a637-93967ee50636
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389115505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.3389115505
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1059490705
Short name T42
Test name
Test status
Simulation time 688449972 ps
CPU time 2.38 seconds
Started Jan 24 02:28:01 PM PST 24
Finished Jan 24 02:28:22 PM PST 24
Peak memory 202720 kb
Host smart-27d38a3d-f55a-4e3f-a7d4-2822f2247ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059490705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.1059490705
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.1490655008
Short name T18
Test name
Test status
Simulation time 201586743 ps
CPU time 2.13 seconds
Started Jan 24 07:06:45 PM PST 24
Finished Jan 24 07:06:47 PM PST 24
Peak memory 220356 kb
Host smart-163de51a-95e4-447f-970a-2388485bb892
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490655008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.1490655008
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.3828089959
Short name T6
Test name
Test status
Simulation time 26523554568 ps
CPU time 1656.82 seconds
Started Jan 24 06:34:13 PM PST 24
Finished Jan 24 07:01:50 PM PST 24
Peak memory 367420 kb
Host smart-f4a08cf2-1258-455b-9664-55935fa7cddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828089959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.3828089959
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4229260543
Short name T57
Test name
Test status
Simulation time 19880541 ps
CPU time 0.68 seconds
Started Jan 24 02:29:34 PM PST 24
Finished Jan 24 02:29:48 PM PST 24
Peak memory 202212 kb
Host smart-39305bd4-0a08-456a-b3a8-afa29db28da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229260543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.4229260543
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3667701090
Short name T78
Test name
Test status
Simulation time 6660899802 ps
CPU time 679.59 seconds
Started Jan 24 07:53:58 PM PST 24
Finished Jan 24 08:05:22 PM PST 24
Peak memory 373788 kb
Host smart-5665ebbc-9c05-4946-9d53-73389be6db7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667701090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.3667701090
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.1548388074
Short name T103
Test name
Test status
Simulation time 49854674047 ps
CPU time 2303.08 seconds
Started Jan 24 07:19:19 PM PST 24
Finished Jan 24 07:57:43 PM PST 24
Peak memory 373776 kb
Host smart-8722f741-1fbe-43e8-aebe-9d598de76643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548388074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.1548388074
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.1281367908
Short name T243
Test name
Test status
Simulation time 29961010 ps
CPU time 0.88 seconds
Started Jan 24 05:53:26 PM PST 24
Finished Jan 24 05:53:27 PM PST 24
Peak memory 201804 kb
Host smart-b9d1c4b1-14c7-457c-a998-7b440ca1f9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281367908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1281367908
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2972685301
Short name T96
Test name
Test status
Simulation time 380730701 ps
CPU time 2.2 seconds
Started Jan 24 02:28:31 PM PST 24
Finished Jan 24 02:28:40 PM PST 24
Peak memory 202820 kb
Host smart-45f4e214-5150-4a86-8a95-f36b0460b0de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972685301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.2972685301
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.67413124
Short name T95
Test name
Test status
Simulation time 517803905 ps
CPU time 2.2 seconds
Started Jan 24 02:28:44 PM PST 24
Finished Jan 24 02:28:48 PM PST 24
Peak memory 202804 kb
Host smart-81d3ac27-a1f9-4fbf-8c2c-0b7996ea705f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67413124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te
st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.sram_ctrl_tl_intg_err.67413124
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.595371593
Short name T56
Test name
Test status
Simulation time 198545030 ps
CPU time 2.28 seconds
Started Jan 24 02:28:21 PM PST 24
Finished Jan 24 02:28:37 PM PST 24
Peak memory 202568 kb
Host smart-f0df7d83-3cdd-49b4-8113-63550292089e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595371593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_bit_bash.595371593
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.64723533
Short name T409
Test name
Test status
Simulation time 15943873 ps
CPU time 0.65 seconds
Started Jan 24 05:52:33 PM PST 24
Finished Jan 24 05:52:34 PM PST 24
Peak memory 200784 kb
Host smart-5b85e4ca-81aa-46ff-8a79-0893687d4e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64723533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_alert_test.64723533
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1923704267
Short name T97
Test name
Test status
Simulation time 510548666 ps
CPU time 2.84 seconds
Started Jan 24 02:29:35 PM PST 24
Finished Jan 24 02:29:51 PM PST 24
Peak memory 202776 kb
Host smart-465b2dd2-5ec2-4603-9e27-46bcaeea4727
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923704267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1923704267
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.702552769
Short name T44
Test name
Test status
Simulation time 485934113 ps
CPU time 2.11 seconds
Started Jan 24 02:54:18 PM PST 24
Finished Jan 24 02:54:44 PM PST 24
Peak memory 202872 kb
Host smart-e501ab65-e677-45c4-b799-3ec165adbdf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702552769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.sram_ctrl_tl_intg_err.702552769
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2186486017
Short name T157
Test name
Test status
Simulation time 45222298 ps
CPU time 1.85 seconds
Started Jan 24 02:27:43 PM PST 24
Finished Jan 24 02:28:13 PM PST 24
Peak memory 202728 kb
Host smart-6b5a0b28-36e8-4df0-b329-d2079ab9e097
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186486017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.2186486017
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3365438202
Short name T150
Test name
Test status
Simulation time 133641732 ps
CPU time 0.67 seconds
Started Jan 24 02:39:20 PM PST 24
Finished Jan 24 02:39:37 PM PST 24
Peak memory 202136 kb
Host smart-3c61fc58-723c-454f-929f-5c99de094775
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365438202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.3365438202
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1036611246
Short name T139
Test name
Test status
Simulation time 66609217 ps
CPU time 1.38 seconds
Started Jan 24 02:28:00 PM PST 24
Finished Jan 24 02:28:19 PM PST 24
Peak memory 202880 kb
Host smart-49987d0a-58b7-4d2f-ac76-6b3bae00775f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036611246 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1036611246
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2319997068
Short name T184
Test name
Test status
Simulation time 13893653 ps
CPU time 0.67 seconds
Started Jan 24 02:27:43 PM PST 24
Finished Jan 24 02:28:12 PM PST 24
Peak memory 202476 kb
Host smart-df7ec0ea-54ed-4aec-813b-2dfaae5430da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319997068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.2319997068
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.383314572
Short name T154
Test name
Test status
Simulation time 51585126 ps
CPU time 0.85 seconds
Started Jan 24 02:37:26 PM PST 24
Finished Jan 24 02:37:57 PM PST 24
Peak memory 202560 kb
Host smart-12ea0595-90b3-45de-a7fa-c9c7bc7a0265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383314572 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.383314572
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3316253545
Short name T169
Test name
Test status
Simulation time 498034046 ps
CPU time 4.21 seconds
Started Jan 24 02:27:43 PM PST 24
Finished Jan 24 02:28:15 PM PST 24
Peak memory 202900 kb
Host smart-7af28f91-c028-4929-b098-4941c451fa4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316253545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.3316253545
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1841565445
Short name T174
Test name
Test status
Simulation time 561662139 ps
CPU time 2.06 seconds
Started Jan 24 02:27:44 PM PST 24
Finished Jan 24 02:28:14 PM PST 24
Peak memory 202836 kb
Host smart-b6647826-f16c-4735-a079-4b5f464cc5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841565445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.1841565445
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3019699398
Short name T141
Test name
Test status
Simulation time 45333427 ps
CPU time 0.66 seconds
Started Jan 24 02:28:08 PM PST 24
Finished Jan 24 02:28:25 PM PST 24
Peak memory 201216 kb
Host smart-1daeff0d-950a-4087-a966-756c4fc9a2d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019699398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.3019699398
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1175692840
Short name T68
Test name
Test status
Simulation time 50206660 ps
CPU time 1.93 seconds
Started Jan 24 02:28:07 PM PST 24
Finished Jan 24 02:28:26 PM PST 24
Peak memory 202736 kb
Host smart-ae7ad80c-ffdf-4830-9b62-074b15e79101
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175692840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.1175692840
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.263359627
Short name T66
Test name
Test status
Simulation time 15814643 ps
CPU time 0.66 seconds
Started Jan 24 02:50:59 PM PST 24
Finished Jan 24 02:51:15 PM PST 24
Peak memory 201240 kb
Host smart-56330188-1cde-45ac-a129-f7ad96d59011
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263359627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_hw_reset.263359627
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1972994539
Short name T135
Test name
Test status
Simulation time 75600005 ps
CPU time 0.91 seconds
Started Jan 24 02:28:08 PM PST 24
Finished Jan 24 02:28:26 PM PST 24
Peak memory 202524 kb
Host smart-a037863f-8ad6-488f-b23d-d58dea11f7ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972994539 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1972994539
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4123281052
Short name T65
Test name
Test status
Simulation time 17330008 ps
CPU time 0.71 seconds
Started Jan 24 02:28:07 PM PST 24
Finished Jan 24 02:28:25 PM PST 24
Peak memory 202404 kb
Host smart-0148c90b-2971-4beb-b0b7-31774ec36073
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123281052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.4123281052
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1488070995
Short name T186
Test name
Test status
Simulation time 20908696 ps
CPU time 0.7 seconds
Started Jan 24 02:28:06 PM PST 24
Finished Jan 24 02:28:23 PM PST 24
Peak memory 202524 kb
Host smart-95c9a893-c32c-46a9-869b-b8159412f4bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488070995 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1488070995
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2781339463
Short name T152
Test name
Test status
Simulation time 221187770 ps
CPU time 4.47 seconds
Started Jan 24 02:28:03 PM PST 24
Finished Jan 24 02:28:24 PM PST 24
Peak memory 202784 kb
Host smart-8c40db5e-37e3-48d5-99fe-fca5cab1bd8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781339463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.2781339463
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1163304583
Short name T168
Test name
Test status
Simulation time 35631681 ps
CPU time 1.12 seconds
Started Jan 24 02:29:21 PM PST 24
Finished Jan 24 02:29:38 PM PST 24
Peak memory 202636 kb
Host smart-6a003b19-bbd0-4c07-925d-868e8dd0b3d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163304583 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1163304583
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.114066282
Short name T192
Test name
Test status
Simulation time 15589641 ps
CPU time 0.74 seconds
Started Jan 24 02:29:12 PM PST 24
Finished Jan 24 02:29:32 PM PST 24
Peak memory 202504 kb
Host smart-76f1bb9a-6488-4346-852f-c2abf6085aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114066282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 10.sram_ctrl_csr_rw.114066282
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3218370866
Short name T87
Test name
Test status
Simulation time 38857561 ps
CPU time 0.7 seconds
Started Jan 24 02:29:12 PM PST 24
Finished Jan 24 02:29:33 PM PST 24
Peak memory 202416 kb
Host smart-e1120709-50a5-4899-944a-4db269635c36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218370866 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3218370866
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2932527996
Short name T51
Test name
Test status
Simulation time 80401712 ps
CPU time 2.52 seconds
Started Jan 24 02:29:10 PM PST 24
Finished Jan 24 02:29:32 PM PST 24
Peak memory 202896 kb
Host smart-3cfbbfe0-af43-477c-a46f-987e7b21f2a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932527996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.2932527996
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.987088238
Short name T99
Test name
Test status
Simulation time 259054131 ps
CPU time 1.6 seconds
Started Jan 24 02:29:06 PM PST 24
Finished Jan 24 02:29:27 PM PST 24
Peak memory 202660 kb
Host smart-863d427b-c4f1-4daf-9460-2ef03057d2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987088238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.sram_ctrl_tl_intg_err.987088238
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1815512036
Short name T53
Test name
Test status
Simulation time 96443968 ps
CPU time 1.73 seconds
Started Jan 24 02:29:24 PM PST 24
Finished Jan 24 02:29:39 PM PST 24
Peak memory 202960 kb
Host smart-7311fa22-d539-4b99-931d-4e3d5bb5bfe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815512036 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1815512036
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2082314772
Short name T172
Test name
Test status
Simulation time 13150283 ps
CPU time 0.66 seconds
Started Jan 24 02:29:22 PM PST 24
Finished Jan 24 02:29:38 PM PST 24
Peak memory 202456 kb
Host smart-d4aff291-cc78-49f2-998b-0db54ab4a40b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082314772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.2082314772
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1233431987
Short name T170
Test name
Test status
Simulation time 35745391 ps
CPU time 0.8 seconds
Started Jan 24 02:29:26 PM PST 24
Finished Jan 24 02:29:39 PM PST 24
Peak memory 202344 kb
Host smart-1b0ca8d9-6f22-483f-a4df-d0bfd13a2019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233431987 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1233431987
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.551345883
Short name T143
Test name
Test status
Simulation time 521091539 ps
CPU time 4.37 seconds
Started Jan 24 02:29:27 PM PST 24
Finished Jan 24 02:29:43 PM PST 24
Peak memory 202880 kb
Host smart-95b7ef39-6cce-43c1-bafb-eec4e61f9cde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551345883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.551345883
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1841620858
Short name T70
Test name
Test status
Simulation time 473845771 ps
CPU time 2.05 seconds
Started Jan 24 02:29:22 PM PST 24
Finished Jan 24 02:29:39 PM PST 24
Peak memory 202856 kb
Host smart-f58c2587-179c-4b25-b357-a531b07a8043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841620858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.1841620858
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1405730511
Short name T49
Test name
Test status
Simulation time 38173063 ps
CPU time 1.3 seconds
Started Jan 24 02:29:22 PM PST 24
Finished Jan 24 02:29:38 PM PST 24
Peak memory 202840 kb
Host smart-c3127fe8-7be9-4cc6-962b-37191b541f20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405730511 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1405730511
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3704562853
Short name T188
Test name
Test status
Simulation time 21812337 ps
CPU time 0.72 seconds
Started Jan 24 02:29:23 PM PST 24
Finished Jan 24 02:29:38 PM PST 24
Peak memory 202460 kb
Host smart-ba77b4e2-267b-47f7-a332-41dd266f8083
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704562853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.3704562853
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2689521398
Short name T163
Test name
Test status
Simulation time 58057481 ps
CPU time 0.69 seconds
Started Jan 24 02:29:21 PM PST 24
Finished Jan 24 02:29:37 PM PST 24
Peak memory 202560 kb
Host smart-7b6dfecc-d43c-4ed8-8d28-030046162e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689521398 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2689521398
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.815672162
Short name T160
Test name
Test status
Simulation time 55941333 ps
CPU time 2.1 seconds
Started Jan 24 02:29:27 PM PST 24
Finished Jan 24 02:29:41 PM PST 24
Peak memory 202888 kb
Host smart-2afc3306-c753-4954-b09b-2bbc89ef5d76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815672162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_tl_errors.815672162
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.497538323
Short name T178
Test name
Test status
Simulation time 4213474400 ps
CPU time 3.95 seconds
Started Jan 24 02:29:25 PM PST 24
Finished Jan 24 02:29:42 PM PST 24
Peak memory 202856 kb
Host smart-ff647a23-73ed-4424-b77e-a64d6e0828c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497538323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.sram_ctrl_tl_intg_err.497538323
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2105149580
Short name T165
Test name
Test status
Simulation time 275262715 ps
CPU time 2.13 seconds
Started Jan 24 02:29:20 PM PST 24
Finished Jan 24 02:29:38 PM PST 24
Peak memory 211028 kb
Host smart-2ba280c3-7572-4a65-8981-4ae976e7cd61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105149580 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2105149580
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1325736688
Short name T58
Test name
Test status
Simulation time 15817443 ps
CPU time 0.67 seconds
Started Jan 24 02:29:26 PM PST 24
Finished Jan 24 02:29:39 PM PST 24
Peak memory 202456 kb
Host smart-460fc313-9d33-44ff-9f03-d963231021b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325736688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.1325736688
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2511967919
Short name T200
Test name
Test status
Simulation time 107103653 ps
CPU time 0.82 seconds
Started Jan 24 02:29:25 PM PST 24
Finished Jan 24 02:29:39 PM PST 24
Peak memory 202472 kb
Host smart-2eba5109-f255-4077-ae65-4ee8d80c9bf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511967919 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2511967919
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1330632441
Short name T69
Test name
Test status
Simulation time 227499431 ps
CPU time 4.11 seconds
Started Jan 24 02:29:26 PM PST 24
Finished Jan 24 02:29:42 PM PST 24
Peak memory 202676 kb
Host smart-05cf802d-c061-4791-ad8c-213a6ebecf05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330632441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.1330632441
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1718792509
Short name T148
Test name
Test status
Simulation time 1338857201 ps
CPU time 2.83 seconds
Started Jan 24 02:29:29 PM PST 24
Finished Jan 24 02:29:44 PM PST 24
Peak memory 202760 kb
Host smart-8335660a-395a-4ee8-8416-40303f689f92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718792509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.1718792509
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1243048826
Short name T159
Test name
Test status
Simulation time 73564139 ps
CPU time 1.64 seconds
Started Jan 24 02:29:32 PM PST 24
Finished Jan 24 02:29:46 PM PST 24
Peak memory 202800 kb
Host smart-9e920ef7-5a43-4397-904c-3bdac7cee27e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243048826 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1243048826
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1482637841
Short name T204
Test name
Test status
Simulation time 66371235 ps
CPU time 0.66 seconds
Started Jan 24 03:37:51 PM PST 24
Finished Jan 24 03:37:53 PM PST 24
Peak memory 202448 kb
Host smart-37ccd2c8-4c3b-41fa-bfcf-a18a4d04bae5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482637841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.1482637841
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1671437079
Short name T60
Test name
Test status
Simulation time 70584856 ps
CPU time 0.75 seconds
Started Jan 24 02:29:34 PM PST 24
Finished Jan 24 02:29:47 PM PST 24
Peak memory 202576 kb
Host smart-39ae37e6-3a9b-492c-b52c-32a0c2401758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671437079 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1671437079
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2933167151
Short name T201
Test name
Test status
Simulation time 351242831 ps
CPU time 2.16 seconds
Started Jan 24 02:29:29 PM PST 24
Finished Jan 24 02:29:43 PM PST 24
Peak memory 202852 kb
Host smart-fba4ece4-a309-4eb8-8f0f-5acc87c1385c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933167151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.2933167151
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.309611295
Short name T101
Test name
Test status
Simulation time 503301271 ps
CPU time 1.55 seconds
Started Jan 24 02:29:35 PM PST 24
Finished Jan 24 02:29:50 PM PST 24
Peak memory 202880 kb
Host smart-47a71e1d-a777-407b-80e9-14f6e795e253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309611295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.sram_ctrl_tl_intg_err.309611295
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3567585814
Short name T47
Test name
Test status
Simulation time 55089434 ps
CPU time 1.2 seconds
Started Jan 24 02:29:36 PM PST 24
Finished Jan 24 02:29:50 PM PST 24
Peak memory 202612 kb
Host smart-c6ce65ac-a7a6-4d21-8303-c800c71748f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567585814 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3567585814
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3309360300
Short name T177
Test name
Test status
Simulation time 130076477 ps
CPU time 0.69 seconds
Started Jan 24 02:29:32 PM PST 24
Finished Jan 24 02:29:45 PM PST 24
Peak memory 202540 kb
Host smart-78c5451d-0d73-4359-bb1f-8310c3fd56ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309360300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3309360300
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1931493045
Short name T205
Test name
Test status
Simulation time 67392983 ps
CPU time 0.74 seconds
Started Jan 24 02:49:48 PM PST 24
Finished Jan 24 02:50:10 PM PST 24
Peak memory 202612 kb
Host smart-17ee2aff-c444-4ea9-94cb-7767056e5440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931493045 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1931493045
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4075300169
Short name T166
Test name
Test status
Simulation time 35076812 ps
CPU time 2.37 seconds
Started Jan 24 02:29:35 PM PST 24
Finished Jan 24 02:29:51 PM PST 24
Peak memory 202924 kb
Host smart-d5290e70-5a53-4863-a589-3d716f790109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075300169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.4075300169
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3735498569
Short name T146
Test name
Test status
Simulation time 1234139403 ps
CPU time 2.29 seconds
Started Jan 24 02:29:32 PM PST 24
Finished Jan 24 02:29:47 PM PST 24
Peak memory 202764 kb
Host smart-973b631c-5042-4fa9-8a1e-05c5aa2652ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735498569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.3735498569
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3937077198
Short name T82
Test name
Test status
Simulation time 64817875 ps
CPU time 1.29 seconds
Started Jan 24 02:49:25 PM PST 24
Finished Jan 24 02:49:39 PM PST 24
Peak memory 211100 kb
Host smart-b7c7402d-5faf-4692-bdfe-9ef58517b7af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937077198 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3937077198
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1503456278
Short name T176
Test name
Test status
Simulation time 39533125 ps
CPU time 0.66 seconds
Started Jan 24 02:29:32 PM PST 24
Finished Jan 24 02:29:44 PM PST 24
Peak memory 202480 kb
Host smart-acacb943-a396-421a-a1a1-b8691a07ea30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503456278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.1503456278
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.248149650
Short name T199
Test name
Test status
Simulation time 62575723 ps
CPU time 0.68 seconds
Started Jan 24 02:29:34 PM PST 24
Finished Jan 24 02:29:48 PM PST 24
Peak memory 202596 kb
Host smart-af1fb73c-d0b9-46de-9dcc-41a2cbad056d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248149650 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.248149650
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.600681425
Short name T187
Test name
Test status
Simulation time 181696532 ps
CPU time 1.91 seconds
Started Jan 24 02:29:31 PM PST 24
Finished Jan 24 02:29:44 PM PST 24
Peak memory 202852 kb
Host smart-a3fa12d5-372e-4c50-b122-22e8804c1fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600681425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.600681425
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1673858224
Short name T194
Test name
Test status
Simulation time 41547584 ps
CPU time 1.36 seconds
Started Jan 24 02:29:49 PM PST 24
Finished Jan 24 02:30:04 PM PST 24
Peak memory 202720 kb
Host smart-e2afe37d-e2d3-4815-a721-9f94900bbed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673858224 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1673858224
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1751790123
Short name T92
Test name
Test status
Simulation time 242472768 ps
CPU time 0.76 seconds
Started Jan 24 02:29:42 PM PST 24
Finished Jan 24 02:29:57 PM PST 24
Peak memory 202544 kb
Host smart-83e0c489-d3d3-466d-b16f-d796a13e61fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751790123 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1751790123
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.195368587
Short name T191
Test name
Test status
Simulation time 46005739 ps
CPU time 1.95 seconds
Started Jan 24 02:29:36 PM PST 24
Finished Jan 24 02:29:51 PM PST 24
Peak memory 202900 kb
Host smart-f0148963-1029-45d2-b080-9a37a10dbcd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195368587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_tl_errors.195368587
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3820558114
Short name T183
Test name
Test status
Simulation time 80886996 ps
CPU time 1.39 seconds
Started Jan 24 02:29:43 PM PST 24
Finished Jan 24 02:29:58 PM PST 24
Peak memory 211064 kb
Host smart-9537e547-5a71-479f-932a-0c62d8e33100
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820558114 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3820558114
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1850476067
Short name T195
Test name
Test status
Simulation time 14059547 ps
CPU time 0.67 seconds
Started Jan 24 02:29:44 PM PST 24
Finished Jan 24 02:29:58 PM PST 24
Peak memory 201212 kb
Host smart-4a5233e6-5b88-48d8-81cb-5e25dd2ed03a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850476067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.1850476067
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3203655362
Short name T185
Test name
Test status
Simulation time 22027515 ps
CPU time 0.74 seconds
Started Jan 24 02:29:48 PM PST 24
Finished Jan 24 02:30:00 PM PST 24
Peak memory 202516 kb
Host smart-36781c1d-0987-4831-bcff-3b4a0bef2742
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203655362 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3203655362
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1151402475
Short name T162
Test name
Test status
Simulation time 156225775 ps
CPU time 3.53 seconds
Started Jan 24 02:29:51 PM PST 24
Finished Jan 24 02:30:08 PM PST 24
Peak memory 202840 kb
Host smart-44eaa659-8a83-4fce-91b6-07662aae98b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151402475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.1151402475
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.32192992
Short name T193
Test name
Test status
Simulation time 271158572 ps
CPU time 2 seconds
Started Jan 24 02:29:49 PM PST 24
Finished Jan 24 02:30:04 PM PST 24
Peak memory 202668 kb
Host smart-4018c96a-1da0-46e9-9fde-4cce048d2b94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32192992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te
st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.sram_ctrl_tl_intg_err.32192992
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2083136848
Short name T164
Test name
Test status
Simulation time 36649174 ps
CPU time 2.48 seconds
Started Jan 24 04:01:57 PM PST 24
Finished Jan 24 04:02:01 PM PST 24
Peak memory 211160 kb
Host smart-09291ef6-74dd-496a-b0f3-69f6827e0334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083136848 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.2083136848
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1136109559
Short name T77
Test name
Test status
Simulation time 14317169 ps
CPU time 0.64 seconds
Started Jan 24 02:52:14 PM PST 24
Finished Jan 24 02:52:20 PM PST 24
Peak memory 202140 kb
Host smart-d4621d8e-5090-4c9d-a91c-dc6bfdf17dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136109559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.1136109559
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.146037485
Short name T202
Test name
Test status
Simulation time 24624240 ps
CPU time 0.67 seconds
Started Jan 24 02:29:50 PM PST 24
Finished Jan 24 02:30:04 PM PST 24
Peak memory 201592 kb
Host smart-a03385b5-d133-49eb-b57a-a17b419c23fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146037485 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.146037485
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.940806676
Short name T83
Test name
Test status
Simulation time 146893712 ps
CPU time 4.91 seconds
Started Jan 24 02:29:49 PM PST 24
Finished Jan 24 02:30:06 PM PST 24
Peak memory 202740 kb
Host smart-33bef591-56c0-462d-a37d-0aa87eff2f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940806676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_tl_errors.940806676
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2169972770
Short name T145
Test name
Test status
Simulation time 1861153952 ps
CPU time 2.78 seconds
Started Jan 24 02:29:49 PM PST 24
Finished Jan 24 02:30:03 PM PST 24
Peak memory 202728 kb
Host smart-7b96a275-5443-4c32-ab80-bae371dc9764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169972770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.2169972770
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1154237684
Short name T171
Test name
Test status
Simulation time 17030779 ps
CPU time 0.68 seconds
Started Jan 24 02:28:15 PM PST 24
Finished Jan 24 02:28:33 PM PST 24
Peak memory 202308 kb
Host smart-25987f0a-0d94-4335-acde-19dd04bda2e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154237684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.1154237684
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.69893145
Short name T156
Test name
Test status
Simulation time 19094307 ps
CPU time 0.65 seconds
Started Jan 24 02:52:08 PM PST 24
Finished Jan 24 02:52:12 PM PST 24
Peak memory 201328 kb
Host smart-6f6a3cc2-9da2-447f-9adf-716ac257cc42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69893145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_hw_reset.69893145
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3266517741
Short name T155
Test name
Test status
Simulation time 160833997 ps
CPU time 1.56 seconds
Started Jan 24 02:28:20 PM PST 24
Finished Jan 24 02:28:37 PM PST 24
Peak memory 202788 kb
Host smart-df0e96a4-a1c0-4104-8b49-394b3e8d8e76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266517741 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3266517741
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.758105262
Short name T61
Test name
Test status
Simulation time 13843162 ps
CPU time 0.66 seconds
Started Jan 24 02:28:21 PM PST 24
Finished Jan 24 02:28:36 PM PST 24
Peak memory 201408 kb
Host smart-a51f40db-b1f2-4d76-830a-139bde378823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758105262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.sram_ctrl_csr_rw.758105262
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.714628500
Short name T196
Test name
Test status
Simulation time 176477588 ps
CPU time 0.8 seconds
Started Jan 24 02:28:17 PM PST 24
Finished Jan 24 02:28:34 PM PST 24
Peak memory 202220 kb
Host smart-db3a0e6e-045f-4749-8467-a7ee631bc6d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714628500 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.714628500
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2665656951
Short name T144
Test name
Test status
Simulation time 104376869 ps
CPU time 2.58 seconds
Started Jan 24 02:28:06 PM PST 24
Finished Jan 24 02:28:25 PM PST 24
Peak memory 202892 kb
Host smart-2b198ae8-14cf-41c7-9e35-3277a43b7e84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665656951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.2665656951
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1165780479
Short name T98
Test name
Test status
Simulation time 565083155 ps
CPU time 1.63 seconds
Started Jan 24 02:28:08 PM PST 24
Finished Jan 24 02:28:26 PM PST 24
Peak memory 202728 kb
Host smart-9f7116c8-45f1-4413-aaa6-21b7121838d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165780479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.1165780479
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1374176650
Short name T76
Test name
Test status
Simulation time 20431410 ps
CPU time 0.73 seconds
Started Jan 24 02:28:30 PM PST 24
Finished Jan 24 02:28:38 PM PST 24
Peak memory 202480 kb
Host smart-2abed425-1301-4870-89f8-ddb2e1341639
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374176650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.1374176650
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1205437879
Short name T136
Test name
Test status
Simulation time 1012158659 ps
CPU time 1.45 seconds
Started Jan 24 02:28:30 PM PST 24
Finished Jan 24 02:28:39 PM PST 24
Peak memory 202724 kb
Host smart-e22a3771-0335-4107-8342-96f52eb6ca13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205437879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1205437879
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2038647621
Short name T54
Test name
Test status
Simulation time 43083303 ps
CPU time 0.69 seconds
Started Jan 24 02:28:29 PM PST 24
Finished Jan 24 02:28:37 PM PST 24
Peak memory 201504 kb
Host smart-5ed36958-7da7-4f15-9421-7f29dfc070ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038647621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.2038647621
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3666856047
Short name T173
Test name
Test status
Simulation time 54502522 ps
CPU time 0.91 seconds
Started Jan 24 02:28:28 PM PST 24
Finished Jan 24 02:28:37 PM PST 24
Peak memory 202624 kb
Host smart-889fae7c-6d08-49f8-80b1-f2ade4b13efc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666856047 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3666856047
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2731434997
Short name T198
Test name
Test status
Simulation time 16238996 ps
CPU time 0.71 seconds
Started Jan 24 02:28:29 PM PST 24
Finished Jan 24 02:28:38 PM PST 24
Peak memory 202404 kb
Host smart-a381768d-b2fa-4985-ada6-aca0ba3d8e27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731434997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.2731434997
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.853329823
Short name T147
Test name
Test status
Simulation time 52687578 ps
CPU time 0.76 seconds
Started Jan 24 02:28:28 PM PST 24
Finished Jan 24 02:28:37 PM PST 24
Peak memory 202560 kb
Host smart-17c2323f-2f70-494d-9564-e6b5d11f97f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853329823 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.853329823
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1491185164
Short name T50
Test name
Test status
Simulation time 312738564 ps
CPU time 3 seconds
Started Jan 24 02:28:27 PM PST 24
Finished Jan 24 02:28:39 PM PST 24
Peak memory 202884 kb
Host smart-68ab42fa-be8c-4504-9c93-56ce7bfa4d3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491185164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.1491185164
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.116629561
Short name T67
Test name
Test status
Simulation time 39711878 ps
CPU time 0.73 seconds
Started Jan 24 02:28:41 PM PST 24
Finished Jan 24 02:28:44 PM PST 24
Peak memory 202456 kb
Host smart-d773bdd8-4846-4b54-aaab-177baa78fef6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116629561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_aliasing.116629561
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3115987111
Short name T142
Test name
Test status
Simulation time 43826060 ps
CPU time 1.83 seconds
Started Jan 24 02:28:42 PM PST 24
Finished Jan 24 02:28:47 PM PST 24
Peak memory 202764 kb
Host smart-31673d40-6eec-419e-84cd-1fd2f11a7c72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115987111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3115987111
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3375101081
Short name T190
Test name
Test status
Simulation time 25462719 ps
CPU time 0.68 seconds
Started Jan 24 02:28:47 PM PST 24
Finished Jan 24 02:28:55 PM PST 24
Peak memory 202064 kb
Host smart-0baca2df-c069-46cf-aec9-33e48257ce0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375101081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.3375101081
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1910735482
Short name T140
Test name
Test status
Simulation time 39493298 ps
CPU time 1.34 seconds
Started Jan 24 02:28:45 PM PST 24
Finished Jan 24 02:28:49 PM PST 24
Peak memory 202896 kb
Host smart-c6bab923-0a5e-4eb5-bb07-4e7029ebeedd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910735482 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1910735482
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3410341181
Short name T179
Test name
Test status
Simulation time 15630885 ps
CPU time 0.72 seconds
Started Jan 24 02:28:44 PM PST 24
Finished Jan 24 02:28:47 PM PST 24
Peak memory 202496 kb
Host smart-4f527c91-47c7-446a-a401-fd250c889e36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410341181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3410341181
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3039251136
Short name T59
Test name
Test status
Simulation time 46427843 ps
CPU time 0.82 seconds
Started Jan 24 02:28:46 PM PST 24
Finished Jan 24 02:28:53 PM PST 24
Peak memory 202520 kb
Host smart-90bbc0a1-e389-418f-a00e-acb59bb85530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039251136 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3039251136
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4059300523
Short name T180
Test name
Test status
Simulation time 436734856 ps
CPU time 3.91 seconds
Started Jan 24 02:28:31 PM PST 24
Finished Jan 24 02:28:41 PM PST 24
Peak memory 202932 kb
Host smart-28258f9b-1d37-4b5f-99d6-5537a9de1138
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059300523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.4059300523
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1664238310
Short name T81
Test name
Test status
Simulation time 104785927 ps
CPU time 1.58 seconds
Started Jan 24 02:28:28 PM PST 24
Finished Jan 24 02:28:38 PM PST 24
Peak memory 202764 kb
Host smart-0af687b4-3283-4fdf-913c-d14979a38c18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664238310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.1664238310
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1046805507
Short name T137
Test name
Test status
Simulation time 33300371 ps
CPU time 2.54 seconds
Started Jan 24 02:28:42 PM PST 24
Finished Jan 24 02:28:47 PM PST 24
Peak memory 211072 kb
Host smart-dc29830e-38f0-4ab1-8ad2-c57433c02104
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046805507 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1046805507
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3210995347
Short name T55
Test name
Test status
Simulation time 46848721 ps
CPU time 0.65 seconds
Started Jan 24 02:28:40 PM PST 24
Finished Jan 24 02:28:44 PM PST 24
Peak memory 201272 kb
Host smart-85cd2ff0-464c-4ac7-a431-b2243b1fa2b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210995347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.3210995347
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3398272933
Short name T203
Test name
Test status
Simulation time 86050761 ps
CPU time 0.76 seconds
Started Jan 24 02:28:45 PM PST 24
Finished Jan 24 02:28:48 PM PST 24
Peak memory 202616 kb
Host smart-6aede574-7c03-4420-b730-267265bac42b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398272933 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3398272933
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1693374456
Short name T153
Test name
Test status
Simulation time 92237440 ps
CPU time 1.79 seconds
Started Jan 24 02:28:44 PM PST 24
Finished Jan 24 02:28:48 PM PST 24
Peak memory 202816 kb
Host smart-a3359fa0-be4f-4b99-9795-db316354792d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693374456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.1693374456
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3229450237
Short name T197
Test name
Test status
Simulation time 46581248 ps
CPU time 1.03 seconds
Started Jan 24 02:28:52 PM PST 24
Finished Jan 24 02:29:05 PM PST 24
Peak memory 202644 kb
Host smart-05c1834c-aa41-4864-aeeb-47691d1c308a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229450237 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3229450237
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.361167312
Short name T175
Test name
Test status
Simulation time 22242122 ps
CPU time 0.69 seconds
Started Jan 24 02:28:39 PM PST 24
Finished Jan 24 02:28:43 PM PST 24
Peak memory 202468 kb
Host smart-2e76f460-0061-4aa5-ba4f-8c83654bcc08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361167312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_csr_rw.361167312
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3947187848
Short name T91
Test name
Test status
Simulation time 38285250 ps
CPU time 0.68 seconds
Started Jan 24 02:28:41 PM PST 24
Finished Jan 24 02:28:44 PM PST 24
Peak memory 202548 kb
Host smart-27bd72ce-d5d2-4c37-968d-828134b57d1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947187848 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3947187848
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.797495934
Short name T151
Test name
Test status
Simulation time 70551138 ps
CPU time 2.35 seconds
Started Jan 24 02:28:41 PM PST 24
Finished Jan 24 02:28:46 PM PST 24
Peak memory 202812 kb
Host smart-0669cd96-74ba-4593-b4a7-3981f1d483db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797495934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_tl_errors.797495934
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.127913048
Short name T100
Test name
Test status
Simulation time 461475613 ps
CPU time 2.13 seconds
Started Jan 24 02:28:40 PM PST 24
Finished Jan 24 02:28:45 PM PST 24
Peak memory 202852 kb
Host smart-4eca8b4f-44b0-42f6-8d93-77e95786cad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127913048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.sram_ctrl_tl_intg_err.127913048
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2810667697
Short name T182
Test name
Test status
Simulation time 198026609 ps
CPU time 1.45 seconds
Started Jan 24 02:28:49 PM PST 24
Finished Jan 24 02:28:57 PM PST 24
Peak memory 202836 kb
Host smart-0f18eb63-bf05-47ce-b32c-08a0ee57cb32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810667697 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2810667697
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1112792730
Short name T206
Test name
Test status
Simulation time 44165294 ps
CPU time 0.67 seconds
Started Jan 24 02:28:47 PM PST 24
Finished Jan 24 02:28:54 PM PST 24
Peak memory 202492 kb
Host smart-5c87920e-3ed6-4934-9ec6-c9fb83c686e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112792730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.1112792730
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2927628472
Short name T181
Test name
Test status
Simulation time 43241088 ps
CPU time 0.72 seconds
Started Jan 24 02:28:50 PM PST 24
Finished Jan 24 02:29:01 PM PST 24
Peak memory 202580 kb
Host smart-5209f2f7-a325-4b8c-aa81-aa21d47a8543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927628472 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.2927628472
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.51592147
Short name T167
Test name
Test status
Simulation time 87297370 ps
CPU time 2.69 seconds
Started Jan 24 02:28:49 PM PST 24
Finished Jan 24 02:28:59 PM PST 24
Peak memory 202812 kb
Host smart-c4fed880-4f8e-4fb8-a431-1e659376dc3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51592147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_tl_errors.51592147
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1045780205
Short name T43
Test name
Test status
Simulation time 726164689 ps
CPU time 2.27 seconds
Started Jan 24 02:28:50 PM PST 24
Finished Jan 24 02:29:02 PM PST 24
Peak memory 202764 kb
Host smart-d19f3398-23a9-489c-a18f-82b467c9a427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045780205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.1045780205
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.646132160
Short name T48
Test name
Test status
Simulation time 95931527 ps
CPU time 1.3 seconds
Started Jan 24 02:29:00 PM PST 24
Finished Jan 24 02:29:17 PM PST 24
Peak memory 202960 kb
Host smart-b5f77b02-d398-4567-86aa-081cd42407f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646132160 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.646132160
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2537061783
Short name T93
Test name
Test status
Simulation time 13486064 ps
CPU time 0.71 seconds
Started Jan 24 02:28:59 PM PST 24
Finished Jan 24 02:29:15 PM PST 24
Peak memory 201316 kb
Host smart-2dc41083-9e8c-49f3-b052-17f2ea9f45ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537061783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.2537061783
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.94826355
Short name T86
Test name
Test status
Simulation time 45608626 ps
CPU time 0.73 seconds
Started Jan 24 02:29:02 PM PST 24
Finished Jan 24 02:29:19 PM PST 24
Peak memory 202512 kb
Host smart-dfd7d0d5-2d3b-4262-956d-a020e5d08a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94826355 -assert nopostproc +UVM_TESTNAME=sram_ctr
l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.94826355
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2004964825
Short name T138
Test name
Test status
Simulation time 68290389 ps
CPU time 4.5 seconds
Started Jan 24 02:28:50 PM PST 24
Finished Jan 24 02:29:04 PM PST 24
Peak memory 202832 kb
Host smart-6c9012e1-e621-4171-96cc-11b9933938df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004964825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.2004964825
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2512360677
Short name T149
Test name
Test status
Simulation time 67877655 ps
CPU time 1.41 seconds
Started Jan 24 02:28:50 PM PST 24
Finished Jan 24 02:29:00 PM PST 24
Peak memory 202824 kb
Host smart-0d6d42bf-16a4-4ebc-aa69-88575b5636ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512360677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.2512360677
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1393103375
Short name T158
Test name
Test status
Simulation time 71106580 ps
CPU time 0.87 seconds
Started Jan 24 02:29:15 PM PST 24
Finished Jan 24 02:29:35 PM PST 24
Peak memory 202636 kb
Host smart-0a0e4d6b-ae14-4cd6-a4b7-5ba2aa8355ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393103375 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1393103375
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.58634238
Short name T88
Test name
Test status
Simulation time 44478863 ps
CPU time 0.67 seconds
Started Jan 24 02:29:09 PM PST 24
Finished Jan 24 02:29:30 PM PST 24
Peak memory 202504 kb
Host smart-2fcc3731-42d6-4d9f-aeec-7e28481b8121
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58634238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.sram_ctrl_csr_rw.58634238
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.305971193
Short name T94
Test name
Test status
Simulation time 139170723 ps
CPU time 0.66 seconds
Started Jan 24 02:29:11 PM PST 24
Finished Jan 24 02:29:32 PM PST 24
Peak memory 201528 kb
Host smart-9b499814-cb26-4bc2-88e7-e1e8a4da04df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305971193 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.305971193
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2038103641
Short name T189
Test name
Test status
Simulation time 61445603 ps
CPU time 2.41 seconds
Started Jan 24 02:29:02 PM PST 24
Finished Jan 24 02:29:20 PM PST 24
Peak memory 202820 kb
Host smart-6f0ea9ca-1760-4e60-8546-3a6f53226486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038103641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.2038103641
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1840762374
Short name T161
Test name
Test status
Simulation time 481241778 ps
CPU time 1.55 seconds
Started Jan 24 02:29:02 PM PST 24
Finished Jan 24 02:29:20 PM PST 24
Peak memory 202836 kb
Host smart-045b38a9-16e2-4986-91c6-d858653b1dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840762374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.1840762374
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1389722394
Short name T751
Test name
Test status
Simulation time 1658320279 ps
CPU time 255.81 seconds
Started Jan 24 06:58:33 PM PST 24
Finished Jan 24 07:03:07 PM PST 24
Peak memory 365132 kb
Host smart-b9280562-b431-48c5-9cd5-23258e26f3a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389722394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1389722394
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.2557284670
Short name T646
Test name
Test status
Simulation time 15515209 ps
CPU time 0.7 seconds
Started Jan 24 06:01:51 PM PST 24
Finished Jan 24 06:01:53 PM PST 24
Peak memory 201708 kb
Host smart-dcd7d995-3d45-4be1-9e0d-85580fc28b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557284670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.2557284670
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1739570656
Short name T610
Test name
Test status
Simulation time 1101992955 ps
CPU time 70.66 seconds
Started Jan 24 05:41:50 PM PST 24
Finished Jan 24 05:43:01 PM PST 24
Peak memory 201864 kb
Host smart-818515b8-32a1-443e-b5f9-7009fd5480aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739570656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1739570656
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.2110825073
Short name T369
Test name
Test status
Simulation time 991380246 ps
CPU time 33.87 seconds
Started Jan 24 05:42:26 PM PST 24
Finished Jan 24 05:43:00 PM PST 24
Peak memory 263368 kb
Host smart-ad9a56f2-9c7b-46b8-aaf1-95992c0e4e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110825073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.2110825073
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.2069739653
Short name T493
Test name
Test status
Simulation time 2678384195 ps
CPU time 10.62 seconds
Started Jan 24 07:13:33 PM PST 24
Finished Jan 24 07:13:44 PM PST 24
Peak memory 201868 kb
Host smart-202f03ee-08bf-433f-b96e-c3928268725c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069739653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.2069739653
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.2730849667
Short name T788
Test name
Test status
Simulation time 89409923 ps
CPU time 4.06 seconds
Started Jan 24 05:42:04 PM PST 24
Finished Jan 24 05:42:09 PM PST 24
Peak memory 218140 kb
Host smart-b50763c0-0ae2-466c-9b06-afe8e422fea7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730849667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.2730849667
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.333168775
Short name T534
Test name
Test status
Simulation time 166128090 ps
CPU time 5.56 seconds
Started Jan 24 05:42:40 PM PST 24
Finished Jan 24 05:42:47 PM PST 24
Peak memory 218256 kb
Host smart-c2cde43b-1289-4778-9c75-69ddd05ddd6c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333168775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_mem_partial_access.333168775
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.3627181164
Short name T481
Test name
Test status
Simulation time 78389283 ps
CPU time 4.52 seconds
Started Jan 24 05:42:42 PM PST 24
Finished Jan 24 05:42:51 PM PST 24
Peak memory 201900 kb
Host smart-c0772b75-401e-4ac8-9229-bd0a7cb38913
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627181164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.3627181164
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.1432968223
Short name T553
Test name
Test status
Simulation time 12628570778 ps
CPU time 1550.26 seconds
Started Jan 24 06:23:03 PM PST 24
Finished Jan 24 06:48:54 PM PST 24
Peak memory 372760 kb
Host smart-a8d60914-b876-4019-be14-07111b619260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432968223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.1432968223
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.874234693
Short name T801
Test name
Test status
Simulation time 3158051519 ps
CPU time 14.82 seconds
Started Jan 24 08:02:14 PM PST 24
Finished Jan 24 08:02:31 PM PST 24
Peak memory 201992 kb
Host smart-96823efd-fe28-4d17-8e5e-62cdebb3c19a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874234693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr
am_ctrl_partial_access.874234693
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.4200901034
Short name T761
Test name
Test status
Simulation time 3373582067 ps
CPU time 243.39 seconds
Started Jan 24 05:42:07 PM PST 24
Finished Jan 24 05:46:11 PM PST 24
Peak memory 201920 kb
Host smart-f101b0ab-25e1-43bd-83e6-c04d1e3a1588
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200901034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.4200901034
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.1775162160
Short name T417
Test name
Test status
Simulation time 81717666 ps
CPU time 0.86 seconds
Started Jan 24 06:30:07 PM PST 24
Finished Jan 24 06:30:08 PM PST 24
Peak memory 201964 kb
Host smart-f4d1cd9f-0b8e-4f04-a639-c56495b29fed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775162160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1775162160
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.241810308
Short name T526
Test name
Test status
Simulation time 60450823563 ps
CPU time 1188.37 seconds
Started Jan 24 05:42:24 PM PST 24
Finished Jan 24 06:02:15 PM PST 24
Peak memory 366424 kb
Host smart-d3174fdb-e1cc-4d69-b54b-4d3f5d61c202
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241810308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.241810308
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.4171707362
Short name T32
Test name
Test status
Simulation time 214143220 ps
CPU time 2.14 seconds
Started Jan 24 06:24:59 PM PST 24
Finished Jan 24 06:25:02 PM PST 24
Peak memory 220360 kb
Host smart-050b0b47-6427-45a5-96da-c0dab45b251d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171707362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.4171707362
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.1933155570
Short name T614
Test name
Test status
Simulation time 865978050 ps
CPU time 14.57 seconds
Started Jan 24 05:41:52 PM PST 24
Finished Jan 24 05:42:08 PM PST 24
Peak memory 201848 kb
Host smart-2d5908b3-6d7d-48f5-b72d-6c8fdf95968b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933155570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1933155570
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3436753123
Short name T46
Test name
Test status
Simulation time 993277590 ps
CPU time 2796.65 seconds
Started Jan 24 05:56:55 PM PST 24
Finished Jan 24 06:43:32 PM PST 24
Peak memory 429560 kb
Host smart-d32251f0-870a-4af2-b072-f2f97c63a9db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3436753123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.3436753123
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3581615755
Short name T955
Test name
Test status
Simulation time 4536228658 ps
CPU time 281.9 seconds
Started Jan 24 05:41:53 PM PST 24
Finished Jan 24 05:46:36 PM PST 24
Peak memory 201960 kb
Host smart-2524e38d-09ee-4618-8ecc-7f585b25f446
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581615755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.3581615755
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1138490904
Short name T520
Test name
Test status
Simulation time 79142751 ps
CPU time 2.57 seconds
Started Jan 24 05:55:32 PM PST 24
Finished Jan 24 05:55:36 PM PST 24
Peak memory 211144 kb
Host smart-0330a73e-b9ea-4948-b7f6-6170856fdacb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138490904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1138490904
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.952033674
Short name T694
Test name
Test status
Simulation time 2648083788 ps
CPU time 515.72 seconds
Started Jan 24 05:43:28 PM PST 24
Finished Jan 24 05:52:04 PM PST 24
Peak memory 356172 kb
Host smart-1d45badf-8d9c-42db-9e91-7e67b14cc97d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952033674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_access_during_key_req.952033674
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.651223215
Short name T516
Test name
Test status
Simulation time 1904449913 ps
CPU time 41.74 seconds
Started Jan 24 06:28:06 PM PST 24
Finished Jan 24 06:28:48 PM PST 24
Peak memory 201820 kb
Host smart-57946c78-d01f-4fb2-b93c-703f21fb2032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651223215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.651223215
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.2063740340
Short name T362
Test name
Test status
Simulation time 3544188958 ps
CPU time 492.09 seconds
Started Jan 24 05:43:37 PM PST 24
Finished Jan 24 05:51:49 PM PST 24
Peak memory 359408 kb
Host smart-79025f77-a2ca-4a11-b3e2-99caf85e015a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063740340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.2063740340
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.3714552396
Short name T266
Test name
Test status
Simulation time 6761519273 ps
CPU time 9.14 seconds
Started Jan 24 06:02:30 PM PST 24
Finished Jan 24 06:02:40 PM PST 24
Peak memory 210068 kb
Host smart-43f8bb18-c985-46ee-94e8-d43c9e19f7d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714552396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.3714552396
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.4038169715
Short name T937
Test name
Test status
Simulation time 1015871416 ps
CPU time 51.09 seconds
Started Jan 24 06:45:59 PM PST 24
Finished Jan 24 06:46:51 PM PST 24
Peak memory 305100 kb
Host smart-6e296ee0-0796-4d4d-bc10-8bb58e53e955
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038169715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.4038169715
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.510385445
Short name T536
Test name
Test status
Simulation time 175513765 ps
CPU time 3.07 seconds
Started Jan 24 05:43:47 PM PST 24
Finished Jan 24 05:43:51 PM PST 24
Peak memory 211208 kb
Host smart-6eea4af2-7078-4ea8-b3ef-e16673b644d8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510385445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_mem_partial_access.510385445
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.3006719483
Short name T447
Test name
Test status
Simulation time 347153715 ps
CPU time 5.47 seconds
Started Jan 24 05:43:46 PM PST 24
Finished Jan 24 05:43:52 PM PST 24
Peak memory 201920 kb
Host smart-3946fe84-648f-45f4-bc18-0eb9f2105b8c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006719483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.3006719483
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.1521576716
Short name T514
Test name
Test status
Simulation time 2733397218 ps
CPU time 352.88 seconds
Started Jan 24 05:43:10 PM PST 24
Finished Jan 24 05:49:03 PM PST 24
Peak memory 373552 kb
Host smart-7b4bc591-c245-4a8f-b90c-913ba71548b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521576716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.1521576716
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.3110522328
Short name T968
Test name
Test status
Simulation time 200142828 ps
CPU time 125.38 seconds
Started Jan 24 05:43:13 PM PST 24
Finished Jan 24 05:45:19 PM PST 24
Peak memory 342120 kb
Host smart-09455324-bbf4-4c2a-8956-7d65152dc5d9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110522328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.3110522328
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.10838237
Short name T220
Test name
Test status
Simulation time 66073730135 ps
CPU time 392.75 seconds
Started Jan 24 05:43:11 PM PST 24
Finished Jan 24 05:49:45 PM PST 24
Peak memory 201908 kb
Host smart-f7b2b6c1-d55f-4534-87f9-5568c7ca2f37
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10838237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_partial_access_b2b.10838237
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.3129626532
Short name T873
Test name
Test status
Simulation time 35301551 ps
CPU time 0.89 seconds
Started Jan 24 05:43:48 PM PST 24
Finished Jan 24 05:43:49 PM PST 24
Peak memory 201968 kb
Host smart-d5b55810-a843-4f3b-b3e7-3e30cb99fd27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129626532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3129626532
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.175772471
Short name T864
Test name
Test status
Simulation time 12544501937 ps
CPU time 225.53 seconds
Started Jan 24 05:43:42 PM PST 24
Finished Jan 24 05:47:28 PM PST 24
Peak memory 359664 kb
Host smart-dfdfd488-7c3f-4343-bee1-27f6f76886f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175772471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.175772471
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.3963844575
Short name T748
Test name
Test status
Simulation time 174738137 ps
CPU time 3.41 seconds
Started Jan 24 05:43:01 PM PST 24
Finished Jan 24 05:43:05 PM PST 24
Peak memory 212004 kb
Host smart-b175db75-5e5e-478b-ab45-affb604630e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963844575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3963844575
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.137855186
Short name T281
Test name
Test status
Simulation time 66233927613 ps
CPU time 2586.64 seconds
Started Jan 24 05:43:55 PM PST 24
Finished Jan 24 06:27:02 PM PST 24
Peak memory 374672 kb
Host smart-27173cc6-0749-45dc-a70f-4d963a63855f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137855186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_stress_all.137855186
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2464330998
Short name T278
Test name
Test status
Simulation time 1511404257 ps
CPU time 1430.62 seconds
Started Jan 24 08:22:00 PM PST 24
Finished Jan 24 08:45:59 PM PST 24
Peak memory 410688 kb
Host smart-b99ff0cf-6012-418a-9a15-4a0a6d4500ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2464330998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2464330998
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3212151852
Short name T630
Test name
Test status
Simulation time 2042182517 ps
CPU time 200.45 seconds
Started Jan 24 05:43:09 PM PST 24
Finished Jan 24 05:46:30 PM PST 24
Peak memory 201864 kb
Host smart-680e5ff9-f0c6-43a9-8ad8-8dc490448f70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212151852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.3212151852
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3216604686
Short name T9
Test name
Test status
Simulation time 371890543 ps
CPU time 20.15 seconds
Started Jan 24 05:51:41 PM PST 24
Finished Jan 24 05:52:02 PM PST 24
Peak memory 256380 kb
Host smart-0dca6246-0994-4f17-9cf2-275dfa648de3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216604686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3216604686
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2389162907
Short name T663
Test name
Test status
Simulation time 1417237994 ps
CPU time 248.44 seconds
Started Jan 24 05:52:28 PM PST 24
Finished Jan 24 05:56:37 PM PST 24
Peak memory 349480 kb
Host smart-0c00ebcb-aac9-4c33-b9f3-70281efd4c43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389162907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.2389162907
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.3922795698
Short name T395
Test name
Test status
Simulation time 904953812 ps
CPU time 58.35 seconds
Started Jan 24 05:52:13 PM PST 24
Finished Jan 24 05:53:12 PM PST 24
Peak memory 201844 kb
Host smart-253af172-0179-4f5e-b987-ddd2b5205f07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922795698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.3922795698
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.1171056137
Short name T543
Test name
Test status
Simulation time 3193123516 ps
CPU time 1199.06 seconds
Started Jan 24 05:52:25 PM PST 24
Finished Jan 24 06:12:25 PM PST 24
Peak memory 373760 kb
Host smart-1518439f-6cfa-4aaa-b18b-c83fcdde68e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171056137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.1171056137
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.2341524111
Short name T732
Test name
Test status
Simulation time 1314241734 ps
CPU time 9.55 seconds
Started Jan 24 06:22:56 PM PST 24
Finished Jan 24 06:23:07 PM PST 24
Peak memory 210124 kb
Host smart-2565fa1b-b45b-43df-9f54-4126b2f10f5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341524111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.2341524111
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.2945002227
Short name T456
Test name
Test status
Simulation time 99388257 ps
CPU time 42.78 seconds
Started Jan 24 06:49:48 PM PST 24
Finished Jan 24 06:50:31 PM PST 24
Peak memory 286884 kb
Host smart-e879365b-66e8-45e3-81a6-694911a40364
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945002227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.2945002227
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.571414756
Short name T230
Test name
Test status
Simulation time 307475565 ps
CPU time 5.8 seconds
Started Jan 24 05:52:30 PM PST 24
Finished Jan 24 05:52:36 PM PST 24
Peak memory 215004 kb
Host smart-a915c257-731a-43af-91e1-c8fcc3155938
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571414756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.sram_ctrl_mem_partial_access.571414756
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.3203874412
Short name T791
Test name
Test status
Simulation time 927485199 ps
CPU time 5.33 seconds
Started Jan 24 05:52:28 PM PST 24
Finished Jan 24 05:52:34 PM PST 24
Peak memory 201968 kb
Host smart-a73a63bb-73e2-42a9-a063-7a74ee2e28cd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203874412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.3203874412
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.506843240
Short name T606
Test name
Test status
Simulation time 3930856949 ps
CPU time 259.22 seconds
Started Jan 24 05:52:14 PM PST 24
Finished Jan 24 05:56:33 PM PST 24
Peak memory 344600 kb
Host smart-d40df7b1-9ae7-4ad6-8b8a-38c26ac9290f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506843240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip
le_keys.506843240
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.2795369194
Short name T235
Test name
Test status
Simulation time 1212053278 ps
CPU time 18.8 seconds
Started Jan 24 05:52:16 PM PST 24
Finished Jan 24 05:52:36 PM PST 24
Peak memory 201852 kb
Host smart-e570870c-22e4-4e8d-8201-fca04c14bf41
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795369194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.2795369194
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.306535826
Short name T120
Test name
Test status
Simulation time 5245800442 ps
CPU time 380.61 seconds
Started Jan 24 07:34:11 PM PST 24
Finished Jan 24 07:40:33 PM PST 24
Peak memory 201900 kb
Host smart-ee13b6df-b1a8-4baa-a367-65e7d3955a35
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306535826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.sram_ctrl_partial_access_b2b.306535826
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.3764517820
Short name T784
Test name
Test status
Simulation time 45906965 ps
CPU time 0.86 seconds
Started Jan 24 05:52:29 PM PST 24
Finished Jan 24 05:52:31 PM PST 24
Peak memory 201940 kb
Host smart-a6675f4d-821e-4daf-aa89-b9b49e8752dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764517820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3764517820
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.873285349
Short name T680
Test name
Test status
Simulation time 2432173866 ps
CPU time 635.42 seconds
Started Jan 24 05:52:29 PM PST 24
Finished Jan 24 06:03:05 PM PST 24
Peak memory 357820 kb
Host smart-9f796443-c68e-4672-81d8-a8460a9cea5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873285349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.873285349
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.2562747107
Short name T605
Test name
Test status
Simulation time 913900899 ps
CPU time 15.07 seconds
Started Jan 24 05:52:15 PM PST 24
Finished Jan 24 05:52:30 PM PST 24
Peak memory 201704 kb
Host smart-3f72d6e8-786a-417e-a512-141ad820510e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562747107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2562747107
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.4223813577
Short name T673
Test name
Test status
Simulation time 987325295093 ps
CPU time 6446.96 seconds
Started Jan 24 05:52:32 PM PST 24
Finished Jan 24 07:40:01 PM PST 24
Peak memory 373528 kb
Host smart-a194d91b-80e8-4b81-9717-5c0f32214c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223813577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.4223813577
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3702138506
Short name T552
Test name
Test status
Simulation time 1189242420 ps
CPU time 140.5 seconds
Started Jan 24 07:19:23 PM PST 24
Finished Jan 24 07:21:45 PM PST 24
Peak memory 313264 kb
Host smart-d5953943-471b-4b86-b5b2-b860484d0a27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3702138506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3702138506
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1041078174
Short name T821
Test name
Test status
Simulation time 16069772814 ps
CPU time 238.54 seconds
Started Jan 24 05:52:16 PM PST 24
Finished Jan 24 05:56:15 PM PST 24
Peak memory 201964 kb
Host smart-1967b330-74f4-4084-a69e-9cb144eeb030
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041078174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.1041078174
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.526267110
Short name T275
Test name
Test status
Simulation time 77551675 ps
CPU time 17.64 seconds
Started Jan 24 05:52:20 PM PST 24
Finished Jan 24 05:52:38 PM PST 24
Peak memory 260000 kb
Host smart-6de34172-c9b7-4132-baa9-ef3e1e740625
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526267110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.526267110
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3540506823
Short name T718
Test name
Test status
Simulation time 4207104629 ps
CPU time 1078.57 seconds
Started Jan 24 05:53:25 PM PST 24
Finished Jan 24 06:11:24 PM PST 24
Peak memory 357412 kb
Host smart-6dcec721-240c-45e9-aa63-c6e2b834fead
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540506823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.3540506823
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.3054182110
Short name T638
Test name
Test status
Simulation time 15334125 ps
CPU time 0.67 seconds
Started Jan 24 05:53:34 PM PST 24
Finished Jan 24 05:53:38 PM PST 24
Peak memory 201684 kb
Host smart-09e1cfdf-e445-49d9-bbaf-6208a0f82520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054182110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.3054182110
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.1562324863
Short name T917
Test name
Test status
Simulation time 523617266 ps
CPU time 33.9 seconds
Started Jan 24 07:25:19 PM PST 24
Finished Jan 24 07:25:55 PM PST 24
Peak memory 201892 kb
Host smart-726787f2-e308-4e7c-bfe5-cbfd9411a7cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562324863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.1562324863
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.3820009353
Short name T454
Test name
Test status
Simulation time 33743251325 ps
CPU time 1225.46 seconds
Started Jan 24 06:01:40 PM PST 24
Finished Jan 24 06:22:06 PM PST 24
Peak memory 372576 kb
Host smart-39f415a2-e76c-4ebc-bc09-45a0203d4105
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820009353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.3820009353
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.2667867038
Short name T407
Test name
Test status
Simulation time 243365096 ps
CPU time 3.6 seconds
Started Jan 24 05:53:20 PM PST 24
Finished Jan 24 05:53:24 PM PST 24
Peak memory 217952 kb
Host smart-3e9ab5ff-732e-4dcb-bbbe-9c60fb301bf8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667867038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.2667867038
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.4152452516
Short name T805
Test name
Test status
Simulation time 161226840 ps
CPU time 3.21 seconds
Started Jan 24 05:53:30 PM PST 24
Finished Jan 24 05:53:34 PM PST 24
Peak memory 211112 kb
Host smart-2725f94c-7e67-4476-a2f0-6a41eb17a823
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152452516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.4152452516
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.715166744
Short name T624
Test name
Test status
Simulation time 148449554 ps
CPU time 8.37 seconds
Started Jan 24 05:53:26 PM PST 24
Finished Jan 24 05:53:35 PM PST 24
Peak memory 201780 kb
Host smart-fe7afe65-eac9-45a2-b788-c6f5ed608e4b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715166744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_mem_walk.715166744
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.501415745
Short name T354
Test name
Test status
Simulation time 19087331718 ps
CPU time 992.03 seconds
Started Jan 24 05:52:35 PM PST 24
Finished Jan 24 06:09:08 PM PST 24
Peak memory 364496 kb
Host smart-a609a30c-a894-48ef-813a-0b3acf0f92b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501415745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multip
le_keys.501415745
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.2554429028
Short name T246
Test name
Test status
Simulation time 731394406 ps
CPU time 134.51 seconds
Started Jan 24 06:25:23 PM PST 24
Finished Jan 24 06:27:38 PM PST 24
Peak memory 368212 kb
Host smart-f908d045-5b6b-4afd-b29e-98d818fbd081
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554429028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.2554429028
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3774632029
Short name T814
Test name
Test status
Simulation time 64348312622 ps
CPU time 364.87 seconds
Started Jan 24 05:53:20 PM PST 24
Finished Jan 24 05:59:26 PM PST 24
Peak memory 201860 kb
Host smart-5f0ecbe9-ccfe-44e8-a922-81700eb3b59a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774632029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.3774632029
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.2059803847
Short name T714
Test name
Test status
Simulation time 20324487547 ps
CPU time 867.21 seconds
Started Jan 24 06:14:14 PM PST 24
Finished Jan 24 06:28:42 PM PST 24
Peak memory 361476 kb
Host smart-b89eb532-4c0e-4ef8-a3f5-751125861024
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059803847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2059803847
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.2340912536
Short name T236
Test name
Test status
Simulation time 3436220131 ps
CPU time 13.08 seconds
Started Jan 24 06:33:23 PM PST 24
Finished Jan 24 06:33:37 PM PST 24
Peak memory 201864 kb
Host smart-9ef77f5e-701e-4cfb-8723-db9b24996888
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340912536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2340912536
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.1228133970
Short name T291
Test name
Test status
Simulation time 68599213702 ps
CPU time 3686.29 seconds
Started Jan 24 05:53:32 PM PST 24
Finished Jan 24 06:55:00 PM PST 24
Peak memory 373768 kb
Host smart-e70851b7-fc7e-4454-9d97-dd9de94c5ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228133970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.1228133970
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2363758892
Short name T717
Test name
Test status
Simulation time 6792214130 ps
CPU time 4634.59 seconds
Started Jan 24 05:53:32 PM PST 24
Finished Jan 24 07:10:48 PM PST 24
Peak memory 420024 kb
Host smart-efd5f005-5a03-4017-93bb-cfb681a27723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2363758892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2363758892
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1719523551
Short name T950
Test name
Test status
Simulation time 2291597766 ps
CPU time 215.22 seconds
Started Jan 24 07:18:43 PM PST 24
Finished Jan 24 07:22:19 PM PST 24
Peak memory 201948 kb
Host smart-45c67792-0e86-4faf-a005-065f65b47ed3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719523551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.1719523551
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.487475785
Short name T863
Test name
Test status
Simulation time 130013639 ps
CPU time 3.75 seconds
Started Jan 24 05:53:25 PM PST 24
Finished Jan 24 05:53:29 PM PST 24
Peak memory 218204 kb
Host smart-2e50c0ed-030d-4703-b0d6-c246ffded637
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487475785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.487475785
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1133667991
Short name T960
Test name
Test status
Simulation time 6064853250 ps
CPU time 1240.95 seconds
Started Jan 24 05:53:41 PM PST 24
Finished Jan 24 06:14:23 PM PST 24
Peak memory 372724 kb
Host smart-5a532365-b074-40ab-b18b-d80250d58b83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133667991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.1133667991
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.1155643485
Short name T517
Test name
Test status
Simulation time 14318012 ps
CPU time 0.65 seconds
Started Jan 24 05:54:09 PM PST 24
Finished Jan 24 05:54:11 PM PST 24
Peak memory 200700 kb
Host smart-d71a7ab7-31ff-4cd1-b7a7-e886597d5b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155643485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.1155643485
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.2394609032
Short name T958
Test name
Test status
Simulation time 7592178751 ps
CPU time 66.77 seconds
Started Jan 24 06:31:13 PM PST 24
Finished Jan 24 06:32:20 PM PST 24
Peak memory 201916 kb
Host smart-a5ab3c3e-5fa8-4a8c-a3ba-193d168a6f2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394609032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.2394609032
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.709512975
Short name T11
Test name
Test status
Simulation time 19698394306 ps
CPU time 1005.68 seconds
Started Jan 24 06:11:16 PM PST 24
Finished Jan 24 06:28:02 PM PST 24
Peak memory 368444 kb
Host smart-2f8801d9-4a41-4969-a706-5c6f41b2bb9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709512975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executabl
e.709512975
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.109781867
Short name T952
Test name
Test status
Simulation time 494983671 ps
CPU time 3.05 seconds
Started Jan 24 05:53:42 PM PST 24
Finished Jan 24 05:53:46 PM PST 24
Peak memory 210084 kb
Host smart-2ba4cdec-5152-4426-864a-8c9dc395b478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109781867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_esc
alation.109781867
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.1852189734
Short name T972
Test name
Test status
Simulation time 95110741 ps
CPU time 18.04 seconds
Started Jan 24 05:53:36 PM PST 24
Finished Jan 24 05:53:56 PM PST 24
Peak memory 258928 kb
Host smart-2a5c7ee3-9607-4751-b35b-e3de86697f07
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852189734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.1852189734
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2029086966
Short name T392
Test name
Test status
Simulation time 87178796 ps
CPU time 3.05 seconds
Started Jan 24 05:54:00 PM PST 24
Finished Jan 24 05:54:03 PM PST 24
Peak memory 210148 kb
Host smart-aa1343af-2d4e-4639-a11f-c9b4201f4f47
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029086966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.2029086966
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.2036108827
Short name T936
Test name
Test status
Simulation time 2391894300 ps
CPU time 10.28 seconds
Started Jan 24 06:00:14 PM PST 24
Finished Jan 24 06:00:26 PM PST 24
Peak memory 201992 kb
Host smart-16ff8d44-652c-4567-8111-d11486970b8d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036108827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.2036108827
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.2707202780
Short name T436
Test name
Test status
Simulation time 20773550554 ps
CPU time 217.03 seconds
Started Jan 24 05:53:33 PM PST 24
Finished Jan 24 05:57:14 PM PST 24
Peak memory 302764 kb
Host smart-b0a4fa68-635c-4a58-969d-d91a49a3851b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707202780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.2707202780
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.3239314834
Short name T320
Test name
Test status
Simulation time 4792443508 ps
CPU time 62.1 seconds
Started Jan 24 05:53:36 PM PST 24
Finished Jan 24 05:54:40 PM PST 24
Peak memory 306172 kb
Host smart-5e2d5c03-7020-444e-80f3-b745d25d2869
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239314834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.3239314834
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.809183309
Short name T651
Test name
Test status
Simulation time 15675900603 ps
CPU time 420.92 seconds
Started Jan 24 05:53:37 PM PST 24
Finished Jan 24 06:00:39 PM PST 24
Peak memory 201868 kb
Host smart-ba923e3a-ea34-4b05-b3e2-d31ffd92eeab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809183309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.sram_ctrl_partial_access_b2b.809183309
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.3412516593
Short name T448
Test name
Test status
Simulation time 46625279 ps
CPU time 0.85 seconds
Started Jan 24 05:53:54 PM PST 24
Finished Jan 24 05:53:55 PM PST 24
Peak memory 201956 kb
Host smart-dfa74030-6e0f-4345-80ca-4239337fd336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412516593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3412516593
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.1194161847
Short name T927
Test name
Test status
Simulation time 3308030015 ps
CPU time 551.96 seconds
Started Jan 24 05:53:46 PM PST 24
Finished Jan 24 06:02:59 PM PST 24
Peak memory 370844 kb
Host smart-8ce0bb49-a346-4b5b-be1a-67e233211830
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194161847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1194161847
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.2694086728
Short name T866
Test name
Test status
Simulation time 2596022018 ps
CPU time 28.49 seconds
Started Jan 24 07:32:48 PM PST 24
Finished Jan 24 07:33:19 PM PST 24
Peak memory 286696 kb
Host smart-8b189cb2-19f9-4085-81c4-7d058d05de88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694086728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2694086728
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.1696386477
Short name T582
Test name
Test status
Simulation time 88960778897 ps
CPU time 5041.27 seconds
Started Jan 24 06:12:25 PM PST 24
Finished Jan 24 07:36:28 PM PST 24
Peak memory 374244 kb
Host smart-4633e26c-5152-4fa7-9e6b-ae7cc7123cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696386477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.1696386477
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1473758143
Short name T223
Test name
Test status
Simulation time 679285252 ps
CPU time 2056.5 seconds
Started Jan 24 05:53:58 PM PST 24
Finished Jan 24 06:28:15 PM PST 24
Peak memory 432156 kb
Host smart-62bd3c18-d033-4d9d-af9a-0358a292e921
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1473758143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1473758143
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1270645139
Short name T341
Test name
Test status
Simulation time 10990447161 ps
CPU time 270.87 seconds
Started Jan 24 05:53:35 PM PST 24
Finished Jan 24 05:58:09 PM PST 24
Peak memory 201912 kb
Host smart-24a3feee-c3d1-40f1-ace1-9d072339dd99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270645139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.1270645139
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2425045043
Short name T233
Test name
Test status
Simulation time 555490891 ps
CPU time 129.73 seconds
Started Jan 24 05:53:38 PM PST 24
Finished Jan 24 05:55:48 PM PST 24
Peak memory 363336 kb
Host smart-6cdfd338-7a8d-4e65-8a40-70b52addd7da
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425045043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.2425045043
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.226405060
Short name T455
Test name
Test status
Simulation time 3708560343 ps
CPU time 998.43 seconds
Started Jan 24 05:54:21 PM PST 24
Finished Jan 24 06:11:00 PM PST 24
Peak memory 365488 kb
Host smart-dbe693db-c00e-4325-ad2a-5b5458b7ac58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226405060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.sram_ctrl_access_during_key_req.226405060
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.1090637874
Short name T613
Test name
Test status
Simulation time 22488568 ps
CPU time 0.64 seconds
Started Jan 24 05:54:45 PM PST 24
Finished Jan 24 05:54:46 PM PST 24
Peak memory 201728 kb
Host smart-8ffce069-9f7b-46de-851d-730a75741b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090637874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.1090637874
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.2444901596
Short name T116
Test name
Test status
Simulation time 6368766229 ps
CPU time 51.85 seconds
Started Jan 24 07:30:52 PM PST 24
Finished Jan 24 07:31:45 PM PST 24
Peak memory 201940 kb
Host smart-185502a2-e421-40be-a65d-67d115f35f56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444901596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.2444901596
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.3451565560
Short name T257
Test name
Test status
Simulation time 2871273327 ps
CPU time 859.29 seconds
Started Jan 24 05:54:34 PM PST 24
Finished Jan 24 06:08:54 PM PST 24
Peak memory 355576 kb
Host smart-fb093060-6eb9-47fd-8b6f-b41d17a8f269
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451565560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.3451565560
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.1798335937
Short name T963
Test name
Test status
Simulation time 106575517 ps
CPU time 50.81 seconds
Started Jan 24 05:54:22 PM PST 24
Finished Jan 24 05:55:13 PM PST 24
Peak memory 299920 kb
Host smart-2e6e6b7b-69a5-4d93-88e6-4424c021bc6b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798335937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.1798335937
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3151575037
Short name T79
Test name
Test status
Simulation time 330308754 ps
CPU time 4.98 seconds
Started Jan 24 05:54:39 PM PST 24
Finished Jan 24 05:54:44 PM PST 24
Peak memory 214864 kb
Host smart-c11c9179-a30f-4b6f-aa04-06b591f1fc63
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151575037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.3151575037
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.1193941344
Short name T838
Test name
Test status
Simulation time 2256858044 ps
CPU time 702.03 seconds
Started Jan 24 05:55:58 PM PST 24
Finished Jan 24 06:07:41 PM PST 24
Peak memory 371540 kb
Host smart-c5b74ffd-f0bc-4983-9158-a26acf0c18ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193941344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.1193941344
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.2637512866
Short name T384
Test name
Test status
Simulation time 648545252 ps
CPU time 77.27 seconds
Started Jan 24 06:58:59 PM PST 24
Finished Jan 24 07:00:24 PM PST 24
Peak memory 316988 kb
Host smart-d1c34f51-1d93-4c6b-a184-8594d089f09d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637512866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.2637512866
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3887444938
Short name T124
Test name
Test status
Simulation time 23579644946 ps
CPU time 420.03 seconds
Started Jan 24 07:47:02 PM PST 24
Finished Jan 24 07:54:05 PM PST 24
Peak memory 201948 kb
Host smart-7b0fee75-a929-4461-b0a4-d0f707de4af7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887444938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.3887444938
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.2994416042
Short name T561
Test name
Test status
Simulation time 93575655 ps
CPU time 0.82 seconds
Started Jan 24 05:54:38 PM PST 24
Finished Jan 24 05:54:40 PM PST 24
Peak memory 201840 kb
Host smart-72491ef3-c1dd-4f69-8199-7396658530a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994416042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2994416042
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.523636059
Short name T108
Test name
Test status
Simulation time 3803155468 ps
CPU time 1482.34 seconds
Started Jan 24 06:31:36 PM PST 24
Finished Jan 24 06:56:19 PM PST 24
Peak memory 368696 kb
Host smart-b187e216-153c-428c-bf3e-2849f3ee92b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523636059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.523636059
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.2049534771
Short name T587
Test name
Test status
Simulation time 912484826 ps
CPU time 10.43 seconds
Started Jan 24 06:17:57 PM PST 24
Finished Jan 24 06:18:09 PM PST 24
Peak memory 201896 kb
Host smart-afe914ce-6d1e-4b11-b8a8-3843b1a19184
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049534771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2049534771
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.579851726
Short name T872
Test name
Test status
Simulation time 897996117 ps
CPU time 4683 seconds
Started Jan 24 05:54:44 PM PST 24
Finished Jan 24 07:12:47 PM PST 24
Peak memory 403248 kb
Host smart-53214da4-04c3-44fa-85c4-ea23e5fc0f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=579851726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.579851726
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3558164975
Short name T850
Test name
Test status
Simulation time 8301051926 ps
CPU time 174.95 seconds
Started Jan 24 06:34:07 PM PST 24
Finished Jan 24 06:37:03 PM PST 24
Peak memory 201932 kb
Host smart-e79f0e6e-39d8-445f-95b4-8b1f36b86eac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558164975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.3558164975
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3253159099
Short name T298
Test name
Test status
Simulation time 202794373 ps
CPU time 35.91 seconds
Started Jan 24 05:54:20 PM PST 24
Finished Jan 24 05:54:57 PM PST 24
Peak memory 283652 kb
Host smart-7f9443fd-3623-473c-88ba-3f6c24e3ffc7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253159099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3253159099
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.1152905985
Short name T634
Test name
Test status
Simulation time 38091024 ps
CPU time 0.65 seconds
Started Jan 24 05:55:45 PM PST 24
Finished Jan 24 05:55:46 PM PST 24
Peak memory 200760 kb
Host smart-32e2bfd3-1336-48c2-a330-996348648f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152905985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.1152905985
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.2362797590
Short name T785
Test name
Test status
Simulation time 9817989890 ps
CPU time 71.08 seconds
Started Jan 24 05:54:54 PM PST 24
Finished Jan 24 05:56:05 PM PST 24
Peak memory 201856 kb
Host smart-5c3592d6-ae45-4fdc-8141-f8d85c57e976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362797590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.2362797590
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.1330554352
Short name T635
Test name
Test status
Simulation time 16092748892 ps
CPU time 188.5 seconds
Started Jan 24 05:55:21 PM PST 24
Finished Jan 24 05:58:31 PM PST 24
Peak memory 353180 kb
Host smart-7f53e611-1a9c-46c9-8e30-ae06214c05c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330554352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.1330554352
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.1339110174
Short name T293
Test name
Test status
Simulation time 182358773 ps
CPU time 4.47 seconds
Started Jan 24 05:55:08 PM PST 24
Finished Jan 24 05:55:13 PM PST 24
Peak memory 218132 kb
Host smart-7cba221c-6b2b-4a23-8e5f-c0f20f5fe6af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339110174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.1339110174
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1209723971
Short name T237
Test name
Test status
Simulation time 151692997 ps
CPU time 5.33 seconds
Started Jan 24 05:55:34 PM PST 24
Finished Jan 24 05:55:40 PM PST 24
Peak memory 215068 kb
Host smart-a8523ff0-afdd-48cb-9625-67578eb80fd5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209723971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.1209723971
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.100203827
Short name T701
Test name
Test status
Simulation time 151898545 ps
CPU time 7.91 seconds
Started Jan 24 06:05:23 PM PST 24
Finished Jan 24 06:05:35 PM PST 24
Peak memory 202004 kb
Host smart-9ccdd80b-42ff-472e-bf52-3e3525e2923c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100203827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl
_mem_walk.100203827
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.3231690191
Short name T419
Test name
Test status
Simulation time 2130184736 ps
CPU time 211.84 seconds
Started Jan 24 05:54:57 PM PST 24
Finished Jan 24 05:58:30 PM PST 24
Peak memory 372604 kb
Host smart-d3e7260d-4b7c-4b50-9ba2-5603e489e60b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231690191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.3231690191
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.2814125161
Short name T265
Test name
Test status
Simulation time 2204257821 ps
CPU time 10.51 seconds
Started Jan 24 05:54:55 PM PST 24
Finished Jan 24 05:55:06 PM PST 24
Peak memory 201948 kb
Host smart-1732d700-c637-49a7-a592-a23db311ba5b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814125161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.2814125161
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3952873947
Short name T62
Test name
Test status
Simulation time 14098704493 ps
CPU time 261.98 seconds
Started Jan 24 05:54:58 PM PST 24
Finished Jan 24 05:59:20 PM PST 24
Peak memory 201964 kb
Host smart-95f1e447-099e-4b2e-8f9d-411548c9da92
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952873947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.3952873947
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.404045954
Short name T745
Test name
Test status
Simulation time 38170255 ps
CPU time 0.88 seconds
Started Jan 24 06:30:54 PM PST 24
Finished Jan 24 06:30:56 PM PST 24
Peak memory 201964 kb
Host smart-a3bd2106-9a8c-40a3-bfe3-df6612e2a6bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404045954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.404045954
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.3109454346
Short name T269
Test name
Test status
Simulation time 10792286790 ps
CPU time 1476.33 seconds
Started Jan 24 05:55:22 PM PST 24
Finished Jan 24 06:19:59 PM PST 24
Peak memory 372688 kb
Host smart-12aa9594-1827-452e-8385-e2dcad66a5ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109454346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3109454346
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.2085950727
Short name T554
Test name
Test status
Simulation time 74490515 ps
CPU time 2.13 seconds
Started Jan 24 05:54:48 PM PST 24
Finished Jan 24 05:54:50 PM PST 24
Peak memory 201848 kb
Host smart-b9bafcef-4143-40c6-a9d0-63946c5cc5aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085950727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2085950727
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.3575848411
Short name T258
Test name
Test status
Simulation time 10325123664 ps
CPU time 1704.3 seconds
Started Jan 24 05:55:40 PM PST 24
Finished Jan 24 06:24:05 PM PST 24
Peak memory 369488 kb
Host smart-110eca7a-827e-4403-937a-34879989ba4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575848411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.3575848411
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1512968413
Short name T633
Test name
Test status
Simulation time 485364027 ps
CPU time 3178.63 seconds
Started Jan 24 05:55:39 PM PST 24
Finished Jan 24 06:48:39 PM PST 24
Peak memory 422256 kb
Host smart-a69a9339-db2f-4b36-9311-fe155b1841c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1512968413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1512968413
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.260075584
Short name T581
Test name
Test status
Simulation time 7181890803 ps
CPU time 178.67 seconds
Started Jan 24 05:54:55 PM PST 24
Finished Jan 24 05:57:54 PM PST 24
Peak memory 201944 kb
Host smart-8a47d775-bc0f-4564-b9f5-5b9cff8edb75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260075584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_stress_pipeline.260075584
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1092680440
Short name T570
Test name
Test status
Simulation time 49096545 ps
CPU time 1.96 seconds
Started Jan 24 05:55:09 PM PST 24
Finished Jan 24 05:55:11 PM PST 24
Peak memory 210072 kb
Host smart-b96f4050-0fd8-4595-96f0-cf6665df7a69
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092680440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1092680440
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3491999443
Short name T733
Test name
Test status
Simulation time 1477809361 ps
CPU time 563.32 seconds
Started Jan 24 05:56:29 PM PST 24
Finished Jan 24 06:05:54 PM PST 24
Peak memory 365304 kb
Host smart-1017450b-a7ec-44ef-bd80-321e33abd940
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491999443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.3491999443
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.2286976449
Short name T957
Test name
Test status
Simulation time 16269109 ps
CPU time 0.62 seconds
Started Jan 24 06:03:55 PM PST 24
Finished Jan 24 06:03:56 PM PST 24
Peak memory 200748 kb
Host smart-2e1b9dd3-b19b-4e4d-a40e-77c2ddbac811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286976449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.2286976449
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.1425032865
Short name T601
Test name
Test status
Simulation time 4458328502 ps
CPU time 50.87 seconds
Started Jan 24 05:56:25 PM PST 24
Finished Jan 24 05:57:16 PM PST 24
Peak memory 201900 kb
Host smart-049fb667-22d3-4b2b-90c7-6befe76d0587
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425032865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.1425032865
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.3667144876
Short name T979
Test name
Test status
Simulation time 3102651115 ps
CPU time 1070.37 seconds
Started Jan 24 05:56:30 PM PST 24
Finished Jan 24 06:14:22 PM PST 24
Peak memory 372500 kb
Host smart-cd504773-bc36-4f25-8797-6bc71154fcff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667144876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.3667144876
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.2490171304
Short name T109
Test name
Test status
Simulation time 498735580 ps
CPU time 4 seconds
Started Jan 24 07:53:04 PM PST 24
Finished Jan 24 07:53:10 PM PST 24
Peak memory 210084 kb
Host smart-10dd6d7a-d7d1-463d-aa6f-a490a28d26ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490171304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.2490171304
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.2437754507
Short name T126
Test name
Test status
Simulation time 174676477 ps
CPU time 45.16 seconds
Started Jan 24 05:56:27 PM PST 24
Finished Jan 24 05:57:12 PM PST 24
Peak memory 286716 kb
Host smart-4941087b-9595-42bd-9b77-b5f356c29574
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437754507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.2437754507
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1462926630
Short name T427
Test name
Test status
Simulation time 76116378 ps
CPU time 4.96 seconds
Started Jan 24 06:51:13 PM PST 24
Finished Jan 24 06:51:18 PM PST 24
Peak memory 210056 kb
Host smart-b6232771-a5f4-4b38-984c-ec5247df7bf7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462926630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.1462926630
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.355677952
Short name T217
Test name
Test status
Simulation time 2954908961 ps
CPU time 10.13 seconds
Started Jan 24 06:03:50 PM PST 24
Finished Jan 24 06:04:01 PM PST 24
Peak memory 201824 kb
Host smart-aac43c3d-9f1c-4261-9136-f18f8f652b6f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355677952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl
_mem_walk.355677952
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.2983999095
Short name T338
Test name
Test status
Simulation time 20446816392 ps
CPU time 548.8 seconds
Started Jan 24 05:55:58 PM PST 24
Finished Jan 24 06:05:08 PM PST 24
Peak memory 339824 kb
Host smart-3f9b7308-6d0b-4519-a778-c181902ea973
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983999095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.2983999095
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.596817548
Short name T390
Test name
Test status
Simulation time 2328808770 ps
CPU time 99.11 seconds
Started Jan 24 05:56:24 PM PST 24
Finished Jan 24 05:58:04 PM PST 24
Peak memory 337712 kb
Host smart-b90a8a3d-34e3-4c9d-908e-8ec66b6fb42f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596817548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s
ram_ctrl_partial_access.596817548
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.4159154544
Short name T572
Test name
Test status
Simulation time 23258801420 ps
CPU time 491.03 seconds
Started Jan 24 05:56:26 PM PST 24
Finished Jan 24 06:04:38 PM PST 24
Peak memory 201900 kb
Host smart-6b5d11ca-fa68-488e-86a8-4262409d4b67
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159154544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.4159154544
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.3571257313
Short name T450
Test name
Test status
Simulation time 85474193 ps
CPU time 0.88 seconds
Started Jan 24 05:56:33 PM PST 24
Finished Jan 24 05:56:34 PM PST 24
Peak memory 201944 kb
Host smart-6a43e9d5-8959-4ea9-808b-d04ac6e17e03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571257313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3571257313
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.1412518605
Short name T818
Test name
Test status
Simulation time 31055747605 ps
CPU time 655.83 seconds
Started Jan 24 05:56:33 PM PST 24
Finished Jan 24 06:07:29 PM PST 24
Peak memory 368560 kb
Host smart-6d8916f8-70c5-44b4-84ed-d970c8216f94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412518605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1412518605
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.1145469619
Short name T661
Test name
Test status
Simulation time 167509251 ps
CPU time 10.49 seconds
Started Jan 24 05:55:49 PM PST 24
Finished Jan 24 05:56:04 PM PST 24
Peak memory 201892 kb
Host smart-6029b68d-3ac2-4391-901a-a53c3afd787f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145469619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1145469619
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1720165180
Short name T404
Test name
Test status
Simulation time 4382175051 ps
CPU time 2753.56 seconds
Started Jan 24 06:33:12 PM PST 24
Finished Jan 24 07:19:06 PM PST 24
Peak memory 401652 kb
Host smart-048c9991-fe92-45d2-8ab3-875483a6340e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1720165180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.1720165180
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1382873048
Short name T681
Test name
Test status
Simulation time 6327410500 ps
CPU time 147.83 seconds
Started Jan 24 07:10:01 PM PST 24
Finished Jan 24 07:12:30 PM PST 24
Peak memory 201932 kb
Host smart-363cf7b0-60ec-4ee8-aad4-57c3120d0143
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382873048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.1382873048
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2782064293
Short name T556
Test name
Test status
Simulation time 146585800 ps
CPU time 100.77 seconds
Started Jan 24 06:42:28 PM PST 24
Finished Jan 24 06:44:09 PM PST 24
Peak memory 345284 kb
Host smart-3aff1bde-8205-44f1-ae7b-ee252e57d226
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782064293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2782064293
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.750990525
Short name T970
Test name
Test status
Simulation time 3452141884 ps
CPU time 988.51 seconds
Started Jan 24 05:57:02 PM PST 24
Finished Jan 24 06:13:31 PM PST 24
Peak memory 370728 kb
Host smart-0e9add32-0f13-4625-93ea-876d332503ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750990525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_access_during_key_req.750990525
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.3583207057
Short name T583
Test name
Test status
Simulation time 12071678 ps
CPU time 0.64 seconds
Started Jan 24 05:57:45 PM PST 24
Finished Jan 24 05:57:46 PM PST 24
Peak memory 200736 kb
Host smart-a07df953-f8bf-419c-8178-d8283ef48cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583207057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.3583207057
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.2591111370
Short name T823
Test name
Test status
Simulation time 13940246009 ps
CPU time 76.61 seconds
Started Jan 24 05:56:50 PM PST 24
Finished Jan 24 05:58:07 PM PST 24
Peak memory 201800 kb
Host smart-dfacd290-6c61-4d08-804f-f05f9b5ddbb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591111370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.2591111370
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.3883960911
Short name T891
Test name
Test status
Simulation time 5894009491 ps
CPU time 713.7 seconds
Started Jan 24 06:08:45 PM PST 24
Finished Jan 24 06:20:40 PM PST 24
Peak memory 366384 kb
Host smart-8366a9d0-5dbd-430e-aee0-8ec9839bd4dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883960911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.3883960911
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.2882885308
Short name T349
Test name
Test status
Simulation time 1414843728 ps
CPU time 5.14 seconds
Started Jan 24 06:10:45 PM PST 24
Finished Jan 24 06:10:50 PM PST 24
Peak memory 201792 kb
Host smart-8ea1508a-6fb7-4253-a1d6-d01d73c21df7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882885308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.2882885308
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.3782978
Short name T640
Test name
Test status
Simulation time 299897800 ps
CPU time 10.8 seconds
Started Jan 24 06:08:46 PM PST 24
Finished Jan 24 06:08:57 PM PST 24
Peak memory 250428 kb
Host smart-0e442238-0770-4280-b793-616ab07bbe75
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base
_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.sram_ctrl_max_throughput.3782978
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.4268265182
Short name T932
Test name
Test status
Simulation time 152547903 ps
CPU time 5.52 seconds
Started Jan 24 05:57:16 PM PST 24
Finished Jan 24 05:57:22 PM PST 24
Peak memory 210028 kb
Host smart-202d69da-361d-458a-90dc-f64e40014d40
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268265182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.4268265182
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.976873293
Short name T133
Test name
Test status
Simulation time 466089718 ps
CPU time 5.1 seconds
Started Jan 24 05:57:03 PM PST 24
Finished Jan 24 05:57:09 PM PST 24
Peak memory 201964 kb
Host smart-172ce26f-5014-46a3-9f45-f39ea037d3e5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976873293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl
_mem_walk.976873293
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.35068655
Short name T900
Test name
Test status
Simulation time 4392180142 ps
CPU time 904.75 seconds
Started Jan 24 06:23:56 PM PST 24
Finished Jan 24 06:39:02 PM PST 24
Peak memory 368160 kb
Host smart-2a469a44-7978-41da-9954-0de0015ae39a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35068655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multipl
e_keys.35068655
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.2398212683
Short name T299
Test name
Test status
Simulation time 2362725495 ps
CPU time 19 seconds
Started Jan 24 07:26:48 PM PST 24
Finished Jan 24 07:27:08 PM PST 24
Peak memory 201856 kb
Host smart-3c2ab192-1ada-45b8-86f2-db38f9dbbfda
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398212683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.2398212683
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3131096666
Short name T89
Test name
Test status
Simulation time 9259439885 ps
CPU time 371.41 seconds
Started Jan 24 05:56:49 PM PST 24
Finished Jan 24 06:03:01 PM PST 24
Peak memory 201940 kb
Host smart-3c1f2345-51a7-4f88-8538-fce9bf2b2a2e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131096666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.3131096666
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.2602022459
Short name T374
Test name
Test status
Simulation time 92328025 ps
CPU time 0.82 seconds
Started Jan 24 05:57:02 PM PST 24
Finished Jan 24 05:57:03 PM PST 24
Peak memory 202012 kb
Host smart-1d681fb0-cf3c-43eb-8325-dbb7ae0c27d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602022459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2602022459
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.1699418561
Short name T500
Test name
Test status
Simulation time 2355827723 ps
CPU time 755.81 seconds
Started Jan 24 06:23:04 PM PST 24
Finished Jan 24 06:35:41 PM PST 24
Peak memory 362192 kb
Host smart-baa83620-d27b-4033-8d8b-a370516e4b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699418561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1699418561
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.1169167294
Short name T368
Test name
Test status
Simulation time 29601004 ps
CPU time 1.01 seconds
Started Jan 24 05:56:44 PM PST 24
Finished Jan 24 05:56:45 PM PST 24
Peak memory 201620 kb
Host smart-7c53f1aa-2e74-4fcf-b31a-0c9fc3f48c4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169167294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1169167294
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3379336031
Short name T683
Test name
Test status
Simulation time 1436926227 ps
CPU time 4305.73 seconds
Started Jan 24 05:57:45 PM PST 24
Finished Jan 24 07:09:32 PM PST 24
Peak memory 401976 kb
Host smart-f8f317dd-8298-4d11-bf6b-86bf5a8cf2cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3379336031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3379336031
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1875996002
Short name T771
Test name
Test status
Simulation time 6243948066 ps
CPU time 148.3 seconds
Started Jan 24 05:56:53 PM PST 24
Finished Jan 24 05:59:22 PM PST 24
Peak memory 201916 kb
Host smart-69d18367-5068-40b8-8d00-74000792e3d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875996002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.1875996002
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1557259459
Short name T546
Test name
Test status
Simulation time 479966137 ps
CPU time 78.1 seconds
Started Jan 24 05:56:59 PM PST 24
Finished Jan 24 05:58:17 PM PST 24
Peak memory 324532 kb
Host smart-56ccb724-f169-4b7c-a8e8-ef92de5dfd8a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557259459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.1557259459
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3563404429
Short name T591
Test name
Test status
Simulation time 10450974955 ps
CPU time 1032.36 seconds
Started Jan 24 07:08:33 PM PST 24
Finished Jan 24 07:25:50 PM PST 24
Peak memory 368648 kb
Host smart-02e638d3-0ad1-4cba-bef1-dbc090a40c74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563404429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.3563404429
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.886753211
Short name T351
Test name
Test status
Simulation time 12963098 ps
CPU time 0.63 seconds
Started Jan 24 05:58:54 PM PST 24
Finished Jan 24 05:58:55 PM PST 24
Peak memory 200764 kb
Host smart-9f484857-9028-4bab-90c7-96a5b7e2d286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886753211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.886753211
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.2355852644
Short name T461
Test name
Test status
Simulation time 17479892435 ps
CPU time 85.13 seconds
Started Jan 24 05:58:13 PM PST 24
Finished Jan 24 05:59:42 PM PST 24
Peak memory 201848 kb
Host smart-653b302c-9113-4432-8c15-c8cac71a2e0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355852644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.2355852644
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.3041349087
Short name T836
Test name
Test status
Simulation time 4928346623 ps
CPU time 1303.93 seconds
Started Jan 24 05:58:19 PM PST 24
Finished Jan 24 06:20:06 PM PST 24
Peak memory 373764 kb
Host smart-cc394eb9-5b28-444e-b4f7-624fc7eb256e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041349087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.3041349087
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.1518762452
Short name T845
Test name
Test status
Simulation time 752474479 ps
CPU time 5.61 seconds
Started Jan 24 05:58:20 PM PST 24
Finished Jan 24 05:58:28 PM PST 24
Peak memory 210084 kb
Host smart-a5dfb122-f2c8-41c6-96f7-1ba67e74f1fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518762452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.1518762452
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.3573725416
Short name T37
Test name
Test status
Simulation time 97807661 ps
CPU time 4.61 seconds
Started Jan 24 05:58:17 PM PST 24
Finished Jan 24 05:58:24 PM PST 24
Peak memory 219548 kb
Host smart-2d1eeb5f-83b7-4323-bc7a-29660f05f1a0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573725416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.3573725416
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.249865509
Short name T702
Test name
Test status
Simulation time 184966936 ps
CPU time 2.96 seconds
Started Jan 24 07:01:06 PM PST 24
Finished Jan 24 07:01:16 PM PST 24
Peak memory 210172 kb
Host smart-1acf6b50-1069-405d-ae31-57ea8d8c97a3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249865509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_mem_partial_access.249865509
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.736965310
Short name T980
Test name
Test status
Simulation time 3137706599 ps
CPU time 10.92 seconds
Started Jan 24 05:58:21 PM PST 24
Finished Jan 24 05:58:33 PM PST 24
Peak memory 202012 kb
Host smart-05a2bf1a-f93c-4a16-a39e-6a33a41f5061
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736965310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl
_mem_walk.736965310
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.3822180658
Short name T562
Test name
Test status
Simulation time 10645877235 ps
CPU time 345.02 seconds
Started Jan 24 05:58:11 PM PST 24
Finished Jan 24 06:03:57 PM PST 24
Peak memory 317844 kb
Host smart-8456bd55-a589-4565-917a-17623971d335
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822180658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.3822180658
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.3084108285
Short name T976
Test name
Test status
Simulation time 196555050 ps
CPU time 11.4 seconds
Started Jan 24 05:58:11 PM PST 24
Finished Jan 24 05:58:24 PM PST 24
Peak memory 237276 kb
Host smart-4f6e88bf-4474-474f-96d8-a449ab8be771
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084108285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.3084108285
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.178890276
Short name T90
Test name
Test status
Simulation time 77277014242 ps
CPU time 440.04 seconds
Started Jan 24 05:58:14 PM PST 24
Finished Jan 24 06:05:37 PM PST 24
Peak memory 201880 kb
Host smart-8b8f1025-1045-4c6c-8eb3-42fee7819209
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178890276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.sram_ctrl_partial_access_b2b.178890276
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.3393665252
Short name T844
Test name
Test status
Simulation time 51346651 ps
CPU time 0.87 seconds
Started Jan 24 06:44:29 PM PST 24
Finished Jan 24 06:44:31 PM PST 24
Peak memory 201856 kb
Host smart-fa5f887e-2152-45aa-99d5-ea855d9c650d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393665252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3393665252
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.1811420982
Short name T328
Test name
Test status
Simulation time 62392717247 ps
CPU time 1025.58 seconds
Started Jan 24 05:58:19 PM PST 24
Finished Jan 24 06:15:28 PM PST 24
Peak memory 358328 kb
Host smart-cb06b309-3ee1-42fe-ade7-472f2cbadaf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811420982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1811420982
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.3694374968
Short name T627
Test name
Test status
Simulation time 1034043115 ps
CPU time 74.21 seconds
Started Jan 24 05:57:44 PM PST 24
Finished Jan 24 05:58:59 PM PST 24
Peak memory 313144 kb
Host smart-af9e548a-bc13-4a6c-b256-0c753192fbb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694374968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3694374968
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.4056188385
Short name T8
Test name
Test status
Simulation time 109887282649 ps
CPU time 1068.39 seconds
Started Jan 24 05:58:27 PM PST 24
Finished Jan 24 06:16:17 PM PST 24
Peak memory 365360 kb
Host smart-1ee2c442-ca7f-4988-beb4-93d13d888ae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056188385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.sram_ctrl_stress_all.4056188385
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2287470948
Short name T837
Test name
Test status
Simulation time 985614673 ps
CPU time 6462.46 seconds
Started Jan 24 05:58:22 PM PST 24
Finished Jan 24 07:46:06 PM PST 24
Peak memory 431460 kb
Host smart-eac8756f-a408-4c5a-98b9-c9ff1ff2dc15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2287470948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2287470948
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.4048678149
Short name T822
Test name
Test status
Simulation time 9513478530 ps
CPU time 249.84 seconds
Started Jan 24 05:58:11 PM PST 24
Finished Jan 24 06:02:22 PM PST 24
Peak memory 201928 kb
Host smart-c8cd5df6-3b1b-47eb-8259-df07a6c3cd54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048678149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.4048678149
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4255087234
Short name T777
Test name
Test status
Simulation time 433007446 ps
CPU time 22.06 seconds
Started Jan 24 05:58:17 PM PST 24
Finished Jan 24 05:58:42 PM PST 24
Peak memory 273288 kb
Host smart-3ed4db7c-452c-416b-904a-0cc2418f6b36
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255087234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.4255087234
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.4155201238
Short name T528
Test name
Test status
Simulation time 9648059686 ps
CPU time 707.33 seconds
Started Jan 24 07:06:25 PM PST 24
Finished Jan 24 07:18:23 PM PST 24
Peak memory 371712 kb
Host smart-f26c1e00-c0aa-4d32-a68d-4bad0d7e5f2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155201238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.4155201238
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.1977694650
Short name T411
Test name
Test status
Simulation time 29108627 ps
CPU time 0.67 seconds
Started Jan 24 06:14:24 PM PST 24
Finished Jan 24 06:14:26 PM PST 24
Peak memory 201704 kb
Host smart-1dece40d-e02a-40f3-8932-e1e47faa2eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977694650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.1977694650
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.177617057
Short name T261
Test name
Test status
Simulation time 5223065628 ps
CPU time 59.59 seconds
Started Jan 24 06:09:39 PM PST 24
Finished Jan 24 06:10:39 PM PST 24
Peak memory 201964 kb
Host smart-c2581a31-5486-426f-bcde-6466477dc753
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177617057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.
177617057
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.3422580374
Short name T966
Test name
Test status
Simulation time 46186558998 ps
CPU time 1203.9 seconds
Started Jan 24 06:10:43 PM PST 24
Finished Jan 24 06:30:48 PM PST 24
Peak memory 366444 kb
Host smart-4b13ae2c-32f8-4e84-94dc-41f750ee16c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422580374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.3422580374
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.2453052450
Short name T524
Test name
Test status
Simulation time 1162241515 ps
CPU time 1.87 seconds
Started Jan 24 05:59:27 PM PST 24
Finished Jan 24 05:59:30 PM PST 24
Peak memory 210108 kb
Host smart-01a25b0e-0ad8-4cc7-99d2-829988acb8f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453052450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.2453052450
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.2246678707
Short name T769
Test name
Test status
Simulation time 126676061 ps
CPU time 135.79 seconds
Started Jan 24 05:59:27 PM PST 24
Finished Jan 24 06:01:43 PM PST 24
Peak memory 348772 kb
Host smart-a1c293a5-3143-45f2-bd2b-574d1f1c985f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246678707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.2246678707
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1327664663
Short name T672
Test name
Test status
Simulation time 171983002 ps
CPU time 3.13 seconds
Started Jan 24 05:59:32 PM PST 24
Finished Jan 24 05:59:35 PM PST 24
Peak memory 214964 kb
Host smart-f569d56c-db60-4870-8af1-890050e5d168
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327664663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.1327664663
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.2394317477
Short name T242
Test name
Test status
Simulation time 619151123 ps
CPU time 8.02 seconds
Started Jan 24 06:11:28 PM PST 24
Finished Jan 24 06:11:37 PM PST 24
Peak memory 201928 kb
Host smart-d8ff74b5-b677-4b5c-b6b2-2de5ee184d2c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394317477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.2394317477
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.3396516820
Short name T255
Test name
Test status
Simulation time 14011624891 ps
CPU time 2265.12 seconds
Started Jan 24 05:58:58 PM PST 24
Finished Jan 24 06:36:44 PM PST 24
Peak memory 373772 kb
Host smart-4ddbe375-420d-4085-ae3e-a8021fa3a222
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396516820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.3396516820
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.2621707364
Short name T331
Test name
Test status
Simulation time 4684770192 ps
CPU time 19.69 seconds
Started Jan 24 05:58:57 PM PST 24
Finished Jan 24 05:59:18 PM PST 24
Peak memory 201892 kb
Host smart-4367c1b4-76ba-4d5d-8343-fe02e9e42e67
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621707364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.2621707364
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2824992629
Short name T232
Test name
Test status
Simulation time 5694134139 ps
CPU time 393.97 seconds
Started Jan 24 05:58:57 PM PST 24
Finished Jan 24 06:05:32 PM PST 24
Peak memory 201828 kb
Host smart-201ee7ee-080a-49a7-b271-ac263d9cba9f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824992629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.2824992629
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.2068869098
Short name T662
Test name
Test status
Simulation time 30802333 ps
CPU time 0.9 seconds
Started Jan 24 05:59:29 PM PST 24
Finished Jan 24 05:59:31 PM PST 24
Peak memory 201904 kb
Host smart-89faa0fe-9c69-42bc-9eda-40cd57fabb8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068869098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2068869098
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.858626189
Short name T716
Test name
Test status
Simulation time 4048558299 ps
CPU time 224.91 seconds
Started Jan 24 05:59:27 PM PST 24
Finished Jan 24 06:03:12 PM PST 24
Peak memory 327432 kb
Host smart-4ae2fe82-7a9d-4fe0-90c9-254ae11b0fc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858626189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.858626189
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.3493995174
Short name T602
Test name
Test status
Simulation time 959002501 ps
CPU time 8.42 seconds
Started Jan 24 05:58:55 PM PST 24
Finished Jan 24 05:59:04 PM PST 24
Peak memory 201852 kb
Host smart-595fd606-2c5c-4553-9d30-31dae4c76d07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493995174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3493995174
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.1770045687
Short name T449
Test name
Test status
Simulation time 106333656591 ps
CPU time 2255.16 seconds
Started Jan 24 05:59:34 PM PST 24
Finished Jan 24 06:37:10 PM PST 24
Peak memory 373784 kb
Host smart-b89e2882-68f2-4169-8337-f57c652e0013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770045687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.1770045687
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2100316024
Short name T350
Test name
Test status
Simulation time 5048171746 ps
CPU time 3674.47 seconds
Started Jan 24 06:16:42 PM PST 24
Finished Jan 24 07:17:57 PM PST 24
Peak memory 418980 kb
Host smart-1fdeb949-0823-4ac4-b0bb-9b466359ef45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2100316024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2100316024
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3226477942
Short name T639
Test name
Test status
Simulation time 13575066950 ps
CPU time 310.85 seconds
Started Jan 24 05:58:57 PM PST 24
Finished Jan 24 06:04:09 PM PST 24
Peak memory 201964 kb
Host smart-11217052-75f3-4a6e-871e-18ddbc22192e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226477942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.3226477942
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.4138125022
Short name T803
Test name
Test status
Simulation time 130168358 ps
CPU time 79.63 seconds
Started Jan 24 05:59:29 PM PST 24
Finished Jan 24 06:00:49 PM PST 24
Peak memory 324624 kb
Host smart-aec9eaad-0ce1-4c41-86c0-9070471be2a9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138125022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.4138125022
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.898349409
Short name T574
Test name
Test status
Simulation time 4227753995 ps
CPU time 1201.62 seconds
Started Jan 24 06:00:25 PM PST 24
Finished Jan 24 06:20:29 PM PST 24
Peak memory 372644 kb
Host smart-6c693b93-2388-41b1-84e9-4fd400d0e14f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898349409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.sram_ctrl_access_during_key_req.898349409
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.183080390
Short name T482
Test name
Test status
Simulation time 13500630 ps
CPU time 0.65 seconds
Started Jan 24 06:01:36 PM PST 24
Finished Jan 24 06:01:37 PM PST 24
Peak memory 201680 kb
Host smart-f7dfe2a5-6c14-43f9-9e06-114c7a37e9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183080390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.183080390
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.310017678
Short name T969
Test name
Test status
Simulation time 3969307252 ps
CPU time 17.35 seconds
Started Jan 24 05:59:45 PM PST 24
Finished Jan 24 06:00:03 PM PST 24
Peak memory 201928 kb
Host smart-6d5c50a6-7726-4694-84e5-dadcc5763a1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310017678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.
310017678
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.3572067148
Short name T730
Test name
Test status
Simulation time 16747732488 ps
CPU time 1201.08 seconds
Started Jan 24 06:00:32 PM PST 24
Finished Jan 24 06:20:34 PM PST 24
Peak memory 372660 kb
Host smart-2a05edec-13d4-48bb-9242-d81b732a7032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572067148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.3572067148
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.2592868061
Short name T367
Test name
Test status
Simulation time 718001744 ps
CPU time 9.16 seconds
Started Jan 24 06:34:03 PM PST 24
Finished Jan 24 06:34:13 PM PST 24
Peak memory 201860 kb
Host smart-066d521c-e229-412c-9ef0-5c2cac13a3c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592868061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.2592868061
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2344781542
Short name T512
Test name
Test status
Simulation time 89748972 ps
CPU time 4.75 seconds
Started Jan 24 06:00:50 PM PST 24
Finished Jan 24 06:00:57 PM PST 24
Peak memory 211236 kb
Host smart-b4b1adac-b9bb-448c-9235-eb0ede160b84
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344781542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.2344781542
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2050227492
Short name T686
Test name
Test status
Simulation time 904782125 ps
CPU time 9.04 seconds
Started Jan 24 06:00:51 PM PST 24
Finished Jan 24 06:01:01 PM PST 24
Peak memory 201916 kb
Host smart-d9808e50-07c3-4518-9d12-80147bbd1ea6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050227492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2050227492
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.2633353504
Short name T110
Test name
Test status
Simulation time 12547158628 ps
CPU time 923.7 seconds
Started Jan 24 05:59:39 PM PST 24
Finished Jan 24 06:15:03 PM PST 24
Peak memory 372612 kb
Host smart-c986d3fb-6046-46ae-98f1-26059300cfef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633353504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.2633353504
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.4140256057
Short name T899
Test name
Test status
Simulation time 1941317592 ps
CPU time 6.04 seconds
Started Jan 24 05:59:47 PM PST 24
Finished Jan 24 05:59:54 PM PST 24
Peak memory 201868 kb
Host smart-2cf302b1-104f-4b59-b4c9-7aa61438b1a7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140256057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.4140256057
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2235354962
Short name T13
Test name
Test status
Simulation time 36697283834 ps
CPU time 223.49 seconds
Started Jan 24 06:08:00 PM PST 24
Finished Jan 24 06:11:46 PM PST 24
Peak memory 201940 kb
Host smart-6db6c47c-18e3-4085-9879-fd52d4480b25
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235354962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.2235354962
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.148060273
Short name T245
Test name
Test status
Simulation time 28835584 ps
CPU time 1.07 seconds
Started Jan 24 06:51:11 PM PST 24
Finished Jan 24 06:51:12 PM PST 24
Peak memory 202224 kb
Host smart-ee26cd2c-cde2-4acc-93cb-7796088d701f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148060273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.148060273
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.2051322981
Short name T620
Test name
Test status
Simulation time 60121613379 ps
CPU time 1442.42 seconds
Started Jan 24 08:30:08 PM PST 24
Finished Jan 24 08:54:11 PM PST 24
Peak memory 373736 kb
Host smart-0acbf15a-09e7-49e0-85f6-f3c64c2c87ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051322981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2051322981
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.611235437
Short name T111
Test name
Test status
Simulation time 228218565 ps
CPU time 14.69 seconds
Started Jan 24 05:59:36 PM PST 24
Finished Jan 24 05:59:51 PM PST 24
Peak memory 201704 kb
Host smart-f71648af-5080-4ef6-869c-0ec9b1c4168d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611235437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.611235437
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.3834893116
Short name T921
Test name
Test status
Simulation time 37760835961 ps
CPU time 1300.38 seconds
Started Jan 24 06:05:40 PM PST 24
Finished Jan 24 06:27:21 PM PST 24
Peak memory 382900 kb
Host smart-177ce2ec-e76b-4bc7-affc-b6c06a4b8bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834893116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.sram_ctrl_stress_all.3834893116
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3144768948
Short name T396
Test name
Test status
Simulation time 1267846977 ps
CPU time 3515.64 seconds
Started Jan 24 06:01:17 PM PST 24
Finished Jan 24 06:59:53 PM PST 24
Peak memory 418744 kb
Host smart-2e68e62f-fd04-41ce-a3b7-3178180d70d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3144768948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3144768948
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.997907686
Short name T478
Test name
Test status
Simulation time 2979899989 ps
CPU time 290.24 seconds
Started Jan 24 05:59:39 PM PST 24
Finished Jan 24 06:04:30 PM PST 24
Peak memory 201948 kb
Host smart-ca150fe3-848a-4db5-a4ca-f0fb1ab6830a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997907686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_stress_pipeline.997907686
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.623439328
Short name T564
Test name
Test status
Simulation time 468326682 ps
CPU time 21.95 seconds
Started Jan 24 07:31:08 PM PST 24
Finished Jan 24 07:31:34 PM PST 24
Peak memory 274880 kb
Host smart-98d0b075-f032-4dbc-a2cc-8155337fae2f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623439328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.623439328
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3237793735
Short name T487
Test name
Test status
Simulation time 6064097099 ps
CPU time 1397.45 seconds
Started Jan 24 05:44:56 PM PST 24
Finished Jan 24 06:08:14 PM PST 24
Peak memory 373676 kb
Host smart-2e57ad19-4742-4ae1-acb0-bdf36d8b8022
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237793735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.3237793735
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.1745066558
Short name T767
Test name
Test status
Simulation time 16190757 ps
CPU time 0.64 seconds
Started Jan 24 05:45:34 PM PST 24
Finished Jan 24 05:45:40 PM PST 24
Peak memory 201616 kb
Host smart-796ed8e1-7aa5-473c-b34e-7cd2637696df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745066558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.1745066558
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.4278895890
Short name T268
Test name
Test status
Simulation time 8375529169 ps
CPU time 81.08 seconds
Started Jan 24 07:13:31 PM PST 24
Finished Jan 24 07:14:53 PM PST 24
Peak memory 201892 kb
Host smart-978aea28-ecaa-4eb0-aba7-cf2237c6a736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278895890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
4278895890
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.1041597314
Short name T697
Test name
Test status
Simulation time 7520610024 ps
CPU time 28.95 seconds
Started Jan 24 05:44:57 PM PST 24
Finished Jan 24 05:45:27 PM PST 24
Peak memory 201944 kb
Host smart-fdbb6ccc-1f75-43ae-ac47-40da7467e7e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041597314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.1041597314
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.3109794857
Short name T675
Test name
Test status
Simulation time 1058277863 ps
CPU time 54.95 seconds
Started Jan 24 05:44:56 PM PST 24
Finished Jan 24 05:45:52 PM PST 24
Peak memory 290344 kb
Host smart-764a1fd0-5041-4eb8-a7fa-3fc4632676fa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109794857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.3109794857
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2247083011
Short name T486
Test name
Test status
Simulation time 328254597 ps
CPU time 2.92 seconds
Started Jan 24 08:53:45 PM PST 24
Finished Jan 24 08:53:49 PM PST 24
Peak memory 210152 kb
Host smart-ed770753-1de9-4076-b2da-e01859d52eae
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247083011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.2247083011
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.3640213361
Short name T858
Test name
Test status
Simulation time 135492751 ps
CPU time 7.99 seconds
Started Jan 24 05:52:47 PM PST 24
Finished Jan 24 05:53:01 PM PST 24
Peak memory 201948 kb
Host smart-f20b994f-ebf9-400a-8186-5e5f49b8924a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640213361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.3640213361
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.2039686908
Short name T978
Test name
Test status
Simulation time 2472411464 ps
CPU time 499.66 seconds
Started Jan 24 05:43:58 PM PST 24
Finished Jan 24 05:52:19 PM PST 24
Peak memory 359076 kb
Host smart-52daa769-2962-49f9-96b2-e3480fc23776
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039686908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.2039686908
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.2963017118
Short name T433
Test name
Test status
Simulation time 553259040 ps
CPU time 91.21 seconds
Started Jan 24 06:54:00 PM PST 24
Finished Jan 24 06:55:35 PM PST 24
Peak memory 328244 kb
Host smart-77057736-4e8a-4831-9955-047b56b04444
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963017118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.2963017118
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.21181870
Short name T441
Test name
Test status
Simulation time 4485957627 ps
CPU time 326.17 seconds
Started Jan 24 05:44:56 PM PST 24
Finished Jan 24 05:50:23 PM PST 24
Peak memory 201900 kb
Host smart-29cb3885-673d-428b-b539-4d1595942cbe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21181870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_partial_access_b2b.21181870
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.172937181
Short name T703
Test name
Test status
Simulation time 48383360 ps
CPU time 0.83 seconds
Started Jan 24 05:45:28 PM PST 24
Finished Jan 24 05:45:30 PM PST 24
Peak memory 201972 kb
Host smart-dff2095b-6df2-469d-ac8a-adc849b18c26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172937181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.172937181
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.2046479123
Short name T847
Test name
Test status
Simulation time 7210165752 ps
CPU time 1303.88 seconds
Started Jan 24 05:45:24 PM PST 24
Finished Jan 24 06:07:12 PM PST 24
Peak memory 367400 kb
Host smart-8fe98671-3a88-403c-b3cc-25958b64dc5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046479123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2046479123
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.802503253
Short name T33
Test name
Test status
Simulation time 562265881 ps
CPU time 2.78 seconds
Started Jan 24 05:45:33 PM PST 24
Finished Jan 24 05:45:37 PM PST 24
Peak memory 220316 kb
Host smart-fcdd7f39-8b71-4d15-9d03-06698d2f0741
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802503253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_sec_cm.802503253
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.3368984173
Short name T134
Test name
Test status
Simulation time 714309922 ps
CPU time 15.6 seconds
Started Jan 24 05:43:53 PM PST 24
Finished Jan 24 05:44:09 PM PST 24
Peak memory 201680 kb
Host smart-db7df9cc-249f-402c-8c9a-a22fedcba07f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368984173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3368984173
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1033428458
Short name T679
Test name
Test status
Simulation time 3158328672 ps
CPU time 1958.46 seconds
Started Jan 24 05:45:33 PM PST 24
Finished Jan 24 06:18:17 PM PST 24
Peak memory 414496 kb
Host smart-da752c74-fc2a-4500-a187-35489d12242c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1033428458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1033428458
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.531605891
Short name T271
Test name
Test status
Simulation time 17844443876 ps
CPU time 207.89 seconds
Started Jan 24 07:33:53 PM PST 24
Finished Jan 24 07:37:22 PM PST 24
Peak memory 201996 kb
Host smart-e6bfafb2-24a9-4645-a7f4-d7af754ae779
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531605891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_stress_pipeline.531605891
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3902754268
Short name T811
Test name
Test status
Simulation time 193082236 ps
CPU time 82.18 seconds
Started Jan 24 05:44:56 PM PST 24
Finished Jan 24 05:46:19 PM PST 24
Peak memory 327496 kb
Host smart-eb513d6c-f523-4f6a-84e1-5ebd83dd0bb3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902754268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3902754268
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.474398750
Short name T794
Test name
Test status
Simulation time 971913352 ps
CPU time 317.14 seconds
Started Jan 24 06:02:54 PM PST 24
Finished Jan 24 06:08:12 PM PST 24
Peak memory 359848 kb
Host smart-c6084ed4-81a6-4de0-a229-df8931ec5478
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474398750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 20.sram_ctrl_access_during_key_req.474398750
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.337261939
Short name T24
Test name
Test status
Simulation time 21342601 ps
CPU time 0.7 seconds
Started Jan 24 06:39:27 PM PST 24
Finished Jan 24 06:39:28 PM PST 24
Peak memory 200772 kb
Host smart-7b043aea-f294-464e-aac3-41f07660b403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337261939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.337261939
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.2538352165
Short name T815
Test name
Test status
Simulation time 1106320055 ps
CPU time 68.83 seconds
Started Jan 24 06:02:10 PM PST 24
Finished Jan 24 06:03:20 PM PST 24
Peak memory 201864 kb
Host smart-9624e4ad-2c23-4b80-a11c-065ea688ee68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538352165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.2538352165
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.29349281
Short name T285
Test name
Test status
Simulation time 2173842220 ps
CPU time 867.92 seconds
Started Jan 24 07:53:12 PM PST 24
Finished Jan 24 08:07:41 PM PST 24
Peak memory 367580 kb
Host smart-710e1c38-8040-4ba2-b7e9-f8f0dd736088
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29349281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable
.29349281
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.391904386
Short name T530
Test name
Test status
Simulation time 220120789 ps
CPU time 2.87 seconds
Started Jan 24 06:02:53 PM PST 24
Finished Jan 24 06:02:57 PM PST 24
Peak memory 209840 kb
Host smart-30bf0939-2e1a-40dd-a7c2-fcb42de47beb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391904386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc
alation.391904386
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.1074924150
Short name T438
Test name
Test status
Simulation time 536763399 ps
CPU time 145.29 seconds
Started Jan 24 08:25:58 PM PST 24
Finished Jan 24 08:28:25 PM PST 24
Peak memory 365352 kb
Host smart-8bd849ac-bb48-43de-ba07-1f2f76bc80f4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074924150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.1074924150
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3076732143
Short name T644
Test name
Test status
Simulation time 91196802 ps
CPU time 3.11 seconds
Started Jan 24 06:03:29 PM PST 24
Finished Jan 24 06:03:37 PM PST 24
Peak memory 210096 kb
Host smart-ca987099-a82e-436b-a783-fe4a0fc1412b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076732143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.3076732143
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.2951138458
Short name T798
Test name
Test status
Simulation time 1344794076 ps
CPU time 5.47 seconds
Started Jan 24 06:03:24 PM PST 24
Finished Jan 24 06:03:30 PM PST 24
Peak memory 201944 kb
Host smart-884b2353-8676-48b7-923f-34d262f2d624
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951138458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.2951138458
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.100390180
Short name T770
Test name
Test status
Simulation time 20216656098 ps
CPU time 875.72 seconds
Started Jan 24 06:01:39 PM PST 24
Finished Jan 24 06:16:16 PM PST 24
Peak memory 372592 kb
Host smart-a15479bf-0d7f-4de3-9ce4-8a61a10a10c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100390180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip
le_keys.100390180
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.987744926
Short name T816
Test name
Test status
Simulation time 190800943 ps
CPU time 85.58 seconds
Started Jan 24 06:02:19 PM PST 24
Finished Jan 24 06:03:45 PM PST 24
Peak memory 335784 kb
Host smart-db43292e-fe8e-46a8-8c7d-7bbb934be8f0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987744926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.s
ram_ctrl_partial_access.987744926
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.3636352253
Short name T965
Test name
Test status
Simulation time 31808718 ps
CPU time 0.84 seconds
Started Jan 24 06:03:21 PM PST 24
Finished Jan 24 06:03:23 PM PST 24
Peak memory 201932 kb
Host smart-b5951444-f503-4307-bf17-5791920aa821
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636352253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3636352253
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.862559230
Short name T104
Test name
Test status
Simulation time 27563694302 ps
CPU time 1261.55 seconds
Started Jan 24 06:37:47 PM PST 24
Finished Jan 24 06:58:49 PM PST 24
Peak memory 365440 kb
Host smart-a2ee34ba-0fb3-437d-83f3-bf13efc569ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862559230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.862559230
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.4203732394
Short name T435
Test name
Test status
Simulation time 132616588 ps
CPU time 120.77 seconds
Started Jan 24 06:40:06 PM PST 24
Finished Jan 24 06:42:07 PM PST 24
Peak memory 359976 kb
Host smart-4a733fbf-c4ca-4288-bff6-82ca25b41510
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203732394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4203732394
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.379049680
Short name T711
Test name
Test status
Simulation time 120581357423 ps
CPU time 1463.26 seconds
Started Jan 24 06:04:10 PM PST 24
Finished Jan 24 06:28:34 PM PST 24
Peak memory 370232 kb
Host smart-8ca96bbd-064c-4fe2-b9ee-5e2e446e7075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379049680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_stress_all.379049680
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2289297350
Short name T724
Test name
Test status
Simulation time 3349920653 ps
CPU time 4762.62 seconds
Started Jan 24 06:04:08 PM PST 24
Finished Jan 24 07:23:34 PM PST 24
Peak memory 450496 kb
Host smart-ec903bc5-9e52-406a-887f-1da9bced09bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2289297350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.2289297350
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1951174458
Short name T859
Test name
Test status
Simulation time 6483180629 ps
CPU time 148.83 seconds
Started Jan 24 07:21:29 PM PST 24
Finished Jan 24 07:23:59 PM PST 24
Peak memory 201932 kb
Host smart-5eaf8af0-cff1-46b3-8bd4-feb802f9ad67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951174458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1951174458
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2609101506
Short name T288
Test name
Test status
Simulation time 41169797 ps
CPU time 1.83 seconds
Started Jan 24 06:02:31 PM PST 24
Finished Jan 24 06:02:33 PM PST 24
Peak memory 210060 kb
Host smart-e2a0cb59-6881-4ed1-892b-a76cd15e8551
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609101506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.2609101506
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2791133943
Short name T538
Test name
Test status
Simulation time 16306235897 ps
CPU time 1301.56 seconds
Started Jan 24 06:05:08 PM PST 24
Finished Jan 24 06:26:51 PM PST 24
Peak memory 372640 kb
Host smart-c22bf8b6-5d9c-4fb5-be74-f282493ac66b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791133943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.2791133943
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.3203572871
Short name T919
Test name
Test status
Simulation time 13477426 ps
CPU time 0.65 seconds
Started Jan 24 06:06:13 PM PST 24
Finished Jan 24 06:06:15 PM PST 24
Peak memory 201636 kb
Host smart-bdca22df-b5d1-432c-9d48-ebe34d0a1daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203572871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.3203572871
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.1130349612
Short name T621
Test name
Test status
Simulation time 5074642730 ps
CPU time 53.39 seconds
Started Jan 24 06:45:30 PM PST 24
Finished Jan 24 06:46:24 PM PST 24
Peak memory 201900 kb
Host smart-29c89127-087b-4b7c-8000-7fd3614af9c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130349612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.1130349612
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.543528288
Short name T539
Test name
Test status
Simulation time 22027078999 ps
CPU time 1937.04 seconds
Started Jan 24 06:05:13 PM PST 24
Finished Jan 24 06:37:31 PM PST 24
Peak memory 372688 kb
Host smart-6e3c994d-71dd-42f0-a867-7693f09caa03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543528288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executabl
e.543528288
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.93293273
Short name T881
Test name
Test status
Simulation time 1018466967 ps
CPU time 6.89 seconds
Started Jan 24 07:15:57 PM PST 24
Finished Jan 24 07:16:05 PM PST 24
Peak memory 212680 kb
Host smart-4c155a44-537a-4d04-be68-7d47c9df4430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93293273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esca
lation.93293273
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.3491934906
Short name T208
Test name
Test status
Simulation time 387825904 ps
CPU time 56.45 seconds
Started Jan 24 06:04:56 PM PST 24
Finished Jan 24 06:05:53 PM PST 24
Peak memory 299940 kb
Host smart-c962c7e8-ac91-4ff9-be81-aefb6dcedf0e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491934906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.3491934906
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3371879214
Short name T72
Test name
Test status
Simulation time 218857619 ps
CPU time 4.72 seconds
Started Jan 24 06:06:13 PM PST 24
Finished Jan 24 06:06:19 PM PST 24
Peak memory 215356 kb
Host smart-61acc6e5-0853-4357-8441-816c4e58375e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371879214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.3371879214
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.623256467
Short name T596
Test name
Test status
Simulation time 5457106290 ps
CPU time 11.39 seconds
Started Jan 24 06:06:09 PM PST 24
Finished Jan 24 06:06:24 PM PST 24
Peak memory 202072 kb
Host smart-75127021-06a2-4f61-9f2c-ff357eb67370
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623256467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl
_mem_walk.623256467
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.1035812114
Short name T915
Test name
Test status
Simulation time 26827347538 ps
CPU time 894.85 seconds
Started Jan 24 06:52:35 PM PST 24
Finished Jan 24 07:07:35 PM PST 24
Peak memory 366508 kb
Host smart-f3905efd-8975-4c72-8963-54f7792fa18a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035812114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.1035812114
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.4003822948
Short name T465
Test name
Test status
Simulation time 933626225 ps
CPU time 12.99 seconds
Started Jan 24 06:53:02 PM PST 24
Finished Jan 24 06:53:20 PM PST 24
Peak memory 201900 kb
Host smart-deba76ef-0f92-4a29-ad2d-7aaa8d0d296f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003822948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.4003822948
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2597132014
Short name T720
Test name
Test status
Simulation time 57383257641 ps
CPU time 398.89 seconds
Started Jan 24 06:05:00 PM PST 24
Finished Jan 24 06:11:41 PM PST 24
Peak memory 201892 kb
Host smart-6d03cc12-9bc2-48d1-85bb-e50fb6f3d55d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597132014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.2597132014
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.2904668721
Short name T912
Test name
Test status
Simulation time 25659030 ps
CPU time 0.88 seconds
Started Jan 24 06:06:09 PM PST 24
Finished Jan 24 06:06:13 PM PST 24
Peak memory 201980 kb
Host smart-efa1ade6-9f03-46e8-9551-16eba0702f0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904668721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2904668721
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.1809965965
Short name T282
Test name
Test status
Simulation time 18632859355 ps
CPU time 1032.14 seconds
Started Jan 24 06:05:13 PM PST 24
Finished Jan 24 06:22:26 PM PST 24
Peak memory 373200 kb
Host smart-35547bf6-a416-4318-969d-8fb2abff2305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809965965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1809965965
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.2357992869
Short name T659
Test name
Test status
Simulation time 3564487970 ps
CPU time 51.29 seconds
Started Jan 24 06:04:12 PM PST 24
Finished Jan 24 06:05:04 PM PST 24
Peak memory 308872 kb
Host smart-05aa7e63-218e-4bcc-a44f-5b107463ae1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357992869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2357992869
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.173034317
Short name T460
Test name
Test status
Simulation time 14357327305 ps
CPU time 1944.76 seconds
Started Jan 24 06:05:51 PM PST 24
Finished Jan 24 06:38:16 PM PST 24
Peak memory 373772 kb
Host smart-600603bb-4357-4d7c-bb63-f9eceeeac0b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173034317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_stress_all.173034317
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.601925313
Short name T353
Test name
Test status
Simulation time 5798469511 ps
CPU time 5719.5 seconds
Started Jan 24 06:06:13 PM PST 24
Finished Jan 24 07:41:35 PM PST 24
Peak memory 449536 kb
Host smart-e4695757-249c-400b-853f-c9a17945a2e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=601925313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.601925313
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3289721095
Short name T332
Test name
Test status
Simulation time 6934249545 ps
CPU time 345.61 seconds
Started Jan 24 06:37:50 PM PST 24
Finished Jan 24 06:43:36 PM PST 24
Peak memory 201908 kb
Host smart-bc898eda-0614-4c47-807d-29864a095faa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289721095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.3289721095
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.440398800
Short name T414
Test name
Test status
Simulation time 108774787 ps
CPU time 5.25 seconds
Started Jan 24 06:05:06 PM PST 24
Finished Jan 24 06:05:12 PM PST 24
Peak memory 223444 kb
Host smart-b7d2926e-b31c-41e0-b477-49f4da1ec7ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440398800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.440398800
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.4262878381
Short name T756
Test name
Test status
Simulation time 1061880315 ps
CPU time 231.33 seconds
Started Jan 24 07:50:39 PM PST 24
Finished Jan 24 07:54:31 PM PST 24
Peak memory 369548 kb
Host smart-c4c3a960-5faa-4dde-bc67-505276e9bf74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262878381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.4262878381
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.1268528977
Short name T928
Test name
Test status
Simulation time 16271460 ps
CPU time 0.68 seconds
Started Jan 24 06:12:24 PM PST 24
Finished Jan 24 06:12:25 PM PST 24
Peak memory 201704 kb
Host smart-0ebb8ed2-a3f3-4000-920b-c158d8470885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268528977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.1268528977
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.1357444299
Short name T935
Test name
Test status
Simulation time 374095930 ps
CPU time 20.07 seconds
Started Jan 24 06:06:20 PM PST 24
Finished Jan 24 06:06:40 PM PST 24
Peak memory 201784 kb
Host smart-f0a0ad88-1638-4e71-8a74-0cb4df15e682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357444299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.1357444299
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.2024304177
Short name T542
Test name
Test status
Simulation time 33175841238 ps
CPU time 1490.98 seconds
Started Jan 24 07:00:20 PM PST 24
Finished Jan 24 07:25:14 PM PST 24
Peak memory 367568 kb
Host smart-ed5ef7fe-6f58-47f0-bbe4-faf8f0229cf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024304177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab
le.2024304177
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.147725426
Short name T290
Test name
Test status
Simulation time 1339692307 ps
CPU time 5.58 seconds
Started Jan 24 06:27:00 PM PST 24
Finished Jan 24 06:27:06 PM PST 24
Peak memory 210072 kb
Host smart-b93bb6d2-068f-4475-a2a3-e6feb2a8fcd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147725426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc
alation.147725426
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.810436547
Short name T723
Test name
Test status
Simulation time 252796924 ps
CPU time 126.73 seconds
Started Jan 24 06:22:40 PM PST 24
Finished Jan 24 06:24:47 PM PST 24
Peak memory 361200 kb
Host smart-64b324e3-c048-431a-83ba-fc1e080ce957
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810436547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.sram_ctrl_max_throughput.810436547
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1939570013
Short name T782
Test name
Test status
Simulation time 304936790 ps
CPU time 5.02 seconds
Started Jan 24 06:06:47 PM PST 24
Finished Jan 24 06:06:53 PM PST 24
Peak memory 210108 kb
Host smart-2857fd3f-a87b-4315-9a78-af4b94939d9e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939570013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.1939570013
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.3817702338
Short name T324
Test name
Test status
Simulation time 1367816427 ps
CPU time 5.67 seconds
Started Jan 24 06:06:46 PM PST 24
Finished Jan 24 06:06:53 PM PST 24
Peak memory 201916 kb
Host smart-a23cdce6-2e33-404b-a496-25589e9ddb0e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817702338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.3817702338
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.1087368576
Short name T532
Test name
Test status
Simulation time 9139850011 ps
CPU time 559.57 seconds
Started Jan 24 06:06:19 PM PST 24
Finished Jan 24 06:15:39 PM PST 24
Peak memory 329400 kb
Host smart-b438d28c-547b-4765-87fd-0280c3846d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087368576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.1087368576
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.4115251528
Short name T853
Test name
Test status
Simulation time 658951520 ps
CPU time 12.12 seconds
Started Jan 24 08:48:57 PM PST 24
Finished Jan 24 08:49:15 PM PST 24
Peak memory 201816 kb
Host smart-8e9cd836-7051-4855-820b-c977cb744ec4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115251528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.4115251528
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.1604845166
Short name T708
Test name
Test status
Simulation time 30609234 ps
CPU time 1.16 seconds
Started Jan 24 06:06:46 PM PST 24
Finished Jan 24 06:06:48 PM PST 24
Peak memory 202196 kb
Host smart-1ddafe26-ee7e-44b4-8f70-d9cf4d500102
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604845166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1604845166
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.3731784189
Short name T544
Test name
Test status
Simulation time 26064702524 ps
CPU time 697.75 seconds
Started Jan 24 06:06:32 PM PST 24
Finished Jan 24 06:18:10 PM PST 24
Peak memory 373200 kb
Host smart-eb194dab-e4cc-44ec-9308-1507e73f51dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731784189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3731784189
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.3159278738
Short name T973
Test name
Test status
Simulation time 493359881 ps
CPU time 65.41 seconds
Started Jan 24 06:06:17 PM PST 24
Finished Jan 24 06:07:23 PM PST 24
Peak memory 322376 kb
Host smart-45e64e3e-65b3-4d22-97d9-a3b71a045109
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159278738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3159278738
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.99485414
Short name T505
Test name
Test status
Simulation time 64875500364 ps
CPU time 2049.37 seconds
Started Jan 24 06:18:31 PM PST 24
Finished Jan 24 06:52:42 PM PST 24
Peak memory 373724 kb
Host smart-0f5fe161-98d0-48ee-b3ed-0ee95f4fc942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99485414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.sram_ctrl_stress_all.99485414
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1128107555
Short name T876
Test name
Test status
Simulation time 1135281336 ps
CPU time 1317.55 seconds
Started Jan 24 06:06:51 PM PST 24
Finished Jan 24 06:28:50 PM PST 24
Peak memory 464900 kb
Host smart-79a102fa-0964-4eaa-b441-dc01c1d2f8b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1128107555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1128107555
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.3368663617
Short name T119
Test name
Test status
Simulation time 15100453865 ps
CPU time 104.92 seconds
Started Jan 24 07:35:22 PM PST 24
Finished Jan 24 07:37:11 PM PST 24
Peak memory 201964 kb
Host smart-6dba7425-ae66-485c-8cf2-f1a1ce35c5ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368663617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.3368663617
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2029128467
Short name T318
Test name
Test status
Simulation time 62357385 ps
CPU time 5.69 seconds
Started Jan 24 06:06:29 PM PST 24
Finished Jan 24 06:06:36 PM PST 24
Peak memory 225324 kb
Host smart-dec9f94b-8ee9-4898-a12e-64cdc4c4b976
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029128467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.2029128467
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.297981776
Short name T469
Test name
Test status
Simulation time 4441816741 ps
CPU time 298.55 seconds
Started Jan 24 06:07:19 PM PST 24
Finished Jan 24 06:12:19 PM PST 24
Peak memory 366068 kb
Host smart-a8f0b1e8-5b9d-44fc-80cc-08a85fbac801
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297981776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.sram_ctrl_access_during_key_req.297981776
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.533411464
Short name T894
Test name
Test status
Simulation time 13183149 ps
CPU time 0.63 seconds
Started Jan 24 07:37:21 PM PST 24
Finished Jan 24 07:37:23 PM PST 24
Peak memory 200776 kb
Host smart-4492fa09-d78f-4a6b-a8d1-ae860a283d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533411464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.533411464
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.3577399893
Short name T468
Test name
Test status
Simulation time 2471896257 ps
CPU time 52.54 seconds
Started Jan 24 06:06:59 PM PST 24
Finished Jan 24 06:07:52 PM PST 24
Peak memory 201904 kb
Host smart-46ce9050-765f-4b8f-ab1b-f246d39c0a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577399893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.3577399893
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.904978935
Short name T933
Test name
Test status
Simulation time 15448720265 ps
CPU time 1306.73 seconds
Started Jan 24 06:07:21 PM PST 24
Finished Jan 24 06:29:09 PM PST 24
Peak memory 367620 kb
Host smart-c72a7984-b46f-4233-854b-f0dc55c6f34f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904978935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executabl
e.904978935
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.1576046106
Short name T920
Test name
Test status
Simulation time 96418987 ps
CPU time 3.73 seconds
Started Jan 24 06:51:25 PM PST 24
Finished Jan 24 06:51:29 PM PST 24
Peak memory 218048 kb
Host smart-defb9334-6979-459a-af26-0c004d1d19ad
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576046106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.1576046106
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2701983617
Short name T747
Test name
Test status
Simulation time 89164429 ps
CPU time 2.95 seconds
Started Jan 24 06:07:53 PM PST 24
Finished Jan 24 06:07:59 PM PST 24
Peak memory 210012 kb
Host smart-5a39100a-e523-4105-a034-a5e02729860f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701983617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.2701983617
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.204528461
Short name T951
Test name
Test status
Simulation time 1382826585 ps
CPU time 5.84 seconds
Started Jan 24 06:07:47 PM PST 24
Finished Jan 24 06:08:00 PM PST 24
Peak memory 201932 kb
Host smart-858c4b63-308a-45af-9ef3-cad7ed6ff599
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204528461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl
_mem_walk.204528461
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.3158784400
Short name T412
Test name
Test status
Simulation time 1691309312 ps
CPU time 87.02 seconds
Started Jan 24 06:06:51 PM PST 24
Finished Jan 24 06:08:19 PM PST 24
Peak memory 316284 kb
Host smart-360bc97e-7028-449c-ae28-e377b97353ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158784400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.3158784400
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.2313211783
Short name T428
Test name
Test status
Simulation time 309756809 ps
CPU time 21.05 seconds
Started Jan 24 06:07:03 PM PST 24
Finished Jan 24 06:07:24 PM PST 24
Peak memory 262276 kb
Host smart-534b2efa-b249-418a-9361-b4bf675995cc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313211783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.2313211783
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1035460189
Short name T925
Test name
Test status
Simulation time 43502298114 ps
CPU time 469.93 seconds
Started Jan 24 07:41:15 PM PST 24
Finished Jan 24 07:49:06 PM PST 24
Peak memory 201984 kb
Host smart-64a940c7-fe87-4674-b736-6ec74fd2e749
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035460189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.1035460189
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.359403468
Short name T458
Test name
Test status
Simulation time 79828843 ps
CPU time 0.84 seconds
Started Jan 24 06:07:48 PM PST 24
Finished Jan 24 06:07:55 PM PST 24
Peak memory 201944 kb
Host smart-dd164a47-d8df-4283-9823-8dc1798cd462
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359403468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.359403468
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.984666228
Short name T250
Test name
Test status
Simulation time 47676113505 ps
CPU time 741.81 seconds
Started Jan 24 06:07:47 PM PST 24
Finished Jan 24 06:20:16 PM PST 24
Peak memory 357736 kb
Host smart-1637797c-f873-4b0b-b63d-9fd7ba72d0bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984666228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.984666228
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.4294122060
Short name T283
Test name
Test status
Simulation time 676467812 ps
CPU time 124.28 seconds
Started Jan 24 06:06:50 PM PST 24
Finished Jan 24 06:08:56 PM PST 24
Peak memory 371376 kb
Host smart-9575ac29-71ac-454d-b717-6d0d904be959
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294122060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.4294122060
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.4219668306
Short name T494
Test name
Test status
Simulation time 7011370966 ps
CPU time 1955.24 seconds
Started Jan 24 06:26:50 PM PST 24
Finished Jan 24 06:59:26 PM PST 24
Peak memory 364572 kb
Host smart-77b18196-4106-4142-80cd-3278744e50db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219668306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.4219668306
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3510228028
Short name T636
Test name
Test status
Simulation time 2054464028 ps
CPU time 2592.59 seconds
Started Jan 24 06:07:58 PM PST 24
Finished Jan 24 06:51:15 PM PST 24
Peak memory 417812 kb
Host smart-26b0e71b-3b22-429b-93e1-9096dc9e2407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3510228028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3510228028
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3932159338
Short name T903
Test name
Test status
Simulation time 11875149409 ps
CPU time 301.17 seconds
Started Jan 24 06:06:58 PM PST 24
Finished Jan 24 06:12:00 PM PST 24
Peak memory 201944 kb
Host smart-107f65fa-d29e-44aa-ab7b-20f09ebc148c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932159338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.3932159338
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.384428775
Short name T421
Test name
Test status
Simulation time 211514672 ps
CPU time 57.55 seconds
Started Jan 24 06:18:44 PM PST 24
Finished Jan 24 06:19:43 PM PST 24
Peak memory 300044 kb
Host smart-4d369c8e-265c-4de5-b00c-b037cebe24e3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384428775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.384428775
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.4228046969
Short name T948
Test name
Test status
Simulation time 159855755 ps
CPU time 0.67 seconds
Started Jan 24 06:51:06 PM PST 24
Finished Jan 24 06:51:07 PM PST 24
Peak memory 200792 kb
Host smart-a4a2f851-6060-4f10-bc80-9cc895e3e226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228046969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.4228046969
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.3146395119
Short name T671
Test name
Test status
Simulation time 3360594599 ps
CPU time 72.95 seconds
Started Jan 24 09:00:44 PM PST 24
Finished Jan 24 09:01:58 PM PST 24
Peak memory 201948 kb
Host smart-114d368f-fed1-43bf-8fb7-edc4c115a022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146395119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.3146395119
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.1291256531
Short name T279
Test name
Test status
Simulation time 58436850414 ps
CPU time 1541.56 seconds
Started Jan 24 06:09:01 PM PST 24
Finished Jan 24 06:34:43 PM PST 24
Peak memory 372492 kb
Host smart-9927bd33-2b70-4a47-b7b2-9842900cb698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291256531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.1291256531
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.2922441932
Short name T309
Test name
Test status
Simulation time 77223641 ps
CPU time 19.7 seconds
Started Jan 24 06:08:12 PM PST 24
Finished Jan 24 06:08:32 PM PST 24
Peak memory 268280 kb
Host smart-a544a317-f32b-467e-af02-b6938a07a59d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922441932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.2922441932
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.4245319081
Short name T256
Test name
Test status
Simulation time 387491479 ps
CPU time 3.15 seconds
Started Jan 24 06:45:24 PM PST 24
Finished Jan 24 06:45:28 PM PST 24
Peak memory 214984 kb
Host smart-15ca6ffd-a667-4b95-b56a-34132e643e58
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245319081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.4245319081
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.1891063797
Short name T247
Test name
Test status
Simulation time 303038376 ps
CPU time 5.52 seconds
Started Jan 24 09:50:35 PM PST 24
Finished Jan 24 09:50:41 PM PST 24
Peak memory 201916 kb
Host smart-09510b35-26ef-401b-8e37-4cc5baf00b2c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891063797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.1891063797
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.2708146515
Short name T41
Test name
Test status
Simulation time 5645148184 ps
CPU time 536.23 seconds
Started Jan 24 06:08:04 PM PST 24
Finished Jan 24 06:17:01 PM PST 24
Peak memory 370640 kb
Host smart-1636ad07-f0b9-4c12-9796-ddff32f44288
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708146515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.2708146515
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.2556925502
Short name T964
Test name
Test status
Simulation time 2719840645 ps
CPU time 10.1 seconds
Started Jan 24 06:08:06 PM PST 24
Finished Jan 24 06:08:16 PM PST 24
Peak memory 201912 kb
Host smart-0ce576c8-c682-4070-8cdd-73b182973fd6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556925502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.2556925502
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3845794417
Short name T739
Test name
Test status
Simulation time 235508936463 ps
CPU time 516.39 seconds
Started Jan 24 06:08:07 PM PST 24
Finished Jan 24 06:16:45 PM PST 24
Peak memory 201864 kb
Host smart-45ca3c11-26b8-42cb-9865-4a1f596dcc66
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845794417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.3845794417
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.687121390
Short name T219
Test name
Test status
Simulation time 79881599 ps
CPU time 1.11 seconds
Started Jan 24 06:09:07 PM PST 24
Finished Jan 24 06:09:08 PM PST 24
Peak memory 202160 kb
Host smart-735fc3ce-4978-4940-89e4-d7e29df2fa3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687121390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.687121390
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.3308275721
Short name T699
Test name
Test status
Simulation time 165672842763 ps
CPU time 1546.15 seconds
Started Jan 24 06:09:00 PM PST 24
Finished Jan 24 06:34:47 PM PST 24
Peak memory 373788 kb
Host smart-aa5a0c24-d9e8-4867-89f1-0d2520ab70ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308275721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3308275721
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.636749523
Short name T870
Test name
Test status
Simulation time 266947501 ps
CPU time 1.74 seconds
Started Jan 24 07:41:56 PM PST 24
Finished Jan 24 07:42:09 PM PST 24
Peak memory 201844 kb
Host smart-2199ea39-437e-4627-8adc-0368e2b85831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636749523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.636749523
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.1693702869
Short name T728
Test name
Test status
Simulation time 41568364382 ps
CPU time 1225.92 seconds
Started Jan 24 08:34:07 PM PST 24
Finished Jan 24 08:54:34 PM PST 24
Peak memory 370956 kb
Host smart-93de2f92-4f55-4e51-ae55-86672db6eb1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693702869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.1693702869
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1660989805
Short name T906
Test name
Test status
Simulation time 951474210 ps
CPU time 2788.22 seconds
Started Jan 24 06:47:09 PM PST 24
Finished Jan 24 07:33:38 PM PST 24
Peak memory 433188 kb
Host smart-ab1a541c-1c0d-47eb-8183-f6d966548ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1660989805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.1660989805
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.4109928438
Short name T760
Test name
Test status
Simulation time 7257278980 ps
CPU time 246.28 seconds
Started Jan 24 07:54:33 PM PST 24
Finished Jan 24 07:58:41 PM PST 24
Peak memory 201940 kb
Host smart-17fbd96b-3bee-4020-9742-302f47873710
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109928438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.4109928438
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.553915466
Short name T576
Test name
Test status
Simulation time 121173287 ps
CPU time 52.64 seconds
Started Jan 24 07:10:16 PM PST 24
Finished Jan 24 07:11:09 PM PST 24
Peak memory 313204 kb
Host smart-ae3a2ff8-e8fe-43df-8f14-35cbfb9f5b51
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553915466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_throughput_w_partial_write.553915466
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.508989305
Short name T941
Test name
Test status
Simulation time 5413671204 ps
CPU time 349.98 seconds
Started Jan 24 06:26:56 PM PST 24
Finished Jan 24 06:32:47 PM PST 24
Peak memory 362552 kb
Host smart-5c56d75f-a2fb-4946-986f-671e9968fbc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508989305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.sram_ctrl_access_during_key_req.508989305
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.409566367
Short name T446
Test name
Test status
Simulation time 15535421 ps
CPU time 0.67 seconds
Started Jan 24 07:04:21 PM PST 24
Finished Jan 24 07:04:23 PM PST 24
Peak memory 201748 kb
Host smart-3466a582-9a6c-4eb8-91ef-05b8a32d6dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409566367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.409566367
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.560332217
Short name T833
Test name
Test status
Simulation time 5598472014 ps
CPU time 59.85 seconds
Started Jan 24 06:09:07 PM PST 24
Finished Jan 24 06:10:07 PM PST 24
Peak memory 201804 kb
Host smart-b8f79e9e-af51-4bf6-a401-d00a0430ab28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560332217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.
560332217
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.72836895
Short name T746
Test name
Test status
Simulation time 3012026020 ps
CPU time 231.39 seconds
Started Jan 24 07:00:46 PM PST 24
Finished Jan 24 07:04:41 PM PST 24
Peak memory 356660 kb
Host smart-2170470d-d88f-4895-a6a5-0887f89e7b68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72836895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable
.72836895
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.3365905479
Short name T313
Test name
Test status
Simulation time 142126173 ps
CPU time 2.05 seconds
Started Jan 24 06:09:56 PM PST 24
Finished Jan 24 06:09:59 PM PST 24
Peak memory 212280 kb
Host smart-b1124140-f32c-4b14-88da-53e4d17f2f0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365905479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.3365905479
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.870344826
Short name T262
Test name
Test status
Simulation time 2582177288 ps
CPU time 136.85 seconds
Started Jan 24 06:09:53 PM PST 24
Finished Jan 24 06:12:10 PM PST 24
Peak memory 366468 kb
Host smart-f20d79b5-f3f9-4c4c-be94-ef13e0cdc398
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870344826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.sram_ctrl_max_throughput.870344826
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.586171596
Short name T335
Test name
Test status
Simulation time 156664046 ps
CPU time 5.03 seconds
Started Jan 24 06:09:54 PM PST 24
Finished Jan 24 06:10:00 PM PST 24
Peak memory 210100 kb
Host smart-a6fe0d80-120a-492c-8d27-0c2d7faade3f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586171596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.sram_ctrl_mem_partial_access.586171596
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.4204733962
Short name T439
Test name
Test status
Simulation time 696293784 ps
CPU time 4.5 seconds
Started Jan 24 07:26:42 PM PST 24
Finished Jan 24 07:26:47 PM PST 24
Peak memory 201944 kb
Host smart-19b62732-c5c6-4190-8e5b-b34123b06763
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204733962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.4204733962
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.2302558997
Short name T740
Test name
Test status
Simulation time 7561607641 ps
CPU time 627.29 seconds
Started Jan 24 06:49:01 PM PST 24
Finished Jan 24 06:59:29 PM PST 24
Peak memory 367556 kb
Host smart-34d1e630-4444-48a5-ba27-aac08c9bfb67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302558997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.2302558997
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.147973104
Short name T907
Test name
Test status
Simulation time 66101573 ps
CPU time 1.65 seconds
Started Jan 24 06:09:21 PM PST 24
Finished Jan 24 06:09:24 PM PST 24
Peak memory 201792 kb
Host smart-c18688dd-9a2c-40d2-a5cf-de40b74d3ca2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147973104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s
ram_ctrl_partial_access.147973104
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1037942140
Short name T498
Test name
Test status
Simulation time 228117838777 ps
CPU time 643.95 seconds
Started Jan 24 06:09:19 PM PST 24
Finished Jan 24 06:20:04 PM PST 24
Peak memory 201892 kb
Host smart-56e84ad8-5c17-42ec-bd95-858a88a61c2b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037942140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.1037942140
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.3819647133
Short name T637
Test name
Test status
Simulation time 33680738 ps
CPU time 0.9 seconds
Started Jan 24 06:54:46 PM PST 24
Finished Jan 24 06:54:47 PM PST 24
Peak memory 201968 kb
Host smart-3d5ff4d0-0874-4765-ab02-6a232aa3aebf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819647133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3819647133
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.847509286
Short name T787
Test name
Test status
Simulation time 7065664431 ps
CPU time 636.41 seconds
Started Jan 24 06:10:02 PM PST 24
Finished Jan 24 06:20:41 PM PST 24
Peak memory 356108 kb
Host smart-2f7e0b4f-068f-4edd-8573-557cc1954cea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847509286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.847509286
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.2050137656
Short name T658
Test name
Test status
Simulation time 888017174 ps
CPU time 52.55 seconds
Started Jan 24 06:09:06 PM PST 24
Finished Jan 24 06:09:59 PM PST 24
Peak memory 305132 kb
Host smart-f917355f-a5cc-4de0-920a-4c874e7bc03b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050137656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2050137656
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.3032334950
Short name T930
Test name
Test status
Simulation time 54813725982 ps
CPU time 1690.14 seconds
Started Jan 24 09:14:09 PM PST 24
Finished Jan 24 09:42:21 PM PST 24
Peak memory 372852 kb
Host smart-9c80321c-84f8-49b1-af77-f76951e5b3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032334950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.sram_ctrl_stress_all.3032334950
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1591038642
Short name T239
Test name
Test status
Simulation time 1240963506 ps
CPU time 3057.61 seconds
Started Jan 24 06:10:08 PM PST 24
Finished Jan 24 07:01:07 PM PST 24
Peak memory 445716 kb
Host smart-77d84d68-69f1-400a-911c-6fed38513c16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1591038642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.1591038642
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2569786768
Short name T380
Test name
Test status
Simulation time 3077912367 ps
CPU time 275.82 seconds
Started Jan 24 07:19:14 PM PST 24
Finished Jan 24 07:23:51 PM PST 24
Peak memory 201940 kb
Host smart-9ba9806e-811e-45e3-a57b-845160d2f0c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569786768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.2569786768
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1687724432
Short name T394
Test name
Test status
Simulation time 1743802903 ps
CPU time 139.96 seconds
Started Jan 24 07:02:34 PM PST 24
Finished Jan 24 07:04:59 PM PST 24
Peak memory 359024 kb
Host smart-7a983701-3d54-4d7a-8a1c-d505ec348a1f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687724432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1687724432
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1494328481
Short name T604
Test name
Test status
Simulation time 4906823744 ps
CPU time 1216.61 seconds
Started Jan 24 06:45:53 PM PST 24
Finished Jan 24 07:06:11 PM PST 24
Peak memory 370688 kb
Host smart-ada9d6ce-94f8-43fb-95f2-7f768461885a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494328481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.1494328481
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.2015444766
Short name T241
Test name
Test status
Simulation time 206328861 ps
CPU time 0.71 seconds
Started Jan 24 06:11:40 PM PST 24
Finished Jan 24 06:11:41 PM PST 24
Peak memory 201688 kb
Host smart-ee6aadbd-80d6-434c-9004-b396d8069be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015444766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.2015444766
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.972174686
Short name T348
Test name
Test status
Simulation time 985839557 ps
CPU time 17.99 seconds
Started Jan 24 06:10:24 PM PST 24
Finished Jan 24 06:10:43 PM PST 24
Peak memory 201856 kb
Host smart-9d3dbf4b-1551-4ad5-9a48-10541f04c9f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972174686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.
972174686
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.296415882
Short name T504
Test name
Test status
Simulation time 4522639172 ps
CPU time 109.15 seconds
Started Jan 24 06:11:06 PM PST 24
Finished Jan 24 06:12:55 PM PST 24
Peak memory 247848 kb
Host smart-669d5349-e85e-4451-b624-c48dde096ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296415882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl
e.296415882
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.1207544055
Short name T779
Test name
Test status
Simulation time 883117429 ps
CPU time 22.92 seconds
Started Jan 24 06:10:45 PM PST 24
Finished Jan 24 06:11:08 PM PST 24
Peak memory 269296 kb
Host smart-4b18c5e7-c4c6-4b6e-b74c-c37da8810dca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207544055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.1207544055
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.3448746842
Short name T253
Test name
Test status
Simulation time 91369081 ps
CPU time 3.04 seconds
Started Jan 24 07:22:18 PM PST 24
Finished Jan 24 07:22:22 PM PST 24
Peak memory 218256 kb
Host smart-feaf8a21-94eb-4922-91ab-324de8057290
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448746842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.3448746842
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.3085635329
Short name T589
Test name
Test status
Simulation time 291207288 ps
CPU time 4.71 seconds
Started Jan 24 06:54:05 PM PST 24
Finished Jan 24 06:54:11 PM PST 24
Peak memory 201960 kb
Host smart-16b72ecc-9a88-4c18-8b81-306fd369141d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085635329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.3085635329
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.3478898629
Short name T629
Test name
Test status
Simulation time 13296675287 ps
CPU time 1133.19 seconds
Started Jan 24 06:10:26 PM PST 24
Finished Jan 24 06:29:19 PM PST 24
Peak memory 372264 kb
Host smart-62de8c98-fbbf-4bc7-9125-7bd85565e9dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478898629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.3478898629
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.1533896282
Short name T736
Test name
Test status
Simulation time 3864605009 ps
CPU time 17.82 seconds
Started Jan 24 06:10:37 PM PST 24
Finished Jan 24 06:10:56 PM PST 24
Peak memory 201932 kb
Host smart-42ebfce3-ea60-4bc6-a6ae-e799735eeffb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533896282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.1533896282
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1316058942
Short name T52
Test name
Test status
Simulation time 56832336037 ps
CPU time 297.99 seconds
Started Jan 24 07:46:24 PM PST 24
Finished Jan 24 07:51:24 PM PST 24
Peak memory 201924 kb
Host smart-861c6ad6-8315-48ca-a02a-b2f9b48d476a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316058942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.1316058942
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.2443121436
Short name T357
Test name
Test status
Simulation time 159868652 ps
CPU time 0.84 seconds
Started Jan 24 06:11:26 PM PST 24
Finished Jan 24 06:11:27 PM PST 24
Peak memory 201964 kb
Host smart-201d84eb-4627-4ae9-bfdd-c6c075f44ef6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443121436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2443121436
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.3307944172
Short name T273
Test name
Test status
Simulation time 27282158396 ps
CPU time 1680.53 seconds
Started Jan 24 06:11:17 PM PST 24
Finished Jan 24 06:39:22 PM PST 24
Peak memory 371124 kb
Host smart-648b529b-4aae-4bfe-93a1-e032a7affe00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307944172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3307944172
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.378729261
Short name T974
Test name
Test status
Simulation time 195734403 ps
CPU time 7.58 seconds
Started Jan 24 06:47:40 PM PST 24
Finished Jan 24 06:47:48 PM PST 24
Peak memory 231692 kb
Host smart-d32cfbf3-46a6-4852-bb16-06c0a4a01019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378729261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.378729261
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.1277740868
Short name T280
Test name
Test status
Simulation time 11083485280 ps
CPU time 1571.56 seconds
Started Jan 24 06:11:41 PM PST 24
Finished Jan 24 06:37:53 PM PST 24
Peak memory 373792 kb
Host smart-0c797103-955a-4608-8f13-fbee549da151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277740868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.1277740868
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.220095917
Short name T45
Test name
Test status
Simulation time 1135725329 ps
CPU time 2641.37 seconds
Started Jan 24 06:43:20 PM PST 24
Finished Jan 24 07:27:24 PM PST 24
Peak memory 418284 kb
Host smart-eee397ee-5a52-4783-acdf-0a1480e5636d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=220095917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.220095917
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1290038979
Short name T934
Test name
Test status
Simulation time 1127226479 ps
CPU time 87.99 seconds
Started Jan 24 10:04:41 PM PST 24
Finished Jan 24 10:06:14 PM PST 24
Peak memory 201876 kb
Host smart-542771b5-eb5d-4c4a-bd91-5f8732a4e82a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290038979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.1290038979
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3979911105
Short name T575
Test name
Test status
Simulation time 310121961 ps
CPU time 128.89 seconds
Started Jan 24 06:10:44 PM PST 24
Finished Jan 24 06:12:53 PM PST 24
Peak memory 363748 kb
Host smart-105fbec3-ea3d-4aac-b5eb-89b676ff0fcf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979911105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3979911105
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3624883345
Short name T40
Test name
Test status
Simulation time 3226549319 ps
CPU time 1168.06 seconds
Started Jan 24 06:12:39 PM PST 24
Finished Jan 24 06:32:08 PM PST 24
Peak memory 372704 kb
Host smart-86fb3d6e-d04f-4b30-a092-abda21a86291
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624883345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.3624883345
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.141365586
Short name T25
Test name
Test status
Simulation time 13093625 ps
CPU time 0.66 seconds
Started Jan 24 07:22:32 PM PST 24
Finished Jan 24 07:22:33 PM PST 24
Peak memory 201692 kb
Host smart-10301679-9b73-4a86-b829-384a137e31b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141365586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.141365586
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.2702636178
Short name T674
Test name
Test status
Simulation time 6778405630 ps
CPU time 62.93 seconds
Started Jan 24 06:11:54 PM PST 24
Finished Jan 24 06:12:58 PM PST 24
Peak memory 201888 kb
Host smart-c0a30d05-a7c7-4a58-b77b-f52fdd636307
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702636178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.2702636178
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.171781686
Short name T523
Test name
Test status
Simulation time 34967779474 ps
CPU time 354.38 seconds
Started Jan 24 06:12:41 PM PST 24
Finished Jan 24 06:18:36 PM PST 24
Peak memory 357232 kb
Host smart-9f6df246-5fc8-4b1b-abab-facd707fa3a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171781686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executabl
e.171781686
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.645216251
Short name T289
Test name
Test status
Simulation time 44822088 ps
CPU time 2.39 seconds
Started Jan 24 06:12:21 PM PST 24
Finished Jan 24 06:12:27 PM PST 24
Peak memory 210092 kb
Host smart-b9961a2e-8ef0-4bd4-b637-755dc702c983
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645216251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.sram_ctrl_max_throughput.645216251
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3480337017
Short name T74
Test name
Test status
Simulation time 44458384 ps
CPU time 3.03 seconds
Started Jan 24 06:12:57 PM PST 24
Finished Jan 24 06:13:00 PM PST 24
Peak memory 210136 kb
Host smart-3f34815c-631c-4486-b938-43645a9e027a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480337017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.3480337017
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.1773082362
Short name T511
Test name
Test status
Simulation time 1434104429 ps
CPU time 9.89 seconds
Started Jan 24 06:12:54 PM PST 24
Finished Jan 24 06:13:05 PM PST 24
Peak memory 201936 kb
Host smart-7df5e216-072f-43de-ab90-8e677db2fd12
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773082362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.1773082362
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.166911388
Short name T224
Test name
Test status
Simulation time 972562101 ps
CPU time 50.53 seconds
Started Jan 24 06:12:05 PM PST 24
Finished Jan 24 06:12:57 PM PST 24
Peak memory 296700 kb
Host smart-90eef3bf-6934-4805-98a1-25159fd551ea
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166911388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.s
ram_ctrl_partial_access.166911388
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3959832240
Short name T36
Test name
Test status
Simulation time 30900867185 ps
CPU time 382.08 seconds
Started Jan 24 06:12:14 PM PST 24
Finished Jan 24 06:18:36 PM PST 24
Peak memory 201920 kb
Host smart-580597fc-cd75-4efc-bb86-b758b2acdc29
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959832240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.3959832240
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.2615074105
Short name T752
Test name
Test status
Simulation time 83229769 ps
CPU time 1.11 seconds
Started Jan 24 06:12:52 PM PST 24
Finished Jan 24 06:12:54 PM PST 24
Peak memory 202196 kb
Host smart-084f7067-59f2-46d6-a88f-591eeb241b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615074105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2615074105
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.1678469841
Short name T612
Test name
Test status
Simulation time 14148581618 ps
CPU time 1070.2 seconds
Started Jan 24 06:12:44 PM PST 24
Finished Jan 24 06:30:35 PM PST 24
Peak memory 364028 kb
Host smart-0a8e2bbb-0dd4-4396-b4c5-77b670b65187
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678469841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1678469841
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.1462875701
Short name T727
Test name
Test status
Simulation time 223583551 ps
CPU time 72.2 seconds
Started Jan 24 06:11:49 PM PST 24
Finished Jan 24 06:13:02 PM PST 24
Peak memory 319328 kb
Host smart-cc69140a-c7ba-4fa6-a778-498bf3960106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462875701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1462875701
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.330170153
Short name T682
Test name
Test status
Simulation time 98184027661 ps
CPU time 2792.62 seconds
Started Jan 24 06:13:13 PM PST 24
Finished Jan 24 06:59:46 PM PST 24
Peak memory 372712 kb
Host smart-295a2479-6aa3-434f-8690-678c7614b0b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330170153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_stress_all.330170153
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2097443304
Short name T379
Test name
Test status
Simulation time 1756659689 ps
CPU time 2374.05 seconds
Started Jan 24 06:13:05 PM PST 24
Finished Jan 24 06:52:40 PM PST 24
Peak memory 413704 kb
Host smart-7da7c601-684d-47c0-8e83-01dd7a4d63de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2097443304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2097443304
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.4271880970
Short name T967
Test name
Test status
Simulation time 9215023324 ps
CPU time 226.67 seconds
Started Jan 24 06:12:09 PM PST 24
Finished Jan 24 06:15:57 PM PST 24
Peak memory 201924 kb
Host smart-0181afd4-ebf0-437d-9dd5-c3e8515fe1f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271880970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.4271880970
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1033427086
Short name T690
Test name
Test status
Simulation time 329677425 ps
CPU time 125.63 seconds
Started Jan 24 06:12:27 PM PST 24
Finished Jan 24 06:14:34 PM PST 24
Peak memory 361208 kb
Host smart-05c29e4b-5409-42c0-a85b-33e2fb3c61f1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033427086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1033427086
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1947524093
Short name T17
Test name
Test status
Simulation time 5348555168 ps
CPU time 811.66 seconds
Started Jan 24 06:13:58 PM PST 24
Finished Jan 24 06:27:30 PM PST 24
Peak memory 371428 kb
Host smart-7622c4d3-076a-4d67-89c3-fee0f4b408aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947524093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.1947524093
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.4290315775
Short name T548
Test name
Test status
Simulation time 31249015 ps
CPU time 0.65 seconds
Started Jan 24 07:22:48 PM PST 24
Finished Jan 24 07:22:53 PM PST 24
Peak memory 201632 kb
Host smart-ac7135eb-019c-47df-98d8-724b51da2669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290315775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.4290315775
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.1879368517
Short name T272
Test name
Test status
Simulation time 3024490251 ps
CPU time 48.72 seconds
Started Jan 24 06:13:18 PM PST 24
Finished Jan 24 06:14:07 PM PST 24
Peak memory 201928 kb
Host smart-f36f686c-5ea6-4fd2-be42-9b20861667d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879368517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.1879368517
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.3049296238
Short name T432
Test name
Test status
Simulation time 43342473395 ps
CPU time 1753.75 seconds
Started Jan 24 06:25:55 PM PST 24
Finished Jan 24 06:55:13 PM PST 24
Peak memory 372640 kb
Host smart-5adc7b93-e957-42b9-9526-3a1c9d1a6e83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049296238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.3049296238
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.177535766
Short name T793
Test name
Test status
Simulation time 824607384 ps
CPU time 13.82 seconds
Started Jan 24 06:25:54 PM PST 24
Finished Jan 24 06:26:09 PM PST 24
Peak memory 213120 kb
Host smart-4c2dabf9-b979-4287-b863-0661c5d3c798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177535766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc
alation.177535766
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.3019939621
Short name T664
Test name
Test status
Simulation time 942439619 ps
CPU time 31.37 seconds
Started Jan 24 07:04:48 PM PST 24
Finished Jan 24 07:05:21 PM PST 24
Peak memory 288752 kb
Host smart-6b15a25e-927a-4d1f-bc62-9ef03472098f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019939621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.3019939621
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.2933272436
Short name T231
Test name
Test status
Simulation time 311777360 ps
CPU time 8.19 seconds
Started Jan 24 06:14:04 PM PST 24
Finished Jan 24 06:14:13 PM PST 24
Peak memory 201864 kb
Host smart-0c3cf439-efcd-454f-83be-12eb94d59df8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933272436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.2933272436
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.3187760735
Short name T923
Test name
Test status
Simulation time 878764386 ps
CPU time 65.61 seconds
Started Jan 24 06:13:11 PM PST 24
Finished Jan 24 06:14:17 PM PST 24
Peak memory 297616 kb
Host smart-211da849-1161-4ed4-a010-92710c85aad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187760735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.3187760735
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.3564895852
Short name T503
Test name
Test status
Simulation time 2444621516 ps
CPU time 14.05 seconds
Started Jan 24 06:13:34 PM PST 24
Finished Jan 24 06:13:49 PM PST 24
Peak memory 201884 kb
Host smart-1aa79875-ab33-4ac0-9c37-dcbbef30451e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564895852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.3564895852
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2595659395
Short name T665
Test name
Test status
Simulation time 73393948960 ps
CPU time 409.8 seconds
Started Jan 24 07:04:10 PM PST 24
Finished Jan 24 07:11:01 PM PST 24
Peak memory 201952 kb
Host smart-4add9048-1fe0-43a2-97b9-ce63ecdca0be
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595659395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.2595659395
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.1808764093
Short name T31
Test name
Test status
Simulation time 89929869 ps
CPU time 0.89 seconds
Started Jan 24 07:31:58 PM PST 24
Finished Jan 24 07:32:07 PM PST 24
Peak memory 201968 kb
Host smart-cf0b45b9-b174-4756-ba37-04ddb4a2df81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808764093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1808764093
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.3769895318
Short name T360
Test name
Test status
Simulation time 19074242706 ps
CPU time 1343.59 seconds
Started Jan 24 06:14:00 PM PST 24
Finished Jan 24 06:36:25 PM PST 24
Peak memory 373240 kb
Host smart-f85b0208-7e92-4de6-bd43-1b4a1db5f266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769895318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3769895318
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.447845525
Short name T893
Test name
Test status
Simulation time 368251006 ps
CPU time 3.42 seconds
Started Jan 24 06:13:12 PM PST 24
Finished Jan 24 06:13:16 PM PST 24
Peak memory 211012 kb
Host smart-74a4bef1-7fa7-459c-8b6c-835783a5c9b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447845525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.447845525
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.3611087374
Short name T856
Test name
Test status
Simulation time 20991539730 ps
CPU time 1689.56 seconds
Started Jan 24 06:29:17 PM PST 24
Finished Jan 24 06:57:28 PM PST 24
Peak memory 373816 kb
Host smart-54eaf017-edf0-4e85-acc5-4ea5d5dd03c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611087374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.3611087374
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1111190349
Short name T595
Test name
Test status
Simulation time 10585285779 ps
CPU time 3237.14 seconds
Started Jan 24 06:14:14 PM PST 24
Finished Jan 24 07:08:12 PM PST 24
Peak memory 431756 kb
Host smart-b75d02a9-8a5d-48c2-ab7f-d154c53a039c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1111190349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1111190349
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.112611304
Short name T584
Test name
Test status
Simulation time 3869936315 ps
CPU time 187.1 seconds
Started Jan 24 06:47:22 PM PST 24
Finished Jan 24 06:50:29 PM PST 24
Peak memory 201892 kb
Host smart-28c85dcb-8635-447c-a98e-64f382da4ca8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112611304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_stress_pipeline.112611304
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2911645105
Short name T471
Test name
Test status
Simulation time 134619269 ps
CPU time 2.15 seconds
Started Jan 24 07:01:12 PM PST 24
Finished Jan 24 07:01:24 PM PST 24
Peak memory 210068 kb
Host smart-6cae440e-77a3-4b30-ba79-b9f57bfb041f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911645105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2911645105
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2184623601
Short name T218
Test name
Test status
Simulation time 3863122091 ps
CPU time 1789.73 seconds
Started Jan 24 07:54:38 PM PST 24
Finished Jan 24 08:24:29 PM PST 24
Peak memory 371704 kb
Host smart-d03cfad8-1ad9-48c5-b260-749c0e0ac5a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184623601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.2184623601
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.2259904370
Short name T579
Test name
Test status
Simulation time 56385332 ps
CPU time 0.65 seconds
Started Jan 24 06:15:59 PM PST 24
Finished Jan 24 06:16:00 PM PST 24
Peak memory 200744 kb
Host smart-8b05afb7-92e2-47dd-9bfb-ac8c69762a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259904370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.2259904370
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.2686157839
Short name T319
Test name
Test status
Simulation time 833871638 ps
CPU time 39.31 seconds
Started Jan 24 06:30:50 PM PST 24
Finished Jan 24 06:31:30 PM PST 24
Peak memory 201812 kb
Host smart-d02c356f-28d7-46ab-8da2-e69f6cd346d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686157839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.2686157839
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.1233611837
Short name T840
Test name
Test status
Simulation time 3243427754 ps
CPU time 1579.93 seconds
Started Jan 24 08:02:16 PM PST 24
Finished Jan 24 08:28:38 PM PST 24
Peak memory 371672 kb
Host smart-0d76b53d-1684-4cd0-9efc-49024e957753
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233611837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.1233611837
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.3301648370
Short name T366
Test name
Test status
Simulation time 183000754 ps
CPU time 39.1 seconds
Started Jan 24 06:15:07 PM PST 24
Finished Jan 24 06:15:46 PM PST 24
Peak memory 294820 kb
Host smart-8701be08-ab41-4165-b7b8-45f37e5ff144
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301648370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.3301648370
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2586770747
Short name T540
Test name
Test status
Simulation time 341351793 ps
CPU time 5.5 seconds
Started Jan 24 06:15:45 PM PST 24
Finished Jan 24 06:15:50 PM PST 24
Peak memory 210068 kb
Host smart-3af93c6b-da33-440a-b2e2-af6a521b96ae
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586770747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.2586770747
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.3228818606
Short name T214
Test name
Test status
Simulation time 351302572 ps
CPU time 5.31 seconds
Started Jan 24 06:15:42 PM PST 24
Finished Jan 24 06:15:47 PM PST 24
Peak memory 201980 kb
Host smart-c80ce0f6-3cd0-4284-a1a1-c0b7072d4563
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228818606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.3228818606
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.1229688244
Short name T843
Test name
Test status
Simulation time 6522606266 ps
CPU time 237.31 seconds
Started Jan 24 06:14:44 PM PST 24
Finished Jan 24 06:18:42 PM PST 24
Peak memory 332720 kb
Host smart-05906590-0893-41f2-aa37-8e4aa0e960c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229688244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.1229688244
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.4223912820
Short name T545
Test name
Test status
Simulation time 106474179 ps
CPU time 4.04 seconds
Started Jan 24 07:34:08 PM PST 24
Finished Jan 24 07:34:13 PM PST 24
Peak memory 214956 kb
Host smart-efd24328-2206-4a73-bfba-970c6aa0a112
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223912820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.4223912820
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3896877127
Short name T401
Test name
Test status
Simulation time 44491793975 ps
CPU time 489.86 seconds
Started Jan 24 06:35:44 PM PST 24
Finished Jan 24 06:43:55 PM PST 24
Peak memory 201948 kb
Host smart-d4b850e3-9ff5-43ec-bd17-50639ee083c7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896877127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.3896877127
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.1776734206
Short name T826
Test name
Test status
Simulation time 29947096 ps
CPU time 0.86 seconds
Started Jan 24 07:15:34 PM PST 24
Finished Jan 24 07:15:36 PM PST 24
Peak memory 201968 kb
Host smart-528455d6-3f8d-4ed1-9851-a9dd0327ea88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776734206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1776734206
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.342409750
Short name T311
Test name
Test status
Simulation time 26361463669 ps
CPU time 253 seconds
Started Jan 24 06:23:01 PM PST 24
Finished Jan 24 06:27:15 PM PST 24
Peak memory 308628 kb
Host smart-d1c4d04f-e0b4-465a-99ed-eea8f2cc2e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342409750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.342409750
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3583972210
Short name T642
Test name
Test status
Simulation time 231010147 ps
CPU time 3.5 seconds
Started Jan 24 07:48:48 PM PST 24
Finished Jan 24 07:48:52 PM PST 24
Peak memory 201892 kb
Host smart-2ca04fb1-2edc-4313-8685-7e6941ca6859
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583972210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3583972210
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1037900052
Short name T382
Test name
Test status
Simulation time 2335810326 ps
CPU time 3125.25 seconds
Started Jan 24 06:15:49 PM PST 24
Finished Jan 24 07:07:55 PM PST 24
Peak memory 429004 kb
Host smart-6ccbbe54-761b-4011-be95-825dfcb20dfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1037900052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1037900052
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3136059012
Short name T410
Test name
Test status
Simulation time 13963172435 ps
CPU time 179.08 seconds
Started Jan 24 06:39:34 PM PST 24
Finished Jan 24 06:42:34 PM PST 24
Peak memory 201924 kb
Host smart-8fd87dc1-f049-415f-8358-03fadb310d6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136059012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.3136059012
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2471598857
Short name T327
Test name
Test status
Simulation time 91213250 ps
CPU time 3.87 seconds
Started Jan 24 07:09:07 PM PST 24
Finished Jan 24 07:09:12 PM PST 24
Peak memory 217900 kb
Host smart-3ddf0de7-ec90-4d39-bf2b-7a14797a809b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471598857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.2471598857
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1276394695
Short name T462
Test name
Test status
Simulation time 16589662940 ps
CPU time 2049.1 seconds
Started Jan 24 06:24:59 PM PST 24
Finished Jan 24 06:59:09 PM PST 24
Peak memory 372668 kb
Host smart-acbbcdf5-ff13-492b-a634-900a866a46ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276394695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.1276394695
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.2679701042
Short name T882
Test name
Test status
Simulation time 75624964 ps
CPU time 0.66 seconds
Started Jan 24 08:38:29 PM PST 24
Finished Jan 24 08:38:30 PM PST 24
Peak memory 200772 kb
Host smart-66bd579c-cfb8-433a-8acb-42295df447d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679701042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.2679701042
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.3666434095
Short name T303
Test name
Test status
Simulation time 6623469221 ps
CPU time 33.53 seconds
Started Jan 24 05:45:36 PM PST 24
Finished Jan 24 05:46:13 PM PST 24
Peak memory 201916 kb
Host smart-60f6e2d9-e212-4865-9736-99f7082bb428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666434095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
3666434095
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.2987287913
Short name T263
Test name
Test status
Simulation time 436517751 ps
CPU time 397.8 seconds
Started Jan 24 06:45:00 PM PST 24
Finished Jan 24 06:51:38 PM PST 24
Peak memory 371588 kb
Host smart-546f244b-f430-4d2d-83c5-2a618aa0cf57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987287913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.2987287913
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.1923292177
Short name T452
Test name
Test status
Simulation time 5563386347 ps
CPU time 11.37 seconds
Started Jan 24 05:46:36 PM PST 24
Finished Jan 24 05:46:48 PM PST 24
Peak memory 201836 kb
Host smart-8e59af5f-5c85-4f97-93db-281191669355
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923292177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.1923292177
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.3321124881
Short name T778
Test name
Test status
Simulation time 192065961 ps
CPU time 56.83 seconds
Started Jan 24 05:55:17 PM PST 24
Finished Jan 24 05:56:17 PM PST 24
Peak memory 306172 kb
Host smart-7d8c735c-3a7d-459c-af43-a641ec006b26
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321124881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.3321124881
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1558787640
Short name T376
Test name
Test status
Simulation time 115533917 ps
CPU time 3.04 seconds
Started Jan 24 05:46:46 PM PST 24
Finished Jan 24 05:46:50 PM PST 24
Peak memory 210112 kb
Host smart-54257e78-fe60-4a70-b843-7fad3c77697f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558787640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.1558787640
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.1746917305
Short name T878
Test name
Test status
Simulation time 1179342828 ps
CPU time 5.61 seconds
Started Jan 24 06:19:11 PM PST 24
Finished Jan 24 06:19:19 PM PST 24
Peak memory 201924 kb
Host smart-a77e191c-f2b8-4a91-9789-a3e46d64083f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746917305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.1746917305
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.2669049519
Short name T317
Test name
Test status
Simulation time 62328048660 ps
CPU time 1165.06 seconds
Started Jan 24 06:37:44 PM PST 24
Finished Jan 24 06:57:09 PM PST 24
Peak memory 369540 kb
Host smart-a58f3c4d-8f35-4319-ad7f-2942440c2dde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669049519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.2669049519
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.382130013
Short name T781
Test name
Test status
Simulation time 488369638 ps
CPU time 12.03 seconds
Started Jan 24 08:17:43 PM PST 24
Finished Jan 24 08:17:56 PM PST 24
Peak memory 244056 kb
Host smart-534357bb-eda0-4844-a7a6-d83c1214d78d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382130013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr
am_ctrl_partial_access.382130013
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3964186361
Short name T128
Test name
Test status
Simulation time 10013705583 ps
CPU time 267.06 seconds
Started Jan 24 05:46:34 PM PST 24
Finished Jan 24 05:51:02 PM PST 24
Peak memory 201928 kb
Host smart-60676d04-9422-4413-a8b9-fd5e5a2a5a0d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964186361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.3964186361
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.378125646
Short name T698
Test name
Test status
Simulation time 26424995 ps
CPU time 0.89 seconds
Started Jan 24 06:56:22 PM PST 24
Finished Jan 24 06:56:25 PM PST 24
Peak memory 201952 kb
Host smart-8c9f3e31-8ce3-40cb-8bb1-6bd326a39a2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378125646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.378125646
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.2908768457
Short name T267
Test name
Test status
Simulation time 54044885283 ps
CPU time 2472.71 seconds
Started Jan 24 05:46:37 PM PST 24
Finished Jan 24 06:27:51 PM PST 24
Peak memory 373216 kb
Host smart-a4ffc17b-83e6-451d-b49e-4cf07c906eae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908768457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2908768457
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.475335008
Short name T20
Test name
Test status
Simulation time 453510194 ps
CPU time 2.15 seconds
Started Jan 24 05:46:49 PM PST 24
Finished Jan 24 05:46:52 PM PST 24
Peak memory 220280 kb
Host smart-29527818-2014-4fdc-8731-211dc1b9ecac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475335008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_sec_cm.475335008
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.2176066765
Short name T118
Test name
Test status
Simulation time 522678668 ps
CPU time 82.85 seconds
Started Jan 24 05:45:35 PM PST 24
Finished Jan 24 05:47:03 PM PST 24
Peak memory 311748 kb
Host smart-9fedbedd-9a27-4938-b13e-096950855565
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176066765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2176066765
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.2380814405
Short name T722
Test name
Test status
Simulation time 22835149002 ps
CPU time 1932.81 seconds
Started Jan 24 05:46:47 PM PST 24
Finished Jan 24 06:19:01 PM PST 24
Peak memory 370860 kb
Host smart-3da6e51e-caad-41e8-a22b-e4439e498823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380814405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.2380814405
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1356326375
Short name T209
Test name
Test status
Simulation time 7429245539 ps
CPU time 5024.75 seconds
Started Jan 24 07:00:32 PM PST 24
Finished Jan 24 08:24:20 PM PST 24
Peak memory 430972 kb
Host smart-935f06ce-5bf1-43cb-b1b4-03fa99ce1856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1356326375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1356326375
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1793082009
Short name T569
Test name
Test status
Simulation time 47960273887 ps
CPU time 241.89 seconds
Started Jan 24 06:05:33 PM PST 24
Finished Jan 24 06:09:36 PM PST 24
Peak memory 201920 kb
Host smart-266fefad-536d-464d-9126-7777294f6278
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793082009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.1793082009
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1679515480
Short name T234
Test name
Test status
Simulation time 61963898 ps
CPU time 4.49 seconds
Started Jan 24 05:52:40 PM PST 24
Finished Jan 24 05:52:49 PM PST 24
Peak memory 218244 kb
Host smart-b1d4d785-db3a-4ae1-b351-e3d4ec9a450d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679515480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1679515480
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3448695773
Short name T749
Test name
Test status
Simulation time 1832567467 ps
CPU time 1094.91 seconds
Started Jan 24 06:28:08 PM PST 24
Finished Jan 24 06:46:23 PM PST 24
Peak memory 370588 kb
Host smart-fdc1dfb9-e1e5-4161-ad37-37cbc8dd6fcc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448695773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.3448695773
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.3432864476
Short name T857
Test name
Test status
Simulation time 14875913 ps
CPU time 0.69 seconds
Started Jan 24 07:12:55 PM PST 24
Finished Jan 24 07:12:57 PM PST 24
Peak memory 201700 kb
Host smart-4a62d4bf-dc38-4664-815b-934af33e4c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432864476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.3432864476
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.1039906871
Short name T475
Test name
Test status
Simulation time 1989801512 ps
CPU time 42.2 seconds
Started Jan 24 06:16:18 PM PST 24
Finished Jan 24 06:17:00 PM PST 24
Peak memory 201852 kb
Host smart-d2677b2b-cdf6-4578-938e-568452f98ef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039906871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.1039906871
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.539842518
Short name T470
Test name
Test status
Simulation time 598846591 ps
CPU time 169.05 seconds
Started Jan 24 06:16:50 PM PST 24
Finished Jan 24 06:19:42 PM PST 24
Peak memory 350556 kb
Host smart-bfbd3a21-75bb-47d3-b736-08429be853b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539842518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl
e.539842518
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.1286947954
Short name T541
Test name
Test status
Simulation time 232815309 ps
CPU time 88.92 seconds
Started Jan 24 06:16:33 PM PST 24
Finished Jan 24 06:18:03 PM PST 24
Peak memory 339580 kb
Host smart-20412796-d61f-4ee3-878c-1c383b2de304
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286947954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.1286947954
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.1481224468
Short name T565
Test name
Test status
Simulation time 238763867 ps
CPU time 4.83 seconds
Started Jan 24 06:17:13 PM PST 24
Finished Jan 24 06:17:19 PM PST 24
Peak memory 214984 kb
Host smart-382bc7d2-efa9-4970-ad28-2f6001664d28
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481224468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.1481224468
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.193521338
Short name T667
Test name
Test status
Simulation time 1713946513 ps
CPU time 5.72 seconds
Started Jan 24 06:17:07 PM PST 24
Finished Jan 24 06:17:13 PM PST 24
Peak memory 201952 kb
Host smart-891f3ac9-7910-4101-b689-34d6462cb966
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193521338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl
_mem_walk.193521338
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.3989997963
Short name T959
Test name
Test status
Simulation time 10604135003 ps
CPU time 607.17 seconds
Started Jan 24 06:21:24 PM PST 24
Finished Jan 24 06:31:32 PM PST 24
Peak memory 372720 kb
Host smart-9b3e32d6-76a4-41ee-a29b-5cb9ab714de5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989997963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.3989997963
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.3208290888
Short name T916
Test name
Test status
Simulation time 402170969 ps
CPU time 11.14 seconds
Started Jan 24 06:16:29 PM PST 24
Finished Jan 24 06:16:41 PM PST 24
Peak memory 242652 kb
Host smart-eb0cc7cc-a4eb-4db1-9fbc-efa1f84672f0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208290888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.3208290888
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1765745735
Short name T85
Test name
Test status
Simulation time 9379742593 ps
CPU time 649.05 seconds
Started Jan 24 07:08:34 PM PST 24
Finished Jan 24 07:19:27 PM PST 24
Peak memory 201928 kb
Host smart-19b6ab6b-62f9-4999-960a-59d3b507474a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765745735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.1765745735
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.2803619332
Short name T865
Test name
Test status
Simulation time 28764373 ps
CPU time 0.86 seconds
Started Jan 24 06:17:05 PM PST 24
Finished Jan 24 06:17:06 PM PST 24
Peak memory 201964 kb
Host smart-74bbb030-a0f3-4c57-9d8f-053fc2653f93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803619332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2803619332
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.3983995689
Short name T982
Test name
Test status
Simulation time 4734925841 ps
CPU time 1518.09 seconds
Started Jan 24 06:16:57 PM PST 24
Finished Jan 24 06:42:17 PM PST 24
Peak memory 372652 kb
Host smart-dc803e72-2004-4c64-8300-f8ab802f88a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983995689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3983995689
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.1683355384
Short name T580
Test name
Test status
Simulation time 392210808 ps
CPU time 45.64 seconds
Started Jan 24 06:15:59 PM PST 24
Finished Jan 24 06:16:46 PM PST 24
Peak memory 289976 kb
Host smart-fea623c6-121a-4dac-9d67-fa2c408750a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683355384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1683355384
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2976482273
Short name T981
Test name
Test status
Simulation time 4243704325 ps
CPU time 1638.69 seconds
Started Jan 24 07:48:14 PM PST 24
Finished Jan 24 08:15:36 PM PST 24
Peak memory 431708 kb
Host smart-025cbddb-a4d4-481f-a955-084c888193f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2976482273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2976482273
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2873818005
Short name T207
Test name
Test status
Simulation time 9798532074 ps
CPU time 264 seconds
Started Jan 24 07:30:24 PM PST 24
Finished Jan 24 07:34:49 PM PST 24
Peak memory 201912 kb
Host smart-e210282b-96d3-4a28-ae5a-126ae8f0bdca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873818005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.2873818005
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3210241144
Short name T632
Test name
Test status
Simulation time 434525917 ps
CPU time 38.68 seconds
Started Jan 24 06:16:42 PM PST 24
Finished Jan 24 06:17:21 PM PST 24
Peak memory 299756 kb
Host smart-36ef3901-d932-4122-9f88-d2ca1863a46c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210241144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3210241144
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.833238532
Short name T466
Test name
Test status
Simulation time 2269978473 ps
CPU time 1045.88 seconds
Started Jan 24 07:52:08 PM PST 24
Finished Jan 24 08:09:35 PM PST 24
Peak memory 370632 kb
Host smart-2a2de594-3eac-4289-87c5-05acd7f79d63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833238532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.sram_ctrl_access_during_key_req.833238532
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.2094221369
Short name T871
Test name
Test status
Simulation time 32742906 ps
CPU time 0.64 seconds
Started Jan 24 06:18:55 PM PST 24
Finished Jan 24 06:19:02 PM PST 24
Peak memory 200732 kb
Host smart-b6112fa5-53d8-45ee-abc9-c876badee862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094221369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.2094221369
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.2507234660
Short name T678
Test name
Test status
Simulation time 10405143802 ps
CPU time 61.58 seconds
Started Jan 24 06:17:33 PM PST 24
Finished Jan 24 06:18:36 PM PST 24
Peak memory 201868 kb
Host smart-4c71e1b8-5cd1-4097-b471-c36bb2ccb6ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507234660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.2507234660
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.376171098
Short name T107
Test name
Test status
Simulation time 897848809 ps
CPU time 283.17 seconds
Started Jan 24 06:18:19 PM PST 24
Finished Jan 24 06:23:03 PM PST 24
Peak memory 351588 kb
Host smart-ef8aa6ba-3bf1-4816-b6cf-9d27b54a3d6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376171098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executabl
e.376171098
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.1715270743
Short name T337
Test name
Test status
Simulation time 1011778611 ps
CPU time 1.76 seconds
Started Jan 24 06:18:07 PM PST 24
Finished Jan 24 06:18:09 PM PST 24
Peak memory 210048 kb
Host smart-81ae5807-5961-4280-9cc8-2d42c6c443e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715270743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.1715270743
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.1644752962
Short name T525
Test name
Test status
Simulation time 132985851 ps
CPU time 112.17 seconds
Started Jan 24 07:26:40 PM PST 24
Finished Jan 24 07:28:33 PM PST 24
Peak memory 365188 kb
Host smart-a34506c2-eabe-42cd-89d2-f2069f936d6d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644752962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.1644752962
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2218852324
Short name T388
Test name
Test status
Simulation time 1609816209 ps
CPU time 3.14 seconds
Started Jan 24 07:00:34 PM PST 24
Finished Jan 24 07:00:39 PM PST 24
Peak memory 210268 kb
Host smart-8673bd8b-01d8-449f-bf13-199a5f254839
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218852324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.2218852324
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.3349407463
Short name T849
Test name
Test status
Simulation time 137462011 ps
CPU time 7.68 seconds
Started Jan 24 07:53:40 PM PST 24
Finished Jan 24 07:53:49 PM PST 24
Peak memory 201988 kb
Host smart-796f8201-8c9a-480d-bfa1-a31085c603b9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349407463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.3349407463
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.3449639731
Short name T563
Test name
Test status
Simulation time 10389292332 ps
CPU time 847.2 seconds
Started Jan 24 07:38:51 PM PST 24
Finished Jan 24 07:53:06 PM PST 24
Peak memory 370592 kb
Host smart-1437cf7b-d6e0-44e2-b558-135b1c17686f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449639731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.3449639731
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.324509418
Short name T689
Test name
Test status
Simulation time 318799149 ps
CPU time 11.41 seconds
Started Jan 24 07:26:41 PM PST 24
Finished Jan 24 07:26:54 PM PST 24
Peak memory 247004 kb
Host smart-9c509beb-efaf-4b5f-9082-9098f24da3cf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324509418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.s
ram_ctrl_partial_access.324509418
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2223764074
Short name T397
Test name
Test status
Simulation time 21076091959 ps
CPU time 294.41 seconds
Started Jan 24 06:17:53 PM PST 24
Finished Jan 24 06:22:49 PM PST 24
Peak memory 201932 kb
Host smart-17c7fc0c-e5d0-46ce-8133-059ce01209c1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223764074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.2223764074
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.3853081034
Short name T398
Test name
Test status
Simulation time 28908993 ps
CPU time 1.18 seconds
Started Jan 24 06:18:24 PM PST 24
Finished Jan 24 06:18:26 PM PST 24
Peak memory 202216 kb
Host smart-ba178e65-24f4-48e1-bf3f-4297d5f658a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853081034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3853081034
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.3568437262
Short name T875
Test name
Test status
Simulation time 53446995192 ps
CPU time 1605.15 seconds
Started Jan 24 06:18:27 PM PST 24
Finished Jan 24 06:45:15 PM PST 24
Peak memory 362312 kb
Host smart-62d18a52-c6cf-4335-ba2a-7a814e0b1e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568437262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3568437262
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.3687099395
Short name T125
Test name
Test status
Simulation time 278591137 ps
CPU time 4.62 seconds
Started Jan 24 06:17:31 PM PST 24
Finished Jan 24 06:17:36 PM PST 24
Peak memory 201852 kb
Host smart-9b8f5c34-6851-4aa8-9d9d-fc573218b75d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687099395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3687099395
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3497113927
Short name T744
Test name
Test status
Simulation time 27946574807 ps
CPU time 4079.9 seconds
Started Jan 24 06:18:51 PM PST 24
Finished Jan 24 07:26:53 PM PST 24
Peak memory 432432 kb
Host smart-d679def4-b8ac-42e2-b5a9-d40235dcc4a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3497113927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3497113927
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2928720640
Short name T274
Test name
Test status
Simulation time 7820990865 ps
CPU time 192.94 seconds
Started Jan 24 06:17:36 PM PST 24
Finished Jan 24 06:20:49 PM PST 24
Peak memory 201948 kb
Host smart-f36e4a32-4375-47ec-be48-e084012ec012
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928720640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.2928720640
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2797482016
Short name T333
Test name
Test status
Simulation time 348911377 ps
CPU time 24.48 seconds
Started Jan 24 06:18:08 PM PST 24
Finished Jan 24 06:18:33 PM PST 24
Peak memory 268324 kb
Host smart-6cf55bfa-596b-4053-9129-f01767a02a9c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797482016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2797482016
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1532223179
Short name T15
Test name
Test status
Simulation time 522641827 ps
CPU time 19.38 seconds
Started Jan 24 06:19:30 PM PST 24
Finished Jan 24 06:19:50 PM PST 24
Peak memory 220304 kb
Host smart-a3023594-f9ce-4247-be2b-9aa71af496f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532223179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.1532223179
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.3859182187
Short name T654
Test name
Test status
Simulation time 19927068 ps
CPU time 0.66 seconds
Started Jan 24 07:44:01 PM PST 24
Finished Jan 24 07:44:03 PM PST 24
Peak memory 201260 kb
Host smart-3a6034f4-e9bc-4c5a-9db2-0023574fcf1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859182187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.3859182187
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.3926793592
Short name T515
Test name
Test status
Simulation time 1186225978 ps
CPU time 25.64 seconds
Started Jan 24 07:35:14 PM PST 24
Finished Jan 24 07:35:50 PM PST 24
Peak memory 201800 kb
Host smart-3ac3636c-ecc3-4b01-acc6-d58343f8ba3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926793592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.3926793592
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.365934278
Short name T22
Test name
Test status
Simulation time 86366229694 ps
CPU time 1214.36 seconds
Started Jan 24 06:19:24 PM PST 24
Finished Jan 24 06:39:39 PM PST 24
Peak memory 373676 kb
Host smart-a4048470-ae32-4fac-8daa-0257bca5529f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365934278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executabl
e.365934278
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.2391720379
Short name T387
Test name
Test status
Simulation time 703050104 ps
CPU time 5.12 seconds
Started Jan 24 06:19:26 PM PST 24
Finished Jan 24 06:19:32 PM PST 24
Peak memory 209984 kb
Host smart-6f2f7fcf-d4c9-4212-bc18-794bbcc43134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391720379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.2391720379
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.231717041
Short name T726
Test name
Test status
Simulation time 114628361 ps
CPU time 62.31 seconds
Started Jan 24 06:19:25 PM PST 24
Finished Jan 24 06:20:28 PM PST 24
Peak memory 323016 kb
Host smart-244af900-ecb4-4003-b4fa-6ad47b547c4d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231717041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.sram_ctrl_max_throughput.231717041
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3842275469
Short name T389
Test name
Test status
Simulation time 193208458 ps
CPU time 3.31 seconds
Started Jan 24 06:19:46 PM PST 24
Finished Jan 24 06:19:50 PM PST 24
Peak memory 211168 kb
Host smart-67f423af-4218-4c62-b83a-ed5d2684867a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842275469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.3842275469
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.1048599383
Short name T854
Test name
Test status
Simulation time 1903470291 ps
CPU time 9.44 seconds
Started Jan 24 06:19:46 PM PST 24
Finished Jan 24 06:19:56 PM PST 24
Peak memory 201788 kb
Host smart-8a563566-9f2d-4cd0-adf4-68e405e1a457
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048599383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.1048599383
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.81983091
Short name T64
Test name
Test status
Simulation time 9938975005 ps
CPU time 1182.04 seconds
Started Jan 24 07:48:48 PM PST 24
Finished Jan 24 08:08:31 PM PST 24
Peak memory 372668 kb
Host smart-1792905e-4013-4488-b350-07e954181fcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81983091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multipl
e_keys.81983091
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.189989455
Short name T896
Test name
Test status
Simulation time 7320404364 ps
CPU time 63.36 seconds
Started Jan 24 06:19:22 PM PST 24
Finished Jan 24 06:20:26 PM PST 24
Peak memory 323032 kb
Host smart-26951682-9a48-4f52-b349-46cb6e2495b5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189989455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.s
ram_ctrl_partial_access.189989455
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1302422836
Short name T657
Test name
Test status
Simulation time 10951754357 ps
CPU time 282.95 seconds
Started Jan 24 06:19:23 PM PST 24
Finished Jan 24 06:24:07 PM PST 24
Peak memory 201956 kb
Host smart-957a043f-e274-4bbb-b82a-e646c45d49ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302422836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.1302422836
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.2387455981
Short name T820
Test name
Test status
Simulation time 93679578 ps
CPU time 0.84 seconds
Started Jan 24 06:19:39 PM PST 24
Finished Jan 24 06:19:40 PM PST 24
Peak memory 201936 kb
Host smart-7e131f68-1845-4d78-9f14-63c19cfd1dd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387455981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2387455981
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.3672267141
Short name T806
Test name
Test status
Simulation time 29418941361 ps
CPU time 1054.26 seconds
Started Jan 24 06:19:33 PM PST 24
Finished Jan 24 06:37:08 PM PST 24
Peak memory 373516 kb
Host smart-912c4ece-9b20-4eea-80bf-cb50b02c3b81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672267141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3672267141
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.3681558755
Short name T307
Test name
Test status
Simulation time 162241981 ps
CPU time 3.1 seconds
Started Jan 24 06:19:01 PM PST 24
Finished Jan 24 06:19:10 PM PST 24
Peak memory 207988 kb
Host smart-b329e570-dcc2-4dd1-8654-d0ea0d8db2bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681558755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3681558755
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.2155650271
Short name T668
Test name
Test status
Simulation time 9471111895 ps
CPU time 1132.59 seconds
Started Jan 24 06:19:53 PM PST 24
Finished Jan 24 06:38:46 PM PST 24
Peak memory 364508 kb
Host smart-f733375a-e394-4e14-8ed3-542636391211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155650271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.sram_ctrl_stress_all.2155650271
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2382490272
Short name T677
Test name
Test status
Simulation time 10889559251 ps
CPU time 2422.16 seconds
Started Jan 24 06:19:48 PM PST 24
Finished Jan 24 07:00:11 PM PST 24
Peak memory 417744 kb
Host smart-c4428231-665b-4577-a3cb-21b82f572341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2382490272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.2382490272
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3841037593
Short name T228
Test name
Test status
Simulation time 12427199550 ps
CPU time 294.52 seconds
Started Jan 24 06:19:23 PM PST 24
Finished Jan 24 06:24:18 PM PST 24
Peak memory 201928 kb
Host smart-86dd41a2-967d-4981-83d2-76c237b9abb6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841037593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.3841037593
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2826577063
Short name T358
Test name
Test status
Simulation time 113905335 ps
CPU time 55.8 seconds
Started Jan 24 06:19:21 PM PST 24
Finished Jan 24 06:20:18 PM PST 24
Peak memory 305096 kb
Host smart-92d24c56-8c70-4b2f-acdb-13784e40f97e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826577063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2826577063
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1040695565
Short name T594
Test name
Test status
Simulation time 2270848261 ps
CPU time 875.77 seconds
Started Jan 24 06:39:27 PM PST 24
Finished Jan 24 06:54:03 PM PST 24
Peak memory 372732 kb
Host smart-580b9cda-1022-4b68-95be-e4bc176fc02f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040695565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.1040695565
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.846111462
Short name T944
Test name
Test status
Simulation time 26360941 ps
CPU time 0.68 seconds
Started Jan 24 06:21:17 PM PST 24
Finished Jan 24 06:21:20 PM PST 24
Peak memory 201712 kb
Host smart-14a3f615-7c1e-4dfe-9372-b30432f7fc2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846111462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.846111462
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.298390397
Short name T312
Test name
Test status
Simulation time 5481637413 ps
CPU time 85.32 seconds
Started Jan 24 06:20:09 PM PST 24
Finished Jan 24 06:21:35 PM PST 24
Peak memory 201828 kb
Host smart-e36d3faf-3022-4316-8cf7-08ba1052e3b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298390397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.
298390397
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.1812860929
Short name T592
Test name
Test status
Simulation time 42435040166 ps
CPU time 1033.64 seconds
Started Jan 24 06:20:42 PM PST 24
Finished Jan 24 06:37:56 PM PST 24
Peak memory 368576 kb
Host smart-c17e6de6-838c-49b1-aec8-6ef536799c7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812860929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.1812860929
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.2395925390
Short name T472
Test name
Test status
Simulation time 244554814 ps
CPU time 12.76 seconds
Started Jan 24 06:20:31 PM PST 24
Finished Jan 24 06:20:45 PM PST 24
Peak memory 250484 kb
Host smart-d6ab020a-eec7-44ca-a766-be776c3d7096
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395925390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.2395925390
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2181105934
Short name T211
Test name
Test status
Simulation time 186791257 ps
CPU time 3.12 seconds
Started Jan 24 06:20:55 PM PST 24
Finished Jan 24 06:21:00 PM PST 24
Peak memory 215288 kb
Host smart-f45a0f3d-cb7a-47af-a0f1-a4c7f92aa888
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181105934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.2181105934
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.3222758383
Short name T586
Test name
Test status
Simulation time 543627857 ps
CPU time 4.48 seconds
Started Jan 24 06:20:53 PM PST 24
Finished Jan 24 06:20:58 PM PST 24
Peak memory 201988 kb
Host smart-7bed13ce-bc07-47df-ab57-d13e7f75712b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222758383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.3222758383
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1759336632
Short name T286
Test name
Test status
Simulation time 2787364986 ps
CPU time 911.2 seconds
Started Jan 24 06:20:03 PM PST 24
Finished Jan 24 06:35:15 PM PST 24
Peak memory 368664 kb
Host smart-8126cb34-f11c-4c91-bc03-411c08d5ab3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759336632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1759336632
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.2886493042
Short name T467
Test name
Test status
Simulation time 930993321 ps
CPU time 119.59 seconds
Started Jan 24 06:20:24 PM PST 24
Finished Jan 24 06:22:24 PM PST 24
Peak memory 346988 kb
Host smart-b3d2ccad-aad6-41a2-98bb-3050a667dada
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886493042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.2886493042
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3596991949
Short name T810
Test name
Test status
Simulation time 24811888220 ps
CPU time 419.32 seconds
Started Jan 24 06:20:32 PM PST 24
Finished Jan 24 06:27:32 PM PST 24
Peak memory 201904 kb
Host smart-62b0d947-24d9-4e54-98a5-d8d28019b202
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596991949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.3596991949
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.81050448
Short name T649
Test name
Test status
Simulation time 44838917 ps
CPU time 0.88 seconds
Started Jan 24 06:20:52 PM PST 24
Finished Jan 24 06:20:54 PM PST 24
Peak memory 201952 kb
Host smart-c24accd0-41ef-48ff-8f25-0faeb473bf42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81050448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.81050448
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.18744955
Short name T227
Test name
Test status
Simulation time 17899795280 ps
CPU time 450.95 seconds
Started Jan 24 06:20:41 PM PST 24
Finished Jan 24 06:28:13 PM PST 24
Peak memory 372472 kb
Host smart-fe559449-7185-43dc-bd01-dcc403331ebe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18744955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.18744955
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.819205101
Short name T731
Test name
Test status
Simulation time 349221042 ps
CPU time 49.98 seconds
Started Jan 24 06:19:58 PM PST 24
Finished Jan 24 06:20:49 PM PST 24
Peak memory 306372 kb
Host smart-010aa240-c755-4c5c-8155-892742267b60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819205101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.819205101
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.4174047067
Short name T874
Test name
Test status
Simulation time 3260748754 ps
CPU time 2423.6 seconds
Started Jan 24 06:21:02 PM PST 24
Finished Jan 24 07:01:30 PM PST 24
Peak memory 420824 kb
Host smart-d0e686ac-1ab8-4851-9de3-c5af5026fc88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4174047067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.4174047067
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2072652049
Short name T867
Test name
Test status
Simulation time 10655961973 ps
CPU time 254.85 seconds
Started Jan 24 06:20:14 PM PST 24
Finished Jan 24 06:24:29 PM PST 24
Peak memory 201964 kb
Host smart-b5c6ea34-0e67-41d9-8575-9ffd0e7a6750
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072652049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.2072652049
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.569427727
Short name T551
Test name
Test status
Simulation time 269951605 ps
CPU time 12.91 seconds
Started Jan 24 06:20:34 PM PST 24
Finished Jan 24 06:20:48 PM PST 24
Peak memory 254904 kb
Host smart-76c30c0b-1ef6-4fee-b1d3-2d78b04e1625
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569427727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.569427727
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2162293964
Short name T786
Test name
Test status
Simulation time 13293433502 ps
CPU time 1518.42 seconds
Started Jan 24 06:21:52 PM PST 24
Finished Jan 24 06:47:12 PM PST 24
Peak memory 372684 kb
Host smart-edb33e80-81ae-4e33-ad10-94503dc52fae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162293964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2162293964
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.1769864872
Short name T869
Test name
Test status
Simulation time 33539454 ps
CPU time 0.64 seconds
Started Jan 24 06:29:56 PM PST 24
Finished Jan 24 06:29:57 PM PST 24
Peak memory 201592 kb
Host smart-2d0a912a-ae82-4957-a787-0f2b8622047b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769864872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.1769864872
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.1617953720
Short name T598
Test name
Test status
Simulation time 6683093607 ps
CPU time 34.62 seconds
Started Jan 24 06:21:31 PM PST 24
Finished Jan 24 06:22:06 PM PST 24
Peak memory 201932 kb
Host smart-55b9c245-97e7-4c39-b2af-4997608b571c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617953720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.1617953720
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.1955847274
Short name T276
Test name
Test status
Simulation time 15349289464 ps
CPU time 328.22 seconds
Started Jan 24 06:22:00 PM PST 24
Finished Jan 24 06:27:29 PM PST 24
Peak memory 363988 kb
Host smart-77d78894-ab28-4015-a1f5-d8a30521fa1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955847274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.1955847274
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.2889687041
Short name T491
Test name
Test status
Simulation time 3028623874 ps
CPU time 8.11 seconds
Started Jan 24 08:18:29 PM PST 24
Finished Jan 24 08:18:38 PM PST 24
Peak memory 210196 kb
Host smart-a9098625-9e97-487b-b0e5-81148ff305cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889687041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.2889687041
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.177833683
Short name T431
Test name
Test status
Simulation time 459837754 ps
CPU time 78.68 seconds
Started Jan 24 07:06:54 PM PST 24
Finished Jan 24 07:08:14 PM PST 24
Peak memory 339424 kb
Host smart-6f22d78e-ce39-4142-b9a8-ce4539490b03
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177833683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.sram_ctrl_max_throughput.177833683
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2167184050
Short name T861
Test name
Test status
Simulation time 176920267 ps
CPU time 5.58 seconds
Started Jan 24 06:22:23 PM PST 24
Finished Jan 24 06:22:29 PM PST 24
Peak memory 211144 kb
Host smart-ef66dfb0-834b-49ba-8451-e7bc7dfd2e3b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167184050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.2167184050
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.1833383473
Short name T758
Test name
Test status
Simulation time 285607325 ps
CPU time 4.65 seconds
Started Jan 24 07:27:25 PM PST 24
Finished Jan 24 07:27:30 PM PST 24
Peak memory 201944 kb
Host smart-a2f6babb-4fa3-4a7c-92ab-11c6adc6965d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833383473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.1833383473
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.1105044748
Short name T931
Test name
Test status
Simulation time 22554617256 ps
CPU time 560.97 seconds
Started Jan 24 07:59:01 PM PST 24
Finished Jan 24 08:08:22 PM PST 24
Peak memory 350652 kb
Host smart-5771b7ba-3cc0-4b56-b4bd-88e02de7837b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105044748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.1105044748
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.2846592034
Short name T535
Test name
Test status
Simulation time 998022378 ps
CPU time 19.28 seconds
Started Jan 24 06:21:33 PM PST 24
Finished Jan 24 06:21:56 PM PST 24
Peak memory 201816 kb
Host smart-a776a813-9554-44cc-9400-6e1e92a6a282
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846592034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.2846592034
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3209535494
Short name T641
Test name
Test status
Simulation time 7334286412 ps
CPU time 187.52 seconds
Started Jan 24 06:21:32 PM PST 24
Finished Jan 24 06:24:44 PM PST 24
Peak memory 201896 kb
Host smart-5ceb80d8-0c8b-4e60-846a-b0a69d3bfb8f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209535494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.3209535494
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.727254183
Short name T817
Test name
Test status
Simulation time 26595277 ps
CPU time 1.12 seconds
Started Jan 24 06:22:12 PM PST 24
Finished Jan 24 06:22:13 PM PST 24
Peak memory 202236 kb
Host smart-e6becd02-7d09-4331-89ae-0c6e3e21df94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727254183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.727254183
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.908894283
Short name T789
Test name
Test status
Simulation time 13443218426 ps
CPU time 1733.14 seconds
Started Jan 24 06:21:59 PM PST 24
Finished Jan 24 06:50:53 PM PST 24
Peak memory 372772 kb
Host smart-272a801d-5a09-4a31-bfc9-383cc2354640
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908894283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.908894283
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.1274156395
Short name T529
Test name
Test status
Simulation time 450648292 ps
CPU time 7.61 seconds
Started Jan 24 06:21:19 PM PST 24
Finished Jan 24 06:21:28 PM PST 24
Peak memory 201812 kb
Host smart-ff5f8bb1-dffc-46fa-a28e-b5b0632e4fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274156395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1274156395
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.69410156
Short name T444
Test name
Test status
Simulation time 30219593137 ps
CPU time 6299.52 seconds
Started Jan 24 06:22:29 PM PST 24
Finished Jan 24 08:07:30 PM PST 24
Peak memory 373636 kb
Host smart-320e1494-e082-47d3-9865-ff9991973cd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69410156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.sram_ctrl_stress_all.69410156
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3181871790
Short name T372
Test name
Test status
Simulation time 255373194 ps
CPU time 2193.04 seconds
Started Jan 24 06:22:30 PM PST 24
Finished Jan 24 06:59:04 PM PST 24
Peak memory 430356 kb
Host smart-6105b5cc-4f42-49e1-96c5-63c9d0bc3671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3181871790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3181871790
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4119274775
Short name T889
Test name
Test status
Simulation time 21104104188 ps
CPU time 148.72 seconds
Started Jan 24 07:58:24 PM PST 24
Finished Jan 24 08:00:54 PM PST 24
Peak memory 201940 kb
Host smart-b9fdea63-92eb-4b4e-858e-5a805b7b1397
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119274775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.4119274775
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1856698673
Short name T800
Test name
Test status
Simulation time 485708790 ps
CPU time 43.19 seconds
Started Jan 24 07:16:12 PM PST 24
Finished Jan 24 07:16:56 PM PST 24
Peak memory 309928 kb
Host smart-cfd65ae1-01ad-4a5e-ad9d-cf32b437dbd3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856698673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1856698673
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.53015188
Short name T590
Test name
Test status
Simulation time 2450148805 ps
CPU time 630.93 seconds
Started Jan 24 06:23:15 PM PST 24
Finished Jan 24 06:33:50 PM PST 24
Peak memory 364444 kb
Host smart-0dce785b-b5b2-4d1a-9781-ebea79e9771e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53015188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.sram_ctrl_access_during_key_req.53015188
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.3865862801
Short name T890
Test name
Test status
Simulation time 14287355 ps
CPU time 0.66 seconds
Started Jan 24 07:02:14 PM PST 24
Finished Jan 24 07:02:22 PM PST 24
Peak memory 201656 kb
Host smart-9af0354a-b6b8-4d08-865f-c47b2ff84b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865862801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.3865862801
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.3495325979
Short name T783
Test name
Test status
Simulation time 4404612746 ps
CPU time 74.88 seconds
Started Jan 24 06:22:48 PM PST 24
Finished Jan 24 06:24:03 PM PST 24
Peak memory 201888 kb
Host smart-c8ed9a4d-d3c4-4927-aeec-003d5691ee26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495325979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.3495325979
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.4229975029
Short name T914
Test name
Test status
Simulation time 2822599868 ps
CPU time 1495.66 seconds
Started Jan 24 06:45:27 PM PST 24
Finished Jan 24 07:10:23 PM PST 24
Peak memory 372692 kb
Host smart-97809293-20aa-4578-b16c-e3b4e4cb24f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229975029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.4229975029
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.281438264
Short name T888
Test name
Test status
Simulation time 1452245086 ps
CPU time 5.54 seconds
Started Jan 24 06:23:15 PM PST 24
Finished Jan 24 06:23:21 PM PST 24
Peak memory 201812 kb
Host smart-7461a005-4167-43b1-831f-7f2133b5b564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281438264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esc
alation.281438264
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.3157182257
Short name T929
Test name
Test status
Simulation time 131239792 ps
CPU time 94.01 seconds
Started Jan 24 06:23:13 PM PST 24
Finished Jan 24 06:24:48 PM PST 24
Peak memory 356636 kb
Host smart-1c94d74d-8c45-48a6-96c2-31d94e7a6ebb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157182257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.3157182257
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2843486043
Short name T495
Test name
Test status
Simulation time 1300001202 ps
CPU time 5.2 seconds
Started Jan 24 06:23:35 PM PST 24
Finished Jan 24 06:23:41 PM PST 24
Peak memory 214820 kb
Host smart-9bc2a8fc-f331-4e89-976b-a151b0c4e0ba
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843486043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.2843486043
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.2879675909
Short name T892
Test name
Test status
Simulation time 3161176521 ps
CPU time 10.84 seconds
Started Jan 24 06:23:36 PM PST 24
Finished Jan 24 06:23:48 PM PST 24
Peak memory 201988 kb
Host smart-775fc6bc-fd91-4343-b022-dbb02dd367b3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879675909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.2879675909
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.3607066892
Short name T618
Test name
Test status
Simulation time 8662671107 ps
CPU time 426.52 seconds
Started Jan 24 06:22:44 PM PST 24
Finished Jan 24 06:29:52 PM PST 24
Peak memory 346972 kb
Host smart-d2095a2b-4d8a-4294-b7b3-e5add2013422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607066892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.3607066892
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.3177864155
Short name T113
Test name
Test status
Simulation time 257741689 ps
CPU time 13.55 seconds
Started Jan 24 06:22:58 PM PST 24
Finished Jan 24 06:23:12 PM PST 24
Peak memory 201912 kb
Host smart-9454be55-a2a2-468e-b305-f0ada2fb8423
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177864155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.3177864155
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3177263373
Short name T292
Test name
Test status
Simulation time 7149856410 ps
CPU time 338.51 seconds
Started Jan 24 07:01:17 PM PST 24
Finished Jan 24 07:07:05 PM PST 24
Peak memory 201948 kb
Host smart-4211df60-010f-4870-81af-b659a655f18b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177263373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.3177263373
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2045773933
Short name T340
Test name
Test status
Simulation time 125426065 ps
CPU time 0.88 seconds
Started Jan 24 06:23:29 PM PST 24
Finished Jan 24 06:23:31 PM PST 24
Peak memory 201920 kb
Host smart-d221928d-0425-4910-8136-3f42ead8f32e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045773933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2045773933
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.2158500863
Short name T102
Test name
Test status
Simulation time 9572187212 ps
CPU time 269.48 seconds
Started Jan 24 06:23:21 PM PST 24
Finished Jan 24 06:27:51 PM PST 24
Peak memory 313040 kb
Host smart-0c0b8a06-4601-4362-abcb-e6d06989f345
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158500863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2158500863
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.3153615172
Short name T305
Test name
Test status
Simulation time 328908338 ps
CPU time 6.71 seconds
Started Jan 24 06:22:37 PM PST 24
Finished Jan 24 06:22:45 PM PST 24
Peak memory 201848 kb
Host smart-85c3e419-1227-45bd-afa6-584bc7c2ad69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153615172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3153615172
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.3318811600
Short name T371
Test name
Test status
Simulation time 7853091297 ps
CPU time 2590.88 seconds
Started Jan 24 09:37:58 PM PST 24
Finished Jan 24 10:21:10 PM PST 24
Peak memory 374736 kb
Host smart-57ee484f-b403-4398-9f8b-8a6b14b5daeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318811600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.3318811600
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3236409505
Short name T776
Test name
Test status
Simulation time 1497015830 ps
CPU time 2117.5 seconds
Started Jan 24 06:23:50 PM PST 24
Finished Jan 24 06:59:08 PM PST 24
Peak memory 439152 kb
Host smart-8e3b8a96-f135-48f5-b4c0-2e0a509a4984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3236409505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3236409505
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1235948789
Short name T229
Test name
Test status
Simulation time 6531120003 ps
CPU time 364.42 seconds
Started Jan 24 06:22:51 PM PST 24
Finished Jan 24 06:28:56 PM PST 24
Peak memory 201956 kb
Host smart-0c3afb38-d198-4380-b00f-818ce104b711
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235948789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.1235948789
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.284382203
Short name T549
Test name
Test status
Simulation time 1625061562 ps
CPU time 162.05 seconds
Started Jan 24 06:23:10 PM PST 24
Finished Jan 24 06:25:52 PM PST 24
Peak memory 366128 kb
Host smart-46cbecad-7410-4e90-95d1-b58895dd0e89
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284382203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_throughput_w_partial_write.284382203
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.925580572
Short name T792
Test name
Test status
Simulation time 3569879401 ps
CPU time 1081.97 seconds
Started Jan 24 06:24:46 PM PST 24
Finished Jan 24 06:42:49 PM PST 24
Peak memory 354260 kb
Host smart-c2d91e72-8e6b-4946-8035-2a61bb7f7bbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925580572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.sram_ctrl_access_during_key_req.925580572
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.2084087949
Short name T513
Test name
Test status
Simulation time 49675154 ps
CPU time 0.65 seconds
Started Jan 24 06:25:31 PM PST 24
Finished Jan 24 06:25:32 PM PST 24
Peak memory 201712 kb
Host smart-ba099d01-1ee1-49e9-81c6-2baff937f550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084087949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.2084087949
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.554299053
Short name T953
Test name
Test status
Simulation time 23259256411 ps
CPU time 28.8 seconds
Started Jan 24 06:24:21 PM PST 24
Finished Jan 24 06:24:51 PM PST 24
Peak memory 201848 kb
Host smart-ef4c2eeb-ae94-4549-97dc-37925bc2b8fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554299053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.
554299053
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.2428452187
Short name T314
Test name
Test status
Simulation time 2659656739 ps
CPU time 623.99 seconds
Started Jan 24 06:56:17 PM PST 24
Finished Jan 24 07:06:44 PM PST 24
Peak memory 369616 kb
Host smart-2e3790df-017b-4f58-8b16-0177e90c17d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428452187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.2428452187
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.2178152230
Short name T381
Test name
Test status
Simulation time 155920362 ps
CPU time 23.56 seconds
Started Jan 24 06:24:35 PM PST 24
Finished Jan 24 06:24:59 PM PST 24
Peak memory 275024 kb
Host smart-01cf1d01-950c-4e77-b109-bc1096e73044
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178152230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.2178152230
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.22717418
Short name T2
Test name
Test status
Simulation time 174456397 ps
CPU time 5.6 seconds
Started Jan 24 06:53:02 PM PST 24
Finished Jan 24 06:53:13 PM PST 24
Peak memory 215228 kb
Host smart-7db6d724-f17a-4802-a1c4-5f254f699100
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22717418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_mem_partial_access.22717418
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.3286836887
Short name T904
Test name
Test status
Simulation time 839096213 ps
CPU time 10.59 seconds
Started Jan 24 07:03:10 PM PST 24
Finished Jan 24 07:03:22 PM PST 24
Peak memory 201928 kb
Host smart-ce052eaf-7160-4d67-8811-104f74c2ef58
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286836887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.3286836887
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.1204829547
Short name T35
Test name
Test status
Simulation time 48174748917 ps
CPU time 680.83 seconds
Started Jan 24 07:37:50 PM PST 24
Finished Jan 24 07:49:13 PM PST 24
Peak memory 358436 kb
Host smart-efdde21f-12fd-4d82-9fe4-1982a1675e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204829547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.1204829547
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.3919682976
Short name T734
Test name
Test status
Simulation time 3968315730 ps
CPU time 19.27 seconds
Started Jan 24 06:24:28 PM PST 24
Finished Jan 24 06:24:48 PM PST 24
Peak memory 201980 kb
Host smart-0f70362b-4276-4671-9728-eb329c90acda
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919682976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.3919682976
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2918104882
Short name T753
Test name
Test status
Simulation time 12714516581 ps
CPU time 217.79 seconds
Started Jan 24 06:24:27 PM PST 24
Finished Jan 24 06:28:05 PM PST 24
Peak memory 201936 kb
Host smart-a2554bb6-a97b-47ca-81c6-7f416f938c96
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918104882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.2918104882
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.3189035973
Short name T819
Test name
Test status
Simulation time 28513477 ps
CPU time 0.85 seconds
Started Jan 24 07:04:53 PM PST 24
Finished Jan 24 07:04:55 PM PST 24
Peak memory 201936 kb
Host smart-0894c241-83e7-4b18-92c2-be9a553c7d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189035973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3189035973
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.1376707314
Short name T4
Test name
Test status
Simulation time 39171294085 ps
CPU time 1282.2 seconds
Started Jan 24 06:24:58 PM PST 24
Finished Jan 24 06:46:21 PM PST 24
Peak memory 374572 kb
Host smart-d9ac36aa-3b1a-4e9a-9cd8-a91d68eff7a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376707314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1376707314
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.1194121532
Short name T852
Test name
Test status
Simulation time 969891162 ps
CPU time 8.88 seconds
Started Jan 24 06:24:02 PM PST 24
Finished Jan 24 06:24:12 PM PST 24
Peak memory 201868 kb
Host smart-5e57151a-f929-4fb3-9569-874d981b708c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194121532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1194121532
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.273476960
Short name T346
Test name
Test status
Simulation time 6153649710 ps
CPU time 1583.38 seconds
Started Jan 24 06:25:30 PM PST 24
Finished Jan 24 06:51:54 PM PST 24
Peak memory 367588 kb
Host smart-392a0b2f-8cfa-4cef-9fc0-50ea0b0f4229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273476960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_stress_all.273476960
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3733798388
Short name T26
Test name
Test status
Simulation time 5215432871 ps
CPU time 3594.24 seconds
Started Jan 24 06:52:46 PM PST 24
Finished Jan 24 07:52:42 PM PST 24
Peak memory 404224 kb
Host smart-b064dcba-3569-42a6-a0bd-d784ba8b54bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3733798388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3733798388
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1840170879
Short name T693
Test name
Test status
Simulation time 1375543347 ps
CPU time 130.6 seconds
Started Jan 24 06:24:24 PM PST 24
Finished Jan 24 06:26:36 PM PST 24
Peak memory 201864 kb
Host smart-17664e19-a131-425e-8002-7a62d476df48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840170879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.1840170879
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2131922068
Short name T264
Test name
Test status
Simulation time 98522273 ps
CPU time 34.29 seconds
Started Jan 24 06:24:33 PM PST 24
Finished Jan 24 06:25:08 PM PST 24
Peak memory 287704 kb
Host smart-84f192bb-f1cd-47a3-97d0-433afc089dd7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131922068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2131922068
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.727329857
Short name T300
Test name
Test status
Simulation time 5127961365 ps
CPU time 489.46 seconds
Started Jan 24 06:48:01 PM PST 24
Finished Jan 24 06:56:14 PM PST 24
Peak memory 364468 kb
Host smart-9467eac8-77cf-4b3a-ab88-d28f72de196a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727329857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.sram_ctrl_access_during_key_req.727329857
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.2018282266
Short name T721
Test name
Test status
Simulation time 77957544 ps
CPU time 0.72 seconds
Started Jan 24 07:42:27 PM PST 24
Finished Jan 24 07:42:29 PM PST 24
Peak memory 201712 kb
Host smart-beb68f46-9358-4af9-aedd-1fe20a46a6aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018282266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.2018282266
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.3875333089
Short name T321
Test name
Test status
Simulation time 4176055815 ps
CPU time 64.57 seconds
Started Jan 24 06:25:38 PM PST 24
Finished Jan 24 06:26:45 PM PST 24
Peak memory 201924 kb
Host smart-a340ba04-debc-496f-ae9d-44528035b966
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875333089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.3875333089
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.3354962852
Short name T571
Test name
Test status
Simulation time 14763638239 ps
CPU time 1427.12 seconds
Started Jan 24 06:26:05 PM PST 24
Finished Jan 24 06:49:54 PM PST 24
Peak memory 372672 kb
Host smart-05de88b8-dfe8-471d-b191-560b2dea0819
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354962852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.3354962852
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3219471634
Short name T913
Test name
Test status
Simulation time 165468066 ps
CPU time 11.19 seconds
Started Jan 24 06:47:00 PM PST 24
Finished Jan 24 06:47:12 PM PST 24
Peak memory 243872 kb
Host smart-79c951cf-a4e3-4021-9746-415279291b3a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219471634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3219471634
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.4165454872
Short name T741
Test name
Test status
Simulation time 45493518 ps
CPU time 2.86 seconds
Started Jan 24 06:26:17 PM PST 24
Finished Jan 24 06:26:22 PM PST 24
Peak memory 211084 kb
Host smart-471ca8db-5944-46c7-abf5-086db826feca
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165454872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.4165454872
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.2036599875
Short name T773
Test name
Test status
Simulation time 1770276557 ps
CPU time 9.8 seconds
Started Jan 24 06:26:12 PM PST 24
Finished Jan 24 06:26:26 PM PST 24
Peak memory 201996 kb
Host smart-85704f4e-9af6-49af-96df-7a6a23f6c1ce
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036599875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.2036599875
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.590731244
Short name T696
Test name
Test status
Simulation time 10306404376 ps
CPU time 924.2 seconds
Started Jan 24 06:25:36 PM PST 24
Finished Jan 24 06:41:05 PM PST 24
Peak memory 370808 kb
Host smart-3c750e71-95d5-4600-a920-0b53fe12aa65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590731244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip
le_keys.590731244
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.2128645262
Short name T603
Test name
Test status
Simulation time 1391420667 ps
CPU time 7.96 seconds
Started Jan 24 07:36:39 PM PST 24
Finished Jan 24 07:36:48 PM PST 24
Peak memory 231456 kb
Host smart-543fa4c1-eef2-4ea3-8431-5aa94576ce97
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128645262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.2128645262
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1413022848
Short name T729
Test name
Test status
Simulation time 9406075197 ps
CPU time 329.1 seconds
Started Jan 24 06:25:49 PM PST 24
Finished Jan 24 06:31:19 PM PST 24
Peak memory 201964 kb
Host smart-41e7b391-1dd7-4855-890c-e9748e31131b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413022848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.1413022848
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.1502376745
Short name T329
Test name
Test status
Simulation time 87487530 ps
CPU time 0.87 seconds
Started Jan 24 06:26:13 PM PST 24
Finished Jan 24 06:26:18 PM PST 24
Peak memory 201920 kb
Host smart-2102d4c0-d45f-4a05-b2db-68b8a7ba27f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502376745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1502376745
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.1320536996
Short name T501
Test name
Test status
Simulation time 5534457563 ps
CPU time 837.96 seconds
Started Jan 24 06:26:05 PM PST 24
Finished Jan 24 06:40:04 PM PST 24
Peak memory 363444 kb
Host smart-106b4833-f770-4060-820b-60553cc36d0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320536996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1320536996
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.3231594882
Short name T527
Test name
Test status
Simulation time 6053099838 ps
CPU time 8.61 seconds
Started Jan 24 06:25:38 PM PST 24
Finished Jan 24 06:25:49 PM PST 24
Peak memory 201908 kb
Host smart-cd368a55-8035-442c-9097-ecb39a37f7a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231594882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3231594882
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.2097855726
Short name T754
Test name
Test status
Simulation time 27192037367 ps
CPU time 1463.47 seconds
Started Jan 24 06:26:26 PM PST 24
Finished Jan 24 06:50:50 PM PST 24
Peak memory 381392 kb
Host smart-b75a169a-f573-462a-8e45-64f363fb5161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097855726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.2097855726
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.959915234
Short name T926
Test name
Test status
Simulation time 7844306865 ps
CPU time 5101.06 seconds
Started Jan 24 06:26:19 PM PST 24
Finished Jan 24 07:51:22 PM PST 24
Peak memory 450116 kb
Host smart-971d6e51-a78c-475c-813b-760efcfe1511
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=959915234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.959915234
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3346715878
Short name T710
Test name
Test status
Simulation time 2796820802 ps
CPU time 254.94 seconds
Started Jan 24 07:58:57 PM PST 24
Finished Jan 24 08:03:12 PM PST 24
Peak memory 201948 kb
Host smart-a17d140f-aa88-4ba8-a4d7-2c94eec8f19f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346715878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.3346715878
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1558921669
Short name T336
Test name
Test status
Simulation time 237321134 ps
CPU time 8.04 seconds
Started Jan 24 06:25:58 PM PST 24
Finished Jan 24 06:26:07 PM PST 24
Peak memory 235588 kb
Host smart-a65a8f41-22a1-4b56-88b1-c1c8042157bd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558921669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1558921669
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3541862439
Short name T975
Test name
Test status
Simulation time 101782677 ps
CPU time 17.59 seconds
Started Jan 24 06:43:34 PM PST 24
Finished Jan 24 06:43:53 PM PST 24
Peak memory 254160 kb
Host smart-fa52bbd3-a1c3-4a2e-92d5-935b38ac7598
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541862439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.3541862439
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.4184427654
Short name T577
Test name
Test status
Simulation time 17428079 ps
CPU time 0.65 seconds
Started Jan 24 06:27:50 PM PST 24
Finished Jan 24 06:27:51 PM PST 24
Peak memory 200664 kb
Host smart-ebb9d18c-6b67-420f-971a-3b4d90e2ef4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184427654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.4184427654
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.741375999
Short name T828
Test name
Test status
Simulation time 3415273458 ps
CPU time 57.37 seconds
Started Jan 24 06:26:54 PM PST 24
Finished Jan 24 06:27:51 PM PST 24
Peak memory 201832 kb
Host smart-f34cbc12-2d7e-413e-82b0-5fa8b42d58c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741375999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.
741375999
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.2417511482
Short name T343
Test name
Test status
Simulation time 6114443916 ps
CPU time 117.12 seconds
Started Jan 24 06:27:18 PM PST 24
Finished Jan 24 06:29:16 PM PST 24
Peak memory 293944 kb
Host smart-2a463013-7c28-40f6-b32e-585b242c7c0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417511482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.2417511482
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.1389573934
Short name T489
Test name
Test status
Simulation time 637077516 ps
CPU time 7.67 seconds
Started Jan 24 06:27:10 PM PST 24
Finished Jan 24 06:27:18 PM PST 24
Peak memory 201828 kb
Host smart-7a602074-288d-485e-bb79-6bdaf4e5a85a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389573934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.1389573934
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.998844867
Short name T742
Test name
Test status
Simulation time 295329271 ps
CPU time 17.33 seconds
Started Jan 24 06:26:57 PM PST 24
Finished Jan 24 06:27:15 PM PST 24
Peak memory 267132 kb
Host smart-7f9eb6a0-208c-4c00-adde-9c3f849c1745
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998844867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.sram_ctrl_max_throughput.998844867
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3082021765
Short name T34
Test name
Test status
Simulation time 45194727 ps
CPU time 2.94 seconds
Started Jan 24 08:03:35 PM PST 24
Finished Jan 24 08:03:44 PM PST 24
Peak memory 214704 kb
Host smart-761a2f3d-ca6c-4e1c-8553-5518e0159681
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082021765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.3082021765
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.341742884
Short name T359
Test name
Test status
Simulation time 360921345 ps
CPU time 5.5 seconds
Started Jan 24 06:27:30 PM PST 24
Finished Jan 24 06:27:36 PM PST 24
Peak memory 201904 kb
Host smart-4a7e4938-ba92-4ef1-bff4-d48e82064c3e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341742884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl
_mem_walk.341742884
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.2628873123
Short name T700
Test name
Test status
Simulation time 9686202711 ps
CPU time 289.44 seconds
Started Jan 24 06:26:46 PM PST 24
Finished Jan 24 06:31:36 PM PST 24
Peak memory 336500 kb
Host smart-279f3048-8eaf-4b95-9009-c2c4d16a5143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628873123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.2628873123
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.2315161692
Short name T502
Test name
Test status
Simulation time 122235718 ps
CPU time 3.2 seconds
Started Jan 24 07:28:12 PM PST 24
Finished Jan 24 07:28:16 PM PST 24
Peak memory 201888 kb
Host smart-93f37a83-c170-48e3-a2b1-dafdbc06677a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315161692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.2315161692
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2558655267
Short name T122
Test name
Test status
Simulation time 26066302196 ps
CPU time 266.58 seconds
Started Jan 24 06:26:54 PM PST 24
Finished Jan 24 06:31:21 PM PST 24
Peak memory 201920 kb
Host smart-f1efab22-4124-41a5-b126-9a3534129e0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558655267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.2558655267
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.2796566932
Short name T902
Test name
Test status
Simulation time 53951234 ps
CPU time 1.13 seconds
Started Jan 24 06:27:31 PM PST 24
Finished Jan 24 06:27:32 PM PST 24
Peak memory 202196 kb
Host smart-33f043a2-9dbc-42bf-bdd2-02c707260e5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796566932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2796566932
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.1082529974
Short name T862
Test name
Test status
Simulation time 7378660687 ps
CPU time 531.41 seconds
Started Jan 24 06:27:25 PM PST 24
Finished Jan 24 06:36:17 PM PST 24
Peak memory 365488 kb
Host smart-8d427920-a53d-438f-9b07-594a996b2b51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082529974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1082529974
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.2811940793
Short name T599
Test name
Test status
Simulation time 97764221 ps
CPU time 28.16 seconds
Started Jan 24 06:26:36 PM PST 24
Finished Jan 24 06:27:04 PM PST 24
Peak memory 288976 kb
Host smart-cfd5490e-6fae-4e4a-92cb-8b9558675ea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811940793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2811940793
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.3221723693
Short name T868
Test name
Test status
Simulation time 508650899324 ps
CPU time 2847.8 seconds
Started Jan 24 06:27:51 PM PST 24
Finished Jan 24 07:15:20 PM PST 24
Peak memory 375772 kb
Host smart-8bc73b22-4f10-4c62-93d5-316ee864b5f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221723693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.3221723693
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.438045922
Short name T391
Test name
Test status
Simulation time 12231186580 ps
CPU time 296.65 seconds
Started Jan 24 06:26:52 PM PST 24
Finished Jan 24 06:31:50 PM PST 24
Peak memory 201768 kb
Host smart-6da53f48-2c1e-477e-a33d-8939c62dd0ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438045922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_stress_pipeline.438045922
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2016674216
Short name T600
Test name
Test status
Simulation time 661944121 ps
CPU time 63.54 seconds
Started Jan 24 06:27:08 PM PST 24
Finished Jan 24 06:28:12 PM PST 24
Peak memory 314268 kb
Host smart-c1c4fca5-ccc3-4e9b-81db-493f36f7eace
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016674216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2016674216
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1383253331
Short name T559
Test name
Test status
Simulation time 3710998234 ps
CPU time 1328.11 seconds
Started Jan 24 06:40:12 PM PST 24
Finished Jan 24 07:02:21 PM PST 24
Peak memory 372688 kb
Host smart-38c78b01-7b6f-4506-ab92-9cf48a3c14fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383253331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.1383253331
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.3693492053
Short name T315
Test name
Test status
Simulation time 13218355 ps
CPU time 0.64 seconds
Started Jan 24 06:28:56 PM PST 24
Finished Jan 24 06:28:57 PM PST 24
Peak memory 201600 kb
Host smart-581fbedd-0763-423c-98ee-aead55cc3020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693492053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.3693492053
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.2834981503
Short name T743
Test name
Test status
Simulation time 6074339018 ps
CPU time 34.59 seconds
Started Jan 24 06:28:16 PM PST 24
Finished Jan 24 06:28:53 PM PST 24
Peak memory 201876 kb
Host smart-8aac0a90-30df-45f7-9af7-c4f7a737f0a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834981503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.2834981503
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.1469035412
Short name T519
Test name
Test status
Simulation time 36756313686 ps
CPU time 538.97 seconds
Started Jan 24 06:28:25 PM PST 24
Finished Jan 24 06:37:27 PM PST 24
Peak memory 372616 kb
Host smart-6497a7ee-4bde-4486-a07b-c97fdf7042b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469035412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.1469035412
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.3409165279
Short name T429
Test name
Test status
Simulation time 160916966 ps
CPU time 20.88 seconds
Started Jan 24 06:28:23 PM PST 24
Finished Jan 24 06:28:45 PM PST 24
Peak memory 270228 kb
Host smart-82458655-5de8-4f91-8046-ad9909954d88
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409165279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.3409165279
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2085073280
Short name T887
Test name
Test status
Simulation time 119961114 ps
CPU time 5.04 seconds
Started Jan 24 06:28:48 PM PST 24
Finished Jan 24 06:28:54 PM PST 24
Peak memory 210124 kb
Host smart-228006e9-3236-4dd0-8972-78fb6ed59025
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085073280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.2085073280
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.2952814207
Short name T378
Test name
Test status
Simulation time 882624469 ps
CPU time 9.83 seconds
Started Jan 24 06:38:32 PM PST 24
Finished Jan 24 06:38:43 PM PST 24
Peak memory 202008 kb
Host smart-b308fb5d-6262-46a8-843c-fe7da085314d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952814207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.2952814207
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.2182904096
Short name T492
Test name
Test status
Simulation time 53952659903 ps
CPU time 769.09 seconds
Started Jan 24 07:16:01 PM PST 24
Finished Jan 24 07:28:51 PM PST 24
Peak memory 373636 kb
Host smart-21df3a1e-43f3-4f83-a80c-65d0ed92271e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182904096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.2182904096
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.4293869898
Short name T365
Test name
Test status
Simulation time 995974522 ps
CPU time 8.45 seconds
Started Jan 24 06:28:15 PM PST 24
Finished Jan 24 06:28:27 PM PST 24
Peak memory 201832 kb
Host smart-f76a2909-9e58-4012-bd2a-fdc0eed923a4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293869898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.4293869898
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3705630978
Short name T127
Test name
Test status
Simulation time 16577334851 ps
CPU time 277.93 seconds
Started Jan 24 06:28:21 PM PST 24
Finished Jan 24 06:33:02 PM PST 24
Peak memory 201960 kb
Host smart-7177afc2-7eb9-4ba1-beab-914af05ebbdb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705630978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.3705630978
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.2680236332
Short name T294
Test name
Test status
Simulation time 288111807 ps
CPU time 0.9 seconds
Started Jan 24 06:28:43 PM PST 24
Finished Jan 24 06:28:45 PM PST 24
Peak memory 201940 kb
Host smart-cdd26876-ca9a-448d-863f-afa3deb83324
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680236332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2680236332
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.1042668189
Short name T652
Test name
Test status
Simulation time 11907632479 ps
CPU time 941.76 seconds
Started Jan 24 06:28:35 PM PST 24
Finished Jan 24 06:44:18 PM PST 24
Peak memory 361500 kb
Host smart-71491887-b944-4064-ac52-c33a5b6e4e5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042668189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1042668189
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.2721342001
Short name T130
Test name
Test status
Simulation time 2535891020 ps
CPU time 92.84 seconds
Started Jan 24 06:27:48 PM PST 24
Finished Jan 24 06:29:22 PM PST 24
Peak memory 349080 kb
Host smart-b303de32-691d-4046-b09b-322b1d2f2c82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721342001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2721342001
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.1166704687
Short name T608
Test name
Test status
Simulation time 88997804096 ps
CPU time 2982.78 seconds
Started Jan 24 06:28:55 PM PST 24
Finished Jan 24 07:18:38 PM PST 24
Peak memory 381900 kb
Host smart-c143e476-8deb-4961-8eea-17bb65bbc544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166704687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.1166704687
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2500597174
Short name T942
Test name
Test status
Simulation time 2248352908 ps
CPU time 4324.5 seconds
Started Jan 24 06:28:56 PM PST 24
Finished Jan 24 07:41:02 PM PST 24
Peak memory 419484 kb
Host smart-b86140fd-ea39-4e91-ac41-1b674646fa27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2500597174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2500597174
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.4052839443
Short name T249
Test name
Test status
Simulation time 1471676122 ps
CPU time 119.08 seconds
Started Jan 24 06:28:15 PM PST 24
Finished Jan 24 06:30:18 PM PST 24
Peak memory 201892 kb
Host smart-a9d9f569-56a3-4919-849b-f40482f029e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052839443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.4052839443
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3086389056
Short name T573
Test name
Test status
Simulation time 73726044 ps
CPU time 11.96 seconds
Started Jan 24 06:28:22 PM PST 24
Finished Jan 24 06:28:36 PM PST 24
Peak memory 250924 kb
Host smart-a92cb3c9-f001-43c5-97eb-76f39a952299
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086389056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3086389056
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.2832916133
Short name T879
Test name
Test status
Simulation time 13540376829 ps
CPU time 2317.09 seconds
Started Jan 24 05:47:01 PM PST 24
Finished Jan 24 06:25:39 PM PST 24
Peak memory 373724 kb
Host smart-3cf585ee-bc79-4f18-b0f4-28e03cf98dd1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832916133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.2832916133
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.3500734159
Short name T474
Test name
Test status
Simulation time 12316995 ps
CPU time 0.74 seconds
Started Jan 24 06:08:02 PM PST 24
Finished Jan 24 06:08:03 PM PST 24
Peak memory 200808 kb
Host smart-91aba68c-1daa-420f-b5bb-dde03c77f7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500734159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.3500734159
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.1275811535
Short name T537
Test name
Test status
Simulation time 9303028619 ps
CPU time 1442.57 seconds
Started Jan 24 05:52:43 PM PST 24
Finished Jan 24 06:16:47 PM PST 24
Peak memory 371684 kb
Host smart-90ec6506-d95a-4b32-ae19-a4a72e9e9cd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275811535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.1275811535
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.3924112473
Short name T259
Test name
Test status
Simulation time 603361826 ps
CPU time 4.94 seconds
Started Jan 24 05:47:02 PM PST 24
Finished Jan 24 05:47:07 PM PST 24
Peak memory 210040 kb
Host smart-ee4a34b6-1373-423b-81a5-4750e483d1c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924112473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.3924112473
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.250029090
Short name T210
Test name
Test status
Simulation time 162039488 ps
CPU time 4.17 seconds
Started Jan 24 05:51:52 PM PST 24
Finished Jan 24 05:51:57 PM PST 24
Peak memory 218244 kb
Host smart-adb7b31c-f4df-443e-ad5b-7c9ede3d24bf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250029090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.sram_ctrl_max_throughput.250029090
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1324017439
Short name T485
Test name
Test status
Simulation time 700885869 ps
CPU time 5.49 seconds
Started Jan 24 05:47:40 PM PST 24
Finished Jan 24 05:47:46 PM PST 24
Peak memory 210920 kb
Host smart-51b098c0-9677-4dd5-b35c-858bac99ecd9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324017439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.1324017439
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.4031952769
Short name T442
Test name
Test status
Simulation time 76208556 ps
CPU time 4.35 seconds
Started Jan 24 05:47:40 PM PST 24
Finished Jan 24 05:47:45 PM PST 24
Peak memory 201992 kb
Host smart-0baf1918-438a-488a-b86f-afeaac497833
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031952769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.4031952769
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.765644759
Short name T918
Test name
Test status
Simulation time 947404800 ps
CPU time 182.02 seconds
Started Jan 24 05:46:51 PM PST 24
Finished Jan 24 05:49:54 PM PST 24
Peak memory 371560 kb
Host smart-3c2df2e6-4328-46fa-97fb-0790bbb1274d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765644759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl
e_keys.765644759
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.556083815
Short name T653
Test name
Test status
Simulation time 612338365 ps
CPU time 17.87 seconds
Started Jan 24 05:46:57 PM PST 24
Finished Jan 24 05:47:15 PM PST 24
Peak memory 201884 kb
Host smart-c3619c23-51d4-4035-9225-35b81f396c26
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556083815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr
am_ctrl_partial_access.556083815
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.961496680
Short name T399
Test name
Test status
Simulation time 51155507859 ps
CPU time 347.03 seconds
Started Jan 24 05:46:59 PM PST 24
Finished Jan 24 05:52:46 PM PST 24
Peak memory 201740 kb
Host smart-666038ba-c65b-4e8a-bf20-1965b38ccda7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961496680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.sram_ctrl_partial_access_b2b.961496680
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.3224527891
Short name T685
Test name
Test status
Simulation time 30375498 ps
CPU time 0.83 seconds
Started Jan 24 05:47:41 PM PST 24
Finished Jan 24 05:47:42 PM PST 24
Peak memory 201772 kb
Host smart-f163cd30-08ee-48e7-bf91-e4bc80e36181
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224527891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3224527891
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.2111187711
Short name T295
Test name
Test status
Simulation time 9496743842 ps
CPU time 1181.28 seconds
Started Jan 24 05:47:14 PM PST 24
Finished Jan 24 06:06:56 PM PST 24
Peak memory 366560 kb
Host smart-471703cf-d9b1-4961-b2f9-9b62d7ccafb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111187711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.2111187711
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.1077748849
Short name T19
Test name
Test status
Simulation time 645363434 ps
CPU time 3.06 seconds
Started Jan 24 06:13:34 PM PST 24
Finished Jan 24 06:13:37 PM PST 24
Peak memory 223812 kb
Host smart-6a3241c3-6024-41f6-a0be-c3902eb377b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077748849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.1077748849
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.919883105
Short name T425
Test name
Test status
Simulation time 70676485 ps
CPU time 11.26 seconds
Started Jan 24 06:13:38 PM PST 24
Finished Jan 24 06:13:49 PM PST 24
Peak memory 245564 kb
Host smart-718362ac-7538-46fe-927c-1c4f137399f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919883105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.919883105
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.236875798
Short name T808
Test name
Test status
Simulation time 162292130095 ps
CPU time 8222.78 seconds
Started Jan 24 07:11:53 PM PST 24
Finished Jan 24 09:29:00 PM PST 24
Peak memory 382916 kb
Host smart-e91f5c2a-9842-43e3-83ac-61047f6147c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236875798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_stress_all.236875798
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1886154721
Short name T521
Test name
Test status
Simulation time 1531669294 ps
CPU time 3922.74 seconds
Started Jan 24 06:09:45 PM PST 24
Finished Jan 24 07:15:09 PM PST 24
Peak memory 403052 kb
Host smart-53aa3197-6f43-4ffe-b063-e6ffc543f478
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1886154721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1886154721
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.428824729
Short name T712
Test name
Test status
Simulation time 1685338104 ps
CPU time 159.97 seconds
Started Jan 24 05:47:00 PM PST 24
Finished Jan 24 05:49:40 PM PST 24
Peak memory 201888 kb
Host smart-419464ff-8e97-43d6-a174-702a64386b94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428824729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_stress_pipeline.428824729
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3024921379
Short name T795
Test name
Test status
Simulation time 508080924 ps
CPU time 90.8 seconds
Started Jan 24 05:47:02 PM PST 24
Finished Jan 24 05:48:33 PM PST 24
Peak memory 341628 kb
Host smart-a3dbd0fc-1da3-46a9-8c34-f2b3914cd1ec
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024921379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3024921379
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1111366999
Short name T323
Test name
Test status
Simulation time 3072963198 ps
CPU time 858.92 seconds
Started Jan 24 07:13:21 PM PST 24
Finished Jan 24 07:27:41 PM PST 24
Peak memory 357400 kb
Host smart-962738a0-6524-490c-8158-e6199999e2a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111366999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.1111366999
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.3944515030
Short name T897
Test name
Test status
Simulation time 45632624 ps
CPU time 0.67 seconds
Started Jan 24 06:42:26 PM PST 24
Finished Jan 24 06:42:27 PM PST 24
Peak memory 200784 kb
Host smart-60859bf3-11b6-4f5a-a21a-b583a8677eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944515030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.3944515030
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.1306363939
Short name T813
Test name
Test status
Simulation time 1088831749 ps
CPU time 24.41 seconds
Started Jan 24 06:29:01 PM PST 24
Finished Jan 24 06:29:26 PM PST 24
Peak memory 201856 kb
Host smart-f12d0c8a-4bf1-487b-a983-70ebcdc54b04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306363939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.1306363939
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.2534799668
Short name T316
Test name
Test status
Simulation time 2917505459 ps
CPU time 703.89 seconds
Started Jan 24 06:29:29 PM PST 24
Finished Jan 24 06:41:13 PM PST 24
Peak memory 361432 kb
Host smart-04b3a730-8cde-4acf-b1f9-5cc572795ead
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534799668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.2534799668
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.266382134
Short name T643
Test name
Test status
Simulation time 8387668664 ps
CPU time 7.86 seconds
Started Jan 24 07:30:55 PM PST 24
Finished Jan 24 07:31:04 PM PST 24
Peak memory 201912 kb
Host smart-49a50ae7-48d8-41b1-8844-e4c8b5196c11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266382134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc
alation.266382134
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.212917945
Short name T648
Test name
Test status
Simulation time 123472795 ps
CPU time 3.05 seconds
Started Jan 24 06:29:46 PM PST 24
Finished Jan 24 06:29:50 PM PST 24
Peak memory 211028 kb
Host smart-54114e16-6e8b-4bbb-8e8b-bccc943407c9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212917945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.sram_ctrl_mem_partial_access.212917945
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.1797680470
Short name T940
Test name
Test status
Simulation time 4112807175 ps
CPU time 11 seconds
Started Jan 24 06:29:42 PM PST 24
Finished Jan 24 06:29:53 PM PST 24
Peak memory 202032 kb
Host smart-c0dc4fd2-e15d-4ae6-95b0-e763a696975c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797680470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.1797680470
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.1847949897
Short name T370
Test name
Test status
Simulation time 91600396155 ps
CPU time 1451.36 seconds
Started Jan 24 07:52:07 PM PST 24
Finished Jan 24 08:16:20 PM PST 24
Peak memory 364464 kb
Host smart-5f9e156a-28eb-4884-a40f-cc9d7a81e2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847949897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.1847949897
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.185792400
Short name T550
Test name
Test status
Simulation time 603371716 ps
CPU time 13.99 seconds
Started Jan 24 06:34:49 PM PST 24
Finished Jan 24 06:35:03 PM PST 24
Peak memory 201896 kb
Host smart-b01a9a3f-6917-4b61-97f4-db9c0a55391d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185792400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s
ram_ctrl_partial_access.185792400
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4023167436
Short name T855
Test name
Test status
Simulation time 47870323598 ps
CPU time 276.33 seconds
Started Jan 24 06:45:07 PM PST 24
Finished Jan 24 06:49:44 PM PST 24
Peak memory 201892 kb
Host smart-aa56f029-d16c-4e9f-ac8e-9802c79966dc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023167436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.4023167436
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.858371378
Short name T506
Test name
Test status
Simulation time 53626023 ps
CPU time 0.85 seconds
Started Jan 24 06:29:34 PM PST 24
Finished Jan 24 06:29:36 PM PST 24
Peak memory 201852 kb
Host smart-fb3059ac-c600-4624-9d13-4ef3ee1b5cd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858371378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.858371378
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3802419112
Short name T496
Test name
Test status
Simulation time 5175872098 ps
CPU time 282.1 seconds
Started Jan 24 06:29:35 PM PST 24
Finished Jan 24 06:34:18 PM PST 24
Peak memory 365244 kb
Host smart-524ac033-f3c7-41e6-b990-71159d56de32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802419112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3802419112
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.2425100561
Short name T63
Test name
Test status
Simulation time 389043613 ps
CPU time 38.71 seconds
Started Jan 24 06:29:00 PM PST 24
Finished Jan 24 06:29:40 PM PST 24
Peak memory 294328 kb
Host smart-791f3833-854c-463e-9eb3-47cd74b3622a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425100561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2425100561
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.2536963684
Short name T476
Test name
Test status
Simulation time 57262114698 ps
CPU time 3801.59 seconds
Started Jan 24 06:29:51 PM PST 24
Finished Jan 24 07:33:14 PM PST 24
Peak memory 374708 kb
Host smart-baeb13bb-3cd1-4266-b4df-3318eaa4de69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536963684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.2536963684
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2600937920
Short name T885
Test name
Test status
Simulation time 11888526271 ps
CPU time 4067.34 seconds
Started Jan 24 06:29:51 PM PST 24
Finished Jan 24 07:37:39 PM PST 24
Peak memory 448780 kb
Host smart-08a89ab1-a851-40ea-8356-f5c8bdf79f14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2600937920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2600937920
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3973089124
Short name T121
Test name
Test status
Simulation time 3640758208 ps
CPU time 302.41 seconds
Started Jan 24 06:29:13 PM PST 24
Finished Jan 24 06:34:16 PM PST 24
Peak memory 201916 kb
Host smart-e4d89806-9208-4d46-b0f1-4043829f3452
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973089124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.3973089124
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1757025202
Short name T763
Test name
Test status
Simulation time 41106380 ps
CPU time 1.96 seconds
Started Jan 24 06:40:51 PM PST 24
Finished Jan 24 06:40:54 PM PST 24
Peak memory 210064 kb
Host smart-177e89d8-f7ab-4b0e-86d8-00b87374d402
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757025202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1757025202
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.4200988664
Short name T413
Test name
Test status
Simulation time 5509615741 ps
CPU time 283.07 seconds
Started Jan 24 06:30:29 PM PST 24
Finished Jan 24 06:35:13 PM PST 24
Peak memory 364324 kb
Host smart-771060fb-6f01-4cfa-ada8-3afaf310e2e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200988664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.4200988664
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.3960525681
Short name T477
Test name
Test status
Simulation time 32573916 ps
CPU time 0.63 seconds
Started Jan 24 06:31:00 PM PST 24
Finished Jan 24 06:31:01 PM PST 24
Peak memory 201712 kb
Host smart-008280ec-e253-48d3-8b61-d1d97e871d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960525681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.3960525681
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.2140985754
Short name T947
Test name
Test status
Simulation time 1476725103 ps
CPU time 45.76 seconds
Started Jan 24 06:30:02 PM PST 24
Finished Jan 24 06:30:48 PM PST 24
Peak memory 201860 kb
Host smart-d372afc6-50f7-404d-9721-9172ae4d2286
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140985754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.2140985754
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.3410058929
Short name T670
Test name
Test status
Simulation time 10239949493 ps
CPU time 1023.08 seconds
Started Jan 24 06:30:37 PM PST 24
Finished Jan 24 06:47:44 PM PST 24
Peak memory 365560 kb
Host smart-4876ea94-ed50-4434-8cf4-81dbd0da5038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410058929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.3410058929
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.1438534245
Short name T825
Test name
Test status
Simulation time 1896595589 ps
CPU time 13.9 seconds
Started Jan 24 08:00:26 PM PST 24
Finished Jan 24 08:00:42 PM PST 24
Peak memory 210116 kb
Host smart-0cdb5c6a-f7e4-43e7-b71f-426a41f5ed54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438534245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.1438534245
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.901369171
Short name T361
Test name
Test status
Simulation time 383086874 ps
CPU time 5.95 seconds
Started Jan 24 08:39:16 PM PST 24
Finished Jan 24 08:39:23 PM PST 24
Peak memory 227132 kb
Host smart-e28f478e-b31e-4654-b736-7a5b4d458103
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901369171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.sram_ctrl_max_throughput.901369171
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.4254959197
Short name T713
Test name
Test status
Simulation time 100689899 ps
CPU time 2.97 seconds
Started Jan 24 06:30:52 PM PST 24
Finished Jan 24 06:30:55 PM PST 24
Peak memory 210404 kb
Host smart-befed7f1-afe4-4552-b309-2e87b7f0d063
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254959197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.4254959197
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.2128431424
Short name T706
Test name
Test status
Simulation time 2262737562 ps
CPU time 9.82 seconds
Started Jan 24 06:30:51 PM PST 24
Finished Jan 24 06:31:01 PM PST 24
Peak memory 201996 kb
Host smart-95c0b7a2-d47d-4763-98cb-7a7813c34391
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128431424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.2128431424
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.3815515340
Short name T213
Test name
Test status
Simulation time 40226632839 ps
CPU time 1990.28 seconds
Started Jan 24 06:30:02 PM PST 24
Finished Jan 24 07:03:13 PM PST 24
Peak memory 368676 kb
Host smart-dabd610c-5a2b-4225-9976-76829820031b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815515340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.3815515340
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.249576506
Short name T567
Test name
Test status
Simulation time 185393358 ps
CPU time 3.44 seconds
Started Jan 24 06:30:06 PM PST 24
Finished Jan 24 06:30:10 PM PST 24
Peak memory 201628 kb
Host smart-d8afc559-c82e-4e4b-9b74-65c73ce37fba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249576506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s
ram_ctrl_partial_access.249576506
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3846147654
Short name T848
Test name
Test status
Simulation time 22750936985 ps
CPU time 252.36 seconds
Started Jan 24 06:30:14 PM PST 24
Finished Jan 24 06:34:30 PM PST 24
Peak memory 201904 kb
Host smart-7e9f5212-080e-4f60-b088-48a0d0677b40
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846147654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.3846147654
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.3446386878
Short name T132
Test name
Test status
Simulation time 92217251 ps
CPU time 0.84 seconds
Started Jan 24 06:30:51 PM PST 24
Finished Jan 24 06:30:52 PM PST 24
Peak memory 202024 kb
Host smart-8932cc0c-ec91-4f48-a855-fd4993444d1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446386878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3446386878
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.4229389856
Short name T106
Test name
Test status
Simulation time 14214691444 ps
CPU time 728.93 seconds
Started Jan 24 06:30:37 PM PST 24
Finished Jan 24 06:42:50 PM PST 24
Peak memory 364772 kb
Host smart-58a6fa04-1427-486a-a9eb-bafafa315fe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229389856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.4229389856
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.1926354461
Short name T765
Test name
Test status
Simulation time 730562726 ps
CPU time 14.34 seconds
Started Jan 24 06:29:56 PM PST 24
Finished Jan 24 06:30:11 PM PST 24
Peak memory 201820 kb
Host smart-bed63788-e47a-483a-a181-4d908efa9d13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926354461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1926354461
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.3770469498
Short name T762
Test name
Test status
Simulation time 243456202663 ps
CPU time 4497.01 seconds
Started Jan 24 07:02:25 PM PST 24
Finished Jan 24 08:17:26 PM PST 24
Peak memory 374484 kb
Host smart-527f45df-747b-4aff-8d77-7aff9e70f7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770469498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.3770469498
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.650210932
Short name T522
Test name
Test status
Simulation time 2046693540 ps
CPU time 691.87 seconds
Started Jan 24 07:34:57 PM PST 24
Finished Jan 24 07:46:42 PM PST 24
Peak memory 402892 kb
Host smart-7915364c-bbee-4a78-8474-e05800d54ad2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=650210932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.650210932
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3878382679
Short name T310
Test name
Test status
Simulation time 3521442799 ps
CPU time 176.55 seconds
Started Jan 24 06:30:00 PM PST 24
Finished Jan 24 06:32:57 PM PST 24
Peak memory 201764 kb
Host smart-9e773618-5efd-4127-8f2a-bd697167a44f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878382679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3878382679
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2058283756
Short name T531
Test name
Test status
Simulation time 474884523 ps
CPU time 45.1 seconds
Started Jan 24 06:30:18 PM PST 24
Finished Jan 24 06:31:04 PM PST 24
Peak memory 299944 kb
Host smart-c7b62d91-74e6-40a1-85f3-2d771c63933b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058283756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2058283756
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2601696760
Short name T626
Test name
Test status
Simulation time 553351374 ps
CPU time 19.28 seconds
Started Jan 24 06:31:42 PM PST 24
Finished Jan 24 06:32:01 PM PST 24
Peak memory 219796 kb
Host smart-64bd7070-2cd4-4275-a8d6-af80c52e1d9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601696760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.2601696760
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.1358577711
Short name T924
Test name
Test status
Simulation time 32845829 ps
CPU time 0.64 seconds
Started Jan 24 06:32:08 PM PST 24
Finished Jan 24 06:32:09 PM PST 24
Peak memory 201704 kb
Host smart-8f3538b6-daa6-4db7-a7e6-b3e09ec00c6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358577711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.1358577711
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.2786505749
Short name T666
Test name
Test status
Simulation time 3203879950 ps
CPU time 52.68 seconds
Started Jan 24 06:31:14 PM PST 24
Finished Jan 24 06:32:07 PM PST 24
Peak memory 201768 kb
Host smart-dde687f5-7701-46db-80c1-6e133f9cd3ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786505749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.2786505749
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.2998011629
Short name T772
Test name
Test status
Simulation time 4539518320 ps
CPU time 1970.7 seconds
Started Jan 24 06:31:42 PM PST 24
Finished Jan 24 07:04:33 PM PST 24
Peak memory 373568 kb
Host smart-1d4361d3-dedc-4792-9555-7ec38b873f96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998011629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.2998011629
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.1552328497
Short name T619
Test name
Test status
Simulation time 2886924874 ps
CPU time 9.27 seconds
Started Jan 24 06:31:35 PM PST 24
Finished Jan 24 06:31:45 PM PST 24
Peak memory 209972 kb
Host smart-81317320-7f3a-463b-8346-af9770522e55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552328497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.1552328497
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.396446462
Short name T669
Test name
Test status
Simulation time 518805991 ps
CPU time 4.7 seconds
Started Jan 24 06:31:34 PM PST 24
Finished Jan 24 06:31:39 PM PST 24
Peak memory 219920 kb
Host smart-61a822f2-2f81-453d-b154-66860ef747c4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396446462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.sram_ctrl_max_throughput.396446462
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4239265226
Short name T488
Test name
Test status
Simulation time 97288473 ps
CPU time 3.16 seconds
Started Jan 24 06:31:53 PM PST 24
Finished Jan 24 06:31:57 PM PST 24
Peak memory 210060 kb
Host smart-50aba6de-67f8-4b39-b648-3b67ec7dcba9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239265226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.4239265226
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.2068443475
Short name T797
Test name
Test status
Simulation time 357283288 ps
CPU time 8.49 seconds
Started Jan 24 06:31:49 PM PST 24
Finished Jan 24 06:31:58 PM PST 24
Peak memory 201944 kb
Host smart-e901ee48-e565-4420-92e9-24f2f4a817e9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068443475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.2068443475
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.2464560718
Short name T507
Test name
Test status
Simulation time 17882169388 ps
CPU time 1540.59 seconds
Started Jan 24 06:31:21 PM PST 24
Finished Jan 24 06:57:03 PM PST 24
Peak memory 369588 kb
Host smart-c5abfb3b-c2d2-49ab-97ca-c326d22f2c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464560718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.2464560718
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.1235559062
Short name T322
Test name
Test status
Simulation time 1133289064 ps
CPU time 18.87 seconds
Started Jan 24 06:31:27 PM PST 24
Finished Jan 24 06:31:46 PM PST 24
Peak memory 253272 kb
Host smart-b7db1af2-78cc-4947-b4cf-52058be87bf4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235559062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.1235559062
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1553514482
Short name T901
Test name
Test status
Simulation time 19749599634 ps
CPU time 505.13 seconds
Started Jan 24 06:31:27 PM PST 24
Finished Jan 24 06:39:53 PM PST 24
Peak memory 201932 kb
Host smart-954ebc95-862f-40db-b9cd-4f1eff3f81b3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553514482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1553514482
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.149716240
Short name T277
Test name
Test status
Simulation time 82462582 ps
CPU time 0.87 seconds
Started Jan 24 06:31:46 PM PST 24
Finished Jan 24 06:31:48 PM PST 24
Peak memory 201928 kb
Host smart-1603f95a-6bc6-418b-83b6-f0520ee35663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149716240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.149716240
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.1414489948
Short name T764
Test name
Test status
Simulation time 8965382542 ps
CPU time 285.52 seconds
Started Jan 24 06:31:48 PM PST 24
Finished Jan 24 06:36:34 PM PST 24
Peak memory 328236 kb
Host smart-8ebd63c2-47d4-46f7-957a-56d9acf10598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414489948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1414489948
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.2952448772
Short name T834
Test name
Test status
Simulation time 1143017924 ps
CPU time 14.54 seconds
Started Jan 24 07:00:16 PM PST 24
Finished Jan 24 07:00:34 PM PST 24
Peak memory 201900 kb
Host smart-78364a54-c0ac-4a8a-971c-dd9c7c5c7846
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952448772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2952448772
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3840436232
Short name T622
Test name
Test status
Simulation time 904586325 ps
CPU time 1119.81 seconds
Started Jan 24 06:32:00 PM PST 24
Finished Jan 24 06:50:41 PM PST 24
Peak memory 385000 kb
Host smart-5e195e01-c78f-4339-8c8e-9ddebe41a28c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3840436232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3840436232
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3781944193
Short name T131
Test name
Test status
Simulation time 7663505959 ps
CPU time 234.74 seconds
Started Jan 24 08:14:26 PM PST 24
Finished Jan 24 08:18:22 PM PST 24
Peak memory 201948 kb
Host smart-2c63ff87-ed91-4c58-bb27-698128d81469
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781944193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.3781944193
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1088328029
Short name T617
Test name
Test status
Simulation time 1392228638 ps
CPU time 18.61 seconds
Started Jan 24 06:31:36 PM PST 24
Finished Jan 24 06:31:55 PM PST 24
Peak memory 257484 kb
Host smart-a42f1dce-b197-4e98-ba1b-fa7140a12187
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088328029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1088328029
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.430016664
Short name T509
Test name
Test status
Simulation time 20885898397 ps
CPU time 517.46 seconds
Started Jan 24 07:45:39 PM PST 24
Finished Jan 24 07:54:19 PM PST 24
Peak memory 372300 kb
Host smart-a67831b5-6a8e-4cab-9805-000fae40d51d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430016664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 43.sram_ctrl_access_during_key_req.430016664
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.1691431925
Short name T884
Test name
Test status
Simulation time 35441185 ps
CPU time 0.63 seconds
Started Jan 24 06:32:56 PM PST 24
Finished Jan 24 06:32:59 PM PST 24
Peak memory 200696 kb
Host smart-d35ac65c-1358-4576-b20f-568db71ad3ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691431925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.1691431925
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.4236307166
Short name T464
Test name
Test status
Simulation time 2741479797 ps
CPU time 40.94 seconds
Started Jan 24 06:32:43 PM PST 24
Finished Jan 24 06:33:25 PM PST 24
Peak memory 201904 kb
Host smart-9f551ec0-fa28-44a1-99a1-c2e898d36b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236307166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.4236307166
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.1272771582
Short name T945
Test name
Test status
Simulation time 8683800656 ps
CPU time 935.38 seconds
Started Jan 24 06:32:43 PM PST 24
Finished Jan 24 06:48:20 PM PST 24
Peak memory 372676 kb
Host smart-ca1e29d2-370a-4404-b0dc-bcfec8aaf0fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272771582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.1272771582
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.719398983
Short name T27
Test name
Test status
Simulation time 657636826 ps
CPU time 8.11 seconds
Started Jan 24 07:27:03 PM PST 24
Finished Jan 24 07:27:11 PM PST 24
Peak memory 210112 kb
Host smart-c2cb1bb3-9fdf-4902-b8b6-422061abfe9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719398983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc
alation.719398983
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.10739406
Short name T692
Test name
Test status
Simulation time 63861978 ps
CPU time 9.7 seconds
Started Jan 24 06:32:26 PM PST 24
Finished Jan 24 06:32:37 PM PST 24
Peak memory 242560 kb
Host smart-1a9d878a-6cb0-47bf-a624-560e1867711b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10739406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.sram_ctrl_max_throughput.10739406
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3254664861
Short name T484
Test name
Test status
Simulation time 100788330 ps
CPU time 2.96 seconds
Started Jan 24 06:32:52 PM PST 24
Finished Jan 24 06:32:58 PM PST 24
Peak memory 211172 kb
Host smart-8917b9e8-aede-4757-bef5-1cbdb2bef29d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254664861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.3254664861
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.53985256
Short name T962
Test name
Test status
Simulation time 3617525213 ps
CPU time 9.44 seconds
Started Jan 24 08:20:47 PM PST 24
Finished Jan 24 08:20:57 PM PST 24
Peak memory 202084 kb
Host smart-c8db2abd-1eb0-42aa-a5b7-87f4cc2b7edc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53985256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_
mem_walk.53985256
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.1426990976
Short name T949
Test name
Test status
Simulation time 29355926576 ps
CPU time 1257.04 seconds
Started Jan 24 06:32:14 PM PST 24
Finished Jan 24 06:53:12 PM PST 24
Peak memory 373660 kb
Host smart-e9c42982-7341-40b4-9b39-72314bc27d07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426990976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.1426990976
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.847442847
Short name T939
Test name
Test status
Simulation time 1970486672 ps
CPU time 8.66 seconds
Started Jan 24 06:32:21 PM PST 24
Finished Jan 24 06:32:30 PM PST 24
Peak memory 201912 kb
Host smart-05be9bea-b5af-4bab-a4c9-ef6dd5d73518
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847442847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s
ram_ctrl_partial_access.847442847
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.670369828
Short name T287
Test name
Test status
Simulation time 32282983749 ps
CPU time 413.66 seconds
Started Jan 24 06:32:27 PM PST 24
Finished Jan 24 06:39:21 PM PST 24
Peak memory 201848 kb
Host smart-6787d0ac-e517-458a-8c8d-a4b008f74caf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670369828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.sram_ctrl_partial_access_b2b.670369828
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.300945481
Short name T463
Test name
Test status
Simulation time 30204298 ps
CPU time 1.16 seconds
Started Jan 24 06:32:44 PM PST 24
Finished Jan 24 06:32:49 PM PST 24
Peak memory 202212 kb
Host smart-c1f9b845-69d5-42d0-8434-8230436a12c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300945481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.300945481
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.2613314669
Short name T775
Test name
Test status
Simulation time 6773221245 ps
CPU time 1529.72 seconds
Started Jan 24 06:32:38 PM PST 24
Finished Jan 24 06:58:09 PM PST 24
Peak memory 374724 kb
Host smart-9ce93401-2f64-4570-97d2-3c02eeb929e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613314669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2613314669
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.2665414508
Short name T28
Test name
Test status
Simulation time 87430663256 ps
CPU time 3661.72 seconds
Started Jan 24 06:32:56 PM PST 24
Finished Jan 24 07:34:01 PM PST 24
Peak memory 375768 kb
Host smart-7e960dae-4ffd-4d0d-b66a-aff8072646ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665414508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.sram_ctrl_stress_all.2665414508
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2981947747
Short name T342
Test name
Test status
Simulation time 9805971513 ps
CPU time 6176.97 seconds
Started Jan 24 07:23:11 PM PST 24
Finished Jan 24 09:06:11 PM PST 24
Peak memory 432996 kb
Host smart-c2f939d3-faeb-4bb5-8c9a-a556daa2bf19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2981947747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.2981947747
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3724277622
Short name T709
Test name
Test status
Simulation time 3099785938 ps
CPU time 304.6 seconds
Started Jan 24 06:32:20 PM PST 24
Finished Jan 24 06:37:25 PM PST 24
Peak memory 201932 kb
Host smart-7c7e6419-e3a6-4a73-8058-3188d79ba20a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724277622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.3724277622
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.239222687
Short name T296
Test name
Test status
Simulation time 84009465 ps
CPU time 3.97 seconds
Started Jan 24 06:32:28 PM PST 24
Finished Jan 24 06:32:36 PM PST 24
Peak memory 209996 kb
Host smart-a5407da7-602a-4d20-b471-5c8653860206
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239222687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_throughput_w_partial_write.239222687
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2738543265
Short name T16
Test name
Test status
Simulation time 6412438745 ps
CPU time 796.46 seconds
Started Jan 24 06:33:40 PM PST 24
Finished Jan 24 06:46:57 PM PST 24
Peak memory 370632 kb
Host smart-04eacb3c-1e4f-4b6c-9964-a8f14f1f7ca3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738543265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.2738543265
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.2065499383
Short name T938
Test name
Test status
Simulation time 11571929 ps
CPU time 0.66 seconds
Started Jan 24 10:41:01 PM PST 24
Finished Jan 24 10:41:07 PM PST 24
Peak memory 200824 kb
Host smart-3f4fbf52-9a95-4325-981b-9f8e805a86d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065499383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.2065499383
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.4032282118
Short name T356
Test name
Test status
Simulation time 2392620426 ps
CPU time 34.98 seconds
Started Jan 24 07:49:51 PM PST 24
Finished Jan 24 07:50:27 PM PST 24
Peak memory 201956 kb
Host smart-0c60df82-4d6e-4a35-813c-a3cea3efe5e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032282118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.4032282118
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.45819286
Short name T21
Test name
Test status
Simulation time 129060498212 ps
CPU time 972.02 seconds
Started Jan 24 06:33:41 PM PST 24
Finished Jan 24 06:49:54 PM PST 24
Peak memory 365588 kb
Host smart-a1c5eb1e-5cdb-4f0d-9b49-9d541f703db8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45819286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable
.45819286
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.2017411873
Short name T799
Test name
Test status
Simulation time 1955447146 ps
CPU time 14.37 seconds
Started Jan 24 06:33:37 PM PST 24
Finished Jan 24 06:33:52 PM PST 24
Peak memory 201972 kb
Host smart-b087aad8-b1eb-40be-8b12-a950ba270abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017411873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.2017411873
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.3086295874
Short name T129
Test name
Test status
Simulation time 117066429 ps
CPU time 85.66 seconds
Started Jan 24 06:33:21 PM PST 24
Finished Jan 24 06:34:47 PM PST 24
Peak memory 341920 kb
Host smart-700b8a25-50ee-411b-8acc-15c219e5346c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086295874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.3086295874
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3427910389
Short name T73
Test name
Test status
Simulation time 505712355 ps
CPU time 2.89 seconds
Started Jan 24 06:34:04 PM PST 24
Finished Jan 24 06:34:08 PM PST 24
Peak memory 210016 kb
Host smart-f9a3a136-4337-4e59-9da4-39a85e31c417
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427910389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.3427910389
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.3333723583
Short name T345
Test name
Test status
Simulation time 1171610360 ps
CPU time 8.47 seconds
Started Jan 24 06:36:49 PM PST 24
Finished Jan 24 06:36:58 PM PST 24
Peak memory 201972 kb
Host smart-3dfbbe98-54dd-4e28-a066-45a9ab1d1520
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333723583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.3333723583
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.612416260
Short name T631
Test name
Test status
Simulation time 217039891937 ps
CPU time 1145.28 seconds
Started Jan 24 07:01:10 PM PST 24
Finished Jan 24 07:20:23 PM PST 24
Peak memory 373664 kb
Host smart-8fe4e9aa-3976-44de-b02e-cc65ff5c89fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612416260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multip
le_keys.612416260
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.2872636284
Short name T533
Test name
Test status
Simulation time 239179327 ps
CPU time 12.86 seconds
Started Jan 24 06:33:18 PM PST 24
Finished Jan 24 06:33:31 PM PST 24
Peak memory 201868 kb
Host smart-96ceb7ae-17d0-4bee-9014-9c4751ed07ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872636284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.2872636284
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.749538920
Short name T225
Test name
Test status
Simulation time 66091538953 ps
CPU time 328.07 seconds
Started Jan 24 09:12:57 PM PST 24
Finished Jan 24 09:18:28 PM PST 24
Peak memory 201976 kb
Host smart-b2096e4d-a844-4a0c-b73d-aa94aaaa0818
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749538920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.sram_ctrl_partial_access_b2b.749538920
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.3661376463
Short name T977
Test name
Test status
Simulation time 77645090 ps
CPU time 1.09 seconds
Started Jan 24 08:07:20 PM PST 24
Finished Jan 24 08:07:25 PM PST 24
Peak memory 202212 kb
Host smart-070b772c-1978-4b1a-baec-0289d738dd4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661376463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3661376463
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.197978951
Short name T737
Test name
Test status
Simulation time 62192456059 ps
CPU time 2390.15 seconds
Started Jan 24 06:33:40 PM PST 24
Finished Jan 24 07:13:31 PM PST 24
Peak memory 371640 kb
Host smart-9f8034e0-bdd3-4dd4-b518-031d2346d24e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197978951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.197978951
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.185693521
Short name T625
Test name
Test status
Simulation time 334671595 ps
CPU time 26.41 seconds
Started Jan 24 07:25:59 PM PST 24
Finished Jan 24 07:26:29 PM PST 24
Peak memory 289324 kb
Host smart-b51ae420-40ae-4af2-8410-78e14c054826
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185693521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.185693521
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3951790063
Short name T508
Test name
Test status
Simulation time 7161651035 ps
CPU time 6579.17 seconds
Started Jan 24 09:56:43 PM PST 24
Finished Jan 24 11:46:24 PM PST 24
Peak memory 449132 kb
Host smart-54206c61-a6d8-4d35-a237-efa460baf9e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3951790063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3951790063
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.966605478
Short name T364
Test name
Test status
Simulation time 2408012133 ps
CPU time 224.21 seconds
Started Jan 24 06:33:17 PM PST 24
Finished Jan 24 06:37:01 PM PST 24
Peak memory 201960 kb
Host smart-da8689f1-b01d-4f81-aad4-f2cd400ab21e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966605478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.sram_ctrl_stress_pipeline.966605478
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3218548495
Short name T326
Test name
Test status
Simulation time 159106476 ps
CPU time 112.1 seconds
Started Jan 24 06:33:29 PM PST 24
Finished Jan 24 06:35:22 PM PST 24
Peak memory 363916 kb
Host smart-d17351a9-6f7a-424c-a6a5-26dc7d3a8cbd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218548495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3218548495
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1497494316
Short name T518
Test name
Test status
Simulation time 60308521644 ps
CPU time 1067.92 seconds
Started Jan 24 06:35:07 PM PST 24
Finished Jan 24 06:52:56 PM PST 24
Peak memory 372520 kb
Host smart-9972560f-0536-4d3e-9646-57a998138358
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497494316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.1497494316
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.1464895219
Short name T774
Test name
Test status
Simulation time 27155999 ps
CPU time 0.64 seconds
Started Jan 24 06:35:36 PM PST 24
Finished Jan 24 06:35:37 PM PST 24
Peak memory 201684 kb
Host smart-ed827864-66a9-4df2-948a-6940006c7d01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464895219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.1464895219
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.3949489335
Short name T719
Test name
Test status
Simulation time 3048355172 ps
CPU time 49.88 seconds
Started Jan 24 06:34:37 PM PST 24
Finished Jan 24 06:35:31 PM PST 24
Peak memory 201956 kb
Host smart-8720918b-33fd-4232-904e-e9f04a773dc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949489335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.3949489335
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.1890570062
Short name T297
Test name
Test status
Simulation time 10050366846 ps
CPU time 1207.59 seconds
Started Jan 24 06:35:13 PM PST 24
Finished Jan 24 06:55:22 PM PST 24
Peak memory 370580 kb
Host smart-20ab05c5-c5c8-4e71-a8cf-3f32a0a9732f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890570062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.1890570062
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.510817474
Short name T909
Test name
Test status
Simulation time 75105154 ps
CPU time 2.83 seconds
Started Jan 24 06:41:52 PM PST 24
Finished Jan 24 06:41:56 PM PST 24
Peak memory 214472 kb
Host smart-fdab25bf-d2f8-4d14-8384-2ec62774dd01
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510817474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.sram_ctrl_max_throughput.510817474
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2971313992
Short name T420
Test name
Test status
Simulation time 332810698 ps
CPU time 3.12 seconds
Started Jan 24 06:35:22 PM PST 24
Finished Jan 24 06:35:26 PM PST 24
Peak memory 210132 kb
Host smart-152f5bdf-bcbb-42df-a947-c1bab98c8e64
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971313992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.2971313992
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.1980986122
Short name T851
Test name
Test status
Simulation time 891573487 ps
CPU time 9.93 seconds
Started Jan 24 06:35:18 PM PST 24
Finished Jan 24 06:35:28 PM PST 24
Peak memory 201948 kb
Host smart-58ac2bca-2d5c-405d-ad36-95b930afdc9e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980986122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.1980986122
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.954404461
Short name T238
Test name
Test status
Simulation time 43285940538 ps
CPU time 1119.11 seconds
Started Jan 24 06:34:24 PM PST 24
Finished Jan 24 06:53:04 PM PST 24
Peak memory 361440 kb
Host smart-77cc18df-1d93-4345-aff0-bd64832ac9c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954404461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip
le_keys.954404461
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.2022324631
Short name T363
Test name
Test status
Simulation time 2029774472 ps
CPU time 101.61 seconds
Started Jan 24 06:56:25 PM PST 24
Finished Jan 24 06:58:08 PM PST 24
Peak memory 339536 kb
Host smart-779248f2-9ba0-49df-9c1b-00281235d548
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022324631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.2022324631
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.334745608
Short name T946
Test name
Test status
Simulation time 22459697862 ps
CPU time 248.86 seconds
Started Jan 24 06:34:47 PM PST 24
Finished Jan 24 06:38:56 PM PST 24
Peak memory 201888 kb
Host smart-67c9bae9-0fa9-4e80-889e-4e4667e26551
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334745608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.sram_ctrl_partial_access_b2b.334745608
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.3154015799
Short name T831
Test name
Test status
Simulation time 35926544 ps
CPU time 0.9 seconds
Started Jan 24 07:54:58 PM PST 24
Finished Jan 24 07:55:04 PM PST 24
Peak memory 202020 kb
Host smart-9c3705e0-8cf0-47b9-8547-29c0e720655b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154015799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3154015799
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.1209063386
Short name T827
Test name
Test status
Simulation time 48153723072 ps
CPU time 623.15 seconds
Started Jan 24 06:35:10 PM PST 24
Finished Jan 24 06:45:36 PM PST 24
Peak memory 371148 kb
Host smart-fdd1434c-8cf9-48af-b86f-ddec1f2ea28f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209063386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1209063386
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.1722701426
Short name T308
Test name
Test status
Simulation time 80812548 ps
CPU time 4.73 seconds
Started Jan 24 06:34:28 PM PST 24
Finished Jan 24 06:34:34 PM PST 24
Peak memory 201860 kb
Host smart-07c73403-27ba-4f16-9c4c-f580d2e04ece
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722701426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1722701426
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.1004962714
Short name T105
Test name
Test status
Simulation time 327298601075 ps
CPU time 5096.56 seconds
Started Jan 24 06:35:29 PM PST 24
Finished Jan 24 08:00:26 PM PST 24
Peak memory 374104 kb
Host smart-5089e228-a877-47b1-95ad-6b4c20799942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004962714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.1004962714
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1185882957
Short name T715
Test name
Test status
Simulation time 5988162930 ps
CPU time 2775.26 seconds
Started Jan 24 06:35:31 PM PST 24
Finished Jan 24 07:21:47 PM PST 24
Peak memory 451276 kb
Host smart-3f0091ed-5947-424b-888c-b8861e6aeb90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1185882957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1185882957
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.993714817
Short name T971
Test name
Test status
Simulation time 3310641707 ps
CPU time 322.21 seconds
Started Jan 24 06:34:37 PM PST 24
Finished Jan 24 06:40:03 PM PST 24
Peak memory 201944 kb
Host smart-dd3ca6b9-1ae7-4f6d-8603-ae78fb1de04f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993714817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_stress_pipeline.993714817
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.580014948
Short name T655
Test name
Test status
Simulation time 6860769505 ps
CPU time 1100.36 seconds
Started Jan 24 06:36:28 PM PST 24
Finished Jan 24 06:54:49 PM PST 24
Peak memory 369660 kb
Host smart-9d730daf-f45e-449b-be5b-708b9e16eda9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580014948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.sram_ctrl_access_during_key_req.580014948
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.1940596165
Short name T402
Test name
Test status
Simulation time 131025372 ps
CPU time 0.66 seconds
Started Jan 24 06:37:07 PM PST 24
Finished Jan 24 06:37:09 PM PST 24
Peak memory 201660 kb
Host smart-d59b5f11-0770-4681-ae17-9f97a5ef967e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940596165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.1940596165
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.2765061583
Short name T373
Test name
Test status
Simulation time 3395196336 ps
CPU time 44.49 seconds
Started Jan 24 06:35:49 PM PST 24
Finished Jan 24 06:36:34 PM PST 24
Peak memory 201936 kb
Host smart-dd8dadfc-7ba8-4f90-b815-446ed4e313b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765061583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.2765061583
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.2137845732
Short name T578
Test name
Test status
Simulation time 30832470698 ps
CPU time 596.93 seconds
Started Jan 24 06:46:13 PM PST 24
Finished Jan 24 06:56:11 PM PST 24
Peak memory 371524 kb
Host smart-1a08e6d8-e204-4dce-8b84-ac8ffe875f51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137845732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.2137845732
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.3641789320
Short name T757
Test name
Test status
Simulation time 2394991583 ps
CPU time 14.63 seconds
Started Jan 24 06:36:24 PM PST 24
Finished Jan 24 06:36:39 PM PST 24
Peak memory 210096 kb
Host smart-df9885df-e660-4d35-8af0-432ec61c80a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641789320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.3641789320
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.1112482153
Short name T660
Test name
Test status
Simulation time 116241647 ps
CPU time 68.97 seconds
Started Jan 24 07:03:36 PM PST 24
Finished Jan 24 07:04:46 PM PST 24
Peak memory 306544 kb
Host smart-cb6b2348-ebd6-497d-933f-c0b2b56964e8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112482153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.1112482153
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3232400586
Short name T75
Test name
Test status
Simulation time 207011077 ps
CPU time 3.15 seconds
Started Jan 24 06:36:45 PM PST 24
Finished Jan 24 06:36:48 PM PST 24
Peak memory 210064 kb
Host smart-eb3bd4d4-2f91-4c1f-8e42-41e5792a6436
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232400586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.3232400586
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.3353488734
Short name T306
Test name
Test status
Simulation time 1741188128 ps
CPU time 10.01 seconds
Started Jan 24 06:36:40 PM PST 24
Finished Jan 24 06:36:50 PM PST 24
Peak memory 201924 kb
Host smart-b523f0ea-7844-4742-a6c9-4818620247e9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353488734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.3353488734
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.1842793062
Short name T645
Test name
Test status
Simulation time 179155347498 ps
CPU time 1094.61 seconds
Started Jan 24 06:35:41 PM PST 24
Finished Jan 24 06:53:56 PM PST 24
Peak memory 360416 kb
Host smart-c25a5a8a-b55c-4d04-b7b3-5813b6d38e83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842793062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.1842793062
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.3226698324
Short name T510
Test name
Test status
Simulation time 129326865 ps
CPU time 6.71 seconds
Started Jan 24 06:36:00 PM PST 24
Finished Jan 24 06:36:07 PM PST 24
Peak memory 201924 kb
Host smart-e3480cf1-777d-4fac-b422-09577a885b43
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226698324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.3226698324
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.551814302
Short name T212
Test name
Test status
Simulation time 8843761614 ps
CPU time 224.95 seconds
Started Jan 24 06:35:58 PM PST 24
Finished Jan 24 06:39:44 PM PST 24
Peak memory 201900 kb
Host smart-678f6f7b-ace7-4d08-89f1-deca638cf993
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551814302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.sram_ctrl_partial_access_b2b.551814302
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.862591149
Short name T117
Test name
Test status
Simulation time 29743772 ps
CPU time 0.88 seconds
Started Jan 24 06:36:40 PM PST 24
Finished Jan 24 06:36:41 PM PST 24
Peak memory 201912 kb
Host smart-bb64df2d-bfa0-45df-92f4-b3206ee2b94e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862591149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.862591149
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.84460662
Short name T302
Test name
Test status
Simulation time 7229771352 ps
CPU time 463.95 seconds
Started Jan 24 06:36:33 PM PST 24
Finished Jan 24 06:44:17 PM PST 24
Peak memory 351276 kb
Host smart-9fab5b68-912d-4e2c-a88d-bf2fab114673
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84460662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.84460662
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.2679395786
Short name T430
Test name
Test status
Simulation time 527057978 ps
CPU time 121.56 seconds
Started Jan 24 06:35:37 PM PST 24
Finished Jan 24 06:37:39 PM PST 24
Peak memory 349932 kb
Host smart-cb1b41f6-638d-4464-99fb-f73c7f64a461
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679395786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2679395786
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.3092518599
Short name T705
Test name
Test status
Simulation time 27392363788 ps
CPU time 1508.77 seconds
Started Jan 24 08:00:54 PM PST 24
Finished Jan 24 08:26:04 PM PST 24
Peak memory 380960 kb
Host smart-5f7f2e5c-330a-4335-a5e0-c027c948201e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092518599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.3092518599
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3108996214
Short name T406
Test name
Test status
Simulation time 509465111 ps
CPU time 774.74 seconds
Started Jan 24 06:36:53 PM PST 24
Finished Jan 24 06:49:48 PM PST 24
Peak memory 382036 kb
Host smart-80ef091c-ca49-4cd4-8fa1-e51166babfbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3108996214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3108996214
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.359289579
Short name T804
Test name
Test status
Simulation time 2670923288 ps
CPU time 253.12 seconds
Started Jan 24 06:35:51 PM PST 24
Finished Jan 24 06:40:04 PM PST 24
Peak memory 201940 kb
Host smart-1930af37-e032-429a-86ec-46afb31366e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359289579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_stress_pipeline.359289579
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1381411901
Short name T221
Test name
Test status
Simulation time 202789052 ps
CPU time 5.22 seconds
Started Jan 24 06:44:39 PM PST 24
Finished Jan 24 06:44:45 PM PST 24
Peak memory 224680 kb
Host smart-8ef7b97e-0e7b-428e-8edb-c7987bf0196b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381411901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.1381411901
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2950697971
Short name T254
Test name
Test status
Simulation time 16473129315 ps
CPU time 1232.1 seconds
Started Jan 24 06:37:53 PM PST 24
Finished Jan 24 06:58:26 PM PST 24
Peak memory 372376 kb
Host smart-5b1ac6f0-169b-49e8-ac26-d526a1d36eb5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950697971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.2950697971
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.2258926612
Short name T832
Test name
Test status
Simulation time 67658381 ps
CPU time 0.67 seconds
Started Jan 24 06:38:25 PM PST 24
Finished Jan 24 06:38:26 PM PST 24
Peak memory 200800 kb
Host smart-658c89ce-aaab-4013-909b-4f4f2e8a4925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258926612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.2258926612
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.3456699335
Short name T445
Test name
Test status
Simulation time 569849608 ps
CPU time 17.82 seconds
Started Jan 24 06:37:25 PM PST 24
Finished Jan 24 06:37:44 PM PST 24
Peak memory 201912 kb
Host smart-e34fbcb2-3618-439c-b2bd-f1290e5166d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456699335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.3456699335
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.2573869278
Short name T547
Test name
Test status
Simulation time 16105020712 ps
CPU time 1771.84 seconds
Started Jan 24 06:49:12 PM PST 24
Finished Jan 24 07:18:45 PM PST 24
Peak memory 372664 kb
Host smart-201fd202-9560-448f-a226-92a22d53f756
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573869278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.2573869278
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.2377389982
Short name T422
Test name
Test status
Simulation time 482419752 ps
CPU time 6.9 seconds
Started Jan 24 07:30:54 PM PST 24
Finished Jan 24 07:31:03 PM PST 24
Peak memory 210128 kb
Host smart-2577e2ab-f7db-4393-9169-a3d137c02488
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377389982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.2377389982
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.1474529676
Short name T566
Test name
Test status
Simulation time 67569981 ps
CPU time 2.17 seconds
Started Jan 24 06:37:43 PM PST 24
Finished Jan 24 06:37:46 PM PST 24
Peak memory 210092 kb
Host smart-f0bcb0df-c7c6-4331-afcb-3bc797f72e9b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474529676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.1474529676
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3936249103
Short name T80
Test name
Test status
Simulation time 647717069 ps
CPU time 4.69 seconds
Started Jan 24 07:23:21 PM PST 24
Finished Jan 24 07:23:29 PM PST 24
Peak memory 214796 kb
Host smart-ec73aa68-48dc-41e5-b9ae-100e2a9c7b03
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936249103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.3936249103
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.820946682
Short name T418
Test name
Test status
Simulation time 141270537 ps
CPU time 8 seconds
Started Jan 24 07:00:06 PM PST 24
Finished Jan 24 07:00:18 PM PST 24
Peak memory 201892 kb
Host smart-38ce894d-d1cb-4381-994f-9599d6f5d131
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820946682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl
_mem_walk.820946682
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.4266402070
Short name T615
Test name
Test status
Simulation time 26425251696 ps
CPU time 985.37 seconds
Started Jan 24 06:37:29 PM PST 24
Finished Jan 24 06:53:55 PM PST 24
Peak memory 356332 kb
Host smart-344f0e8e-ce98-498c-b364-76c99ed14f2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266402070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.4266402070
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.495061627
Short name T403
Test name
Test status
Simulation time 2694138692 ps
CPU time 7.51 seconds
Started Jan 24 06:37:37 PM PST 24
Finished Jan 24 06:37:45 PM PST 24
Peak memory 225456 kb
Host smart-e568c7b4-fa56-4868-b92f-7c34e75e76cf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495061627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s
ram_ctrl_partial_access.495061627
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2553868848
Short name T961
Test name
Test status
Simulation time 15182760792 ps
CPU time 262.77 seconds
Started Jan 24 06:37:36 PM PST 24
Finished Jan 24 06:42:00 PM PST 24
Peak memory 201956 kb
Host smart-d5e80e09-2640-4549-8311-b86967d93599
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553868848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.2553868848
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.135266691
Short name T780
Test name
Test status
Simulation time 81514210 ps
CPU time 1.11 seconds
Started Jan 24 06:37:58 PM PST 24
Finished Jan 24 06:38:00 PM PST 24
Peak memory 202196 kb
Host smart-e7162b1c-72cb-4a98-92c8-1708814f7d6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135266691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.135266691
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.467767619
Short name T790
Test name
Test status
Simulation time 32097512108 ps
CPU time 728.07 seconds
Started Jan 24 06:38:00 PM PST 24
Finished Jan 24 06:50:10 PM PST 24
Peak memory 372692 kb
Host smart-d4688cc4-575e-4f74-a66f-651cff53f531
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467767619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.467767619
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.2804732668
Short name T252
Test name
Test status
Simulation time 335940102 ps
CPU time 7.58 seconds
Started Jan 24 08:09:31 PM PST 24
Finished Jan 24 08:09:43 PM PST 24
Peak memory 234624 kb
Host smart-d295ed1e-a751-48a1-af0f-c83f3d930183
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804732668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2804732668
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.1242636919
Short name T768
Test name
Test status
Simulation time 36712811383 ps
CPU time 1581.86 seconds
Started Jan 24 06:38:17 PM PST 24
Finished Jan 24 07:04:40 PM PST 24
Peak memory 369636 kb
Host smart-92538229-fc36-4405-aa67-1994a810758c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242636919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.1242636919
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2769116114
Short name T812
Test name
Test status
Simulation time 1529325564 ps
CPU time 2026.41 seconds
Started Jan 24 06:38:13 PM PST 24
Finished Jan 24 07:12:00 PM PST 24
Peak memory 431936 kb
Host smart-8c0790c3-d76f-4ece-9dec-94f2bc4bb1c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2769116114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2769116114
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2557059790
Short name T352
Test name
Test status
Simulation time 2419160776 ps
CPU time 226.8 seconds
Started Jan 24 06:37:30 PM PST 24
Finished Jan 24 06:41:17 PM PST 24
Peak memory 201940 kb
Host smart-482b1203-ab7b-4c38-ac49-39c55d83cad1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557059790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.2557059790
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1876469848
Short name T39
Test name
Test status
Simulation time 94838080 ps
CPU time 29.78 seconds
Started Jan 24 06:37:45 PM PST 24
Finished Jan 24 06:38:15 PM PST 24
Peak memory 283540 kb
Host smart-7ed73f67-360e-4503-a6ae-64be4cf45719
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876469848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1876469848
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3290417861
Short name T226
Test name
Test status
Simulation time 10990588823 ps
CPU time 840.62 seconds
Started Jan 24 06:39:04 PM PST 24
Finished Jan 24 06:53:05 PM PST 24
Peak memory 371304 kb
Host smart-63a65f3e-703c-43d2-9662-ed39522fe214
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290417861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.3290417861
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.1589905071
Short name T807
Test name
Test status
Simulation time 15439569 ps
CPU time 0.66 seconds
Started Jan 24 06:39:41 PM PST 24
Finished Jan 24 06:39:44 PM PST 24
Peak memory 201660 kb
Host smart-cb9fa4a5-8831-499c-9714-76a800f4ce63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589905071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.1589905071
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.657681337
Short name T846
Test name
Test status
Simulation time 12253601168 ps
CPU time 45.32 seconds
Started Jan 24 06:38:32 PM PST 24
Finished Jan 24 06:39:18 PM PST 24
Peak memory 201880 kb
Host smart-7735485b-3ba7-4920-a48c-075440abd0bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657681337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.
657681337
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.3231725476
Short name T841
Test name
Test status
Simulation time 1792665689 ps
CPU time 736.07 seconds
Started Jan 24 06:39:14 PM PST 24
Finished Jan 24 06:51:31 PM PST 24
Peak memory 370000 kb
Host smart-77455631-2c19-4382-8112-3697d8a55a51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231725476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab
le.3231725476
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.3040084072
Short name T355
Test name
Test status
Simulation time 1071435861 ps
CPU time 14.02 seconds
Started Jan 24 06:38:53 PM PST 24
Finished Jan 24 06:39:07 PM PST 24
Peak memory 201824 kb
Host smart-3b5541df-f69e-4817-8045-49a02305b4d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040084072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.3040084072
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.2001016863
Short name T684
Test name
Test status
Simulation time 322213207 ps
CPU time 31.74 seconds
Started Jan 24 06:38:45 PM PST 24
Finished Jan 24 06:39:17 PM PST 24
Peak memory 283452 kb
Host smart-6f8e4f0a-9d1d-4fc1-b46b-8672294ff4df
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001016863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.2001016863
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4026427227
Short name T707
Test name
Test status
Simulation time 163007515 ps
CPU time 2.92 seconds
Started Jan 24 07:18:27 PM PST 24
Finished Jan 24 07:18:31 PM PST 24
Peak memory 214632 kb
Host smart-33eacd42-8df7-4fd5-bce1-0177c3a6a828
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026427227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.4026427227
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.3225240401
Short name T451
Test name
Test status
Simulation time 880385331 ps
CPU time 10.11 seconds
Started Jan 24 06:39:26 PM PST 24
Finished Jan 24 06:39:37 PM PST 24
Peak memory 201944 kb
Host smart-acce552f-ba42-461c-8dc4-5bf5b189f0c3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225240401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.3225240401
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.3359848435
Short name T880
Test name
Test status
Simulation time 13919833336 ps
CPU time 1244.32 seconds
Started Jan 24 06:40:59 PM PST 24
Finished Jan 24 07:01:44 PM PST 24
Peak memory 369588 kb
Host smart-f3753f12-2bf0-4bd4-9185-805c8fea5a7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359848435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.3359848435
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.436325831
Short name T304
Test name
Test status
Simulation time 835152731 ps
CPU time 15.67 seconds
Started Jan 24 06:38:40 PM PST 24
Finished Jan 24 06:38:56 PM PST 24
Peak memory 201928 kb
Host smart-c557933c-e2e4-4da7-8129-20a7840459d8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436325831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.s
ram_ctrl_partial_access.436325831
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2323529887
Short name T443
Test name
Test status
Simulation time 147964115722 ps
CPU time 330.05 seconds
Started Jan 24 06:38:39 PM PST 24
Finished Jan 24 06:44:10 PM PST 24
Peak memory 201740 kb
Host smart-7ee158cb-158b-4e3a-a3a7-c52cb2b2e857
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323529887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.2323529887
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.1218266541
Short name T114
Test name
Test status
Simulation time 80556402 ps
CPU time 1.06 seconds
Started Jan 24 08:28:22 PM PST 24
Finished Jan 24 08:28:24 PM PST 24
Peak memory 202204 kb
Host smart-ad15bfcb-a3ab-4682-bc43-87c9e591727d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218266541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1218266541
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.2877018170
Short name T623
Test name
Test status
Simulation time 28967301660 ps
CPU time 770.63 seconds
Started Jan 24 06:39:17 PM PST 24
Finished Jan 24 06:52:10 PM PST 24
Peak memory 365520 kb
Host smart-2174e2a4-3e28-4284-afd3-b3b10937c92c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877018170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2877018170
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.3072539873
Short name T908
Test name
Test status
Simulation time 9393072612 ps
CPU time 16.91 seconds
Started Jan 24 07:32:49 PM PST 24
Finished Jan 24 07:33:08 PM PST 24
Peak memory 201912 kb
Host smart-00b667ae-1ecc-4766-99e5-ea7167cdfb8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072539873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3072539873
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.317102081
Short name T14
Test name
Test status
Simulation time 681238368 ps
CPU time 1003.38 seconds
Started Jan 24 06:39:28 PM PST 24
Finished Jan 24 06:56:12 PM PST 24
Peak memory 383804 kb
Host smart-fe5efbdf-7cfa-4dc5-aafd-05e4a6550bf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=317102081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.317102081
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3496749299
Short name T676
Test name
Test status
Simulation time 6042638324 ps
CPU time 326.08 seconds
Started Jan 24 06:51:02 PM PST 24
Finished Jan 24 06:56:28 PM PST 24
Peak memory 201952 kb
Host smart-30b5a438-3241-4c0e-85ad-05ef01c606b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496749299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.3496749299
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2819239597
Short name T656
Test name
Test status
Simulation time 99942384 ps
CPU time 25.63 seconds
Started Jan 24 07:41:23 PM PST 24
Finished Jan 24 07:41:50 PM PST 24
Peak memory 284520 kb
Host smart-6e6af5f0-37af-4438-90e9-f847cf66e0ad
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819239597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.2819239597
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1504502110
Short name T84
Test name
Test status
Simulation time 28466843809 ps
CPU time 412.21 seconds
Started Jan 24 06:40:23 PM PST 24
Finished Jan 24 06:47:16 PM PST 24
Peak memory 338940 kb
Host smart-c7ce0436-e6b3-4478-983c-fde2a66613c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504502110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.1504502110
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.1757869033
Short name T347
Test name
Test status
Simulation time 21660717 ps
CPU time 0.65 seconds
Started Jan 24 06:40:41 PM PST 24
Finished Jan 24 06:40:43 PM PST 24
Peak memory 201244 kb
Host smart-97918ae1-2dbc-4df6-8fde-15d0f2124542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757869033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.1757869033
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.2285386424
Short name T453
Test name
Test status
Simulation time 6372110640 ps
CPU time 26.32 seconds
Started Jan 24 06:39:44 PM PST 24
Finished Jan 24 06:40:11 PM PST 24
Peak memory 201916 kb
Host smart-d8208cbb-8245-47c9-acea-abe5aa0d200e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285386424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.2285386424
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.1505757255
Short name T943
Test name
Test status
Simulation time 9558749842 ps
CPU time 257.82 seconds
Started Jan 24 06:40:24 PM PST 24
Finished Jan 24 06:44:42 PM PST 24
Peak memory 317164 kb
Host smart-3864f941-2758-4864-b6c3-4a21e256c637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505757255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.1505757255
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.1749501448
Short name T330
Test name
Test status
Simulation time 2145776995 ps
CPU time 7.04 seconds
Started Jan 24 06:40:17 PM PST 24
Finished Jan 24 06:40:24 PM PST 24
Peak memory 201880 kb
Host smart-9444a5e1-a378-4600-b697-680a1b51fe1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749501448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.1749501448
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.3148999524
Short name T607
Test name
Test status
Simulation time 173188262 ps
CPU time 5.96 seconds
Started Jan 24 06:40:05 PM PST 24
Finished Jan 24 06:40:12 PM PST 24
Peak memory 225164 kb
Host smart-6fe7cc46-b828-4964-a057-d850637bd44e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148999524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.3148999524
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2209201213
Short name T383
Test name
Test status
Simulation time 317932905 ps
CPU time 5.05 seconds
Started Jan 24 07:33:32 PM PST 24
Finished Jan 24 07:33:37 PM PST 24
Peak memory 210092 kb
Host smart-767f123b-f872-4133-a5e4-3ae07117c374
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209201213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.2209201213
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.1301797133
Short name T628
Test name
Test status
Simulation time 233577724 ps
CPU time 5.22 seconds
Started Jan 24 06:40:29 PM PST 24
Finished Jan 24 06:40:35 PM PST 24
Peak memory 201824 kb
Host smart-2d191dc7-2254-4ceb-a053-de830947294a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301797133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.1301797133
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.718198771
Short name T922
Test name
Test status
Simulation time 973853524 ps
CPU time 57.91 seconds
Started Jan 24 06:39:46 PM PST 24
Finished Jan 24 06:40:44 PM PST 24
Peak memory 296820 kb
Host smart-9c635712-2233-45f1-9242-77c9d600e066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718198771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip
le_keys.718198771
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.1604746111
Short name T490
Test name
Test status
Simulation time 248827026 ps
CPU time 4.44 seconds
Started Jan 24 06:40:04 PM PST 24
Finished Jan 24 06:40:09 PM PST 24
Peak memory 201916 kb
Host smart-9918dfc6-647c-4540-ab1e-1dfb6871e48b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604746111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.1604746111
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1076923262
Short name T609
Test name
Test status
Simulation time 76250569182 ps
CPU time 451.62 seconds
Started Jan 24 06:40:04 PM PST 24
Finished Jan 24 06:47:36 PM PST 24
Peak memory 201888 kb
Host smart-b5c67bb1-3db6-4427-824f-c67c54685bc8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076923262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.1076923262
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.2268064140
Short name T3
Test name
Test status
Simulation time 150270514 ps
CPU time 0.87 seconds
Started Jan 24 07:03:55 PM PST 24
Finished Jan 24 07:03:56 PM PST 24
Peak memory 201992 kb
Host smart-9cdc8f19-8124-4b9d-803a-82e8d902e186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268064140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.2268064140
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.621628553
Short name T375
Test name
Test status
Simulation time 129870674449 ps
CPU time 547.57 seconds
Started Jan 24 09:02:25 PM PST 24
Finished Jan 24 09:11:34 PM PST 24
Peak memory 372388 kb
Host smart-ef7dac2f-2046-465b-8c33-c20685718424
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621628553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.621628553
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.1992897653
Short name T829
Test name
Test status
Simulation time 46382273 ps
CPU time 3.37 seconds
Started Jan 24 06:39:40 PM PST 24
Finished Jan 24 06:39:45 PM PST 24
Peak memory 207960 kb
Host smart-f9ea2334-7112-4220-a758-0d452defd0cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992897653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1992897653
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.3398090222
Short name T830
Test name
Test status
Simulation time 9505378828 ps
CPU time 3356.12 seconds
Started Jan 24 07:20:00 PM PST 24
Finished Jan 24 08:16:00 PM PST 24
Peak memory 374668 kb
Host smart-4a75d70a-9598-460c-af48-36c2fbc2b729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398090222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.3398090222
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.578576470
Short name T29
Test name
Test status
Simulation time 4077419209 ps
CPU time 834.32 seconds
Started Jan 24 07:01:12 PM PST 24
Finished Jan 24 07:15:17 PM PST 24
Peak memory 384596 kb
Host smart-8dd6ffe8-f09f-464a-af6b-28b3b06e826a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=578576470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.578576470
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.324791022
Short name T750
Test name
Test status
Simulation time 6463090710 ps
CPU time 113.27 seconds
Started Jan 24 06:39:51 PM PST 24
Finished Jan 24 06:41:44 PM PST 24
Peak memory 201848 kb
Host smart-b10d63a8-742d-49fc-bd99-8d661aa5decd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324791022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_stress_pipeline.324791022
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1896936370
Short name T12
Test name
Test status
Simulation time 360936030 ps
CPU time 31.69 seconds
Started Jan 24 07:08:36 PM PST 24
Finished Jan 24 07:09:10 PM PST 24
Peak memory 283588 kb
Host smart-04980ce4-170a-4b6f-ad39-82f13a17d32c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896936370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1896936370
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1174538786
Short name T457
Test name
Test status
Simulation time 9522429219 ps
CPU time 876.54 seconds
Started Jan 24 05:48:25 PM PST 24
Finished Jan 24 06:03:03 PM PST 24
Peak memory 366504 kb
Host smart-8d675cfd-aeb9-4f89-abc4-b96473c99f3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174538786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.1174538786
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.2353080985
Short name T38
Test name
Test status
Simulation time 18289440 ps
CPU time 0.68 seconds
Started Jan 24 06:03:46 PM PST 24
Finished Jan 24 06:03:47 PM PST 24
Peak memory 200764 kb
Host smart-a3517a32-99ef-452d-929a-a38f8133dc19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353080985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.2353080985
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.2758916334
Short name T10
Test name
Test status
Simulation time 2182953950 ps
CPU time 71.22 seconds
Started Jan 24 05:48:10 PM PST 24
Finished Jan 24 05:49:26 PM PST 24
Peak memory 201876 kb
Host smart-e86738a2-9b64-4d79-82d0-87c91170ca66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758916334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
2758916334
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.3402917944
Short name T334
Test name
Test status
Simulation time 3613260690 ps
CPU time 841.95 seconds
Started Jan 24 05:48:23 PM PST 24
Finished Jan 24 06:02:27 PM PST 24
Peak memory 367080 kb
Host smart-a6bd7c86-6fe3-49f7-bfb9-66debca0cabf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402917944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.3402917944
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.205826501
Short name T886
Test name
Test status
Simulation time 546466358 ps
CPU time 14.63 seconds
Started Jan 24 05:48:24 PM PST 24
Finished Jan 24 05:48:40 PM PST 24
Peak memory 201856 kb
Host smart-4c58c048-f888-4dce-9fc5-9374d565899a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205826501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esca
lation.205826501
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.1698258912
Short name T560
Test name
Test status
Simulation time 130815604 ps
CPU time 134.55 seconds
Started Jan 24 06:50:31 PM PST 24
Finished Jan 24 06:52:47 PM PST 24
Peak memory 365160 kb
Host smart-16e8afc8-98d7-4a47-9ae9-a381f849a8c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698258912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.1698258912
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2436861871
Short name T284
Test name
Test status
Simulation time 677938128 ps
CPU time 5.6 seconds
Started Jan 24 05:58:23 PM PST 24
Finished Jan 24 05:58:29 PM PST 24
Peak memory 210120 kb
Host smart-12ae9986-db21-498e-ae59-b89035e0204a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436861871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.2436861871
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.2974868076
Short name T802
Test name
Test status
Simulation time 1231985666 ps
CPU time 5.36 seconds
Started Jan 24 06:29:09 PM PST 24
Finished Jan 24 06:29:15 PM PST 24
Peak memory 201964 kb
Host smart-555450a8-108a-4245-928a-7030964ae1bc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974868076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.2974868076
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.298211426
Short name T244
Test name
Test status
Simulation time 4662267003 ps
CPU time 208.7 seconds
Started Jan 24 05:48:09 PM PST 24
Finished Jan 24 05:51:41 PM PST 24
Peak memory 320520 kb
Host smart-c7ceedf5-1a1c-4fc4-94b0-e751f9ed63dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298211426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl
e_keys.298211426
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.4163259528
Short name T738
Test name
Test status
Simulation time 485151673 ps
CPU time 8.38 seconds
Started Jan 24 05:48:12 PM PST 24
Finished Jan 24 05:48:28 PM PST 24
Peak memory 201860 kb
Host smart-c8dfc86f-c392-47d7-84b0-34afe9a5f0fa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163259528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.4163259528
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2125108039
Short name T557
Test name
Test status
Simulation time 35602296543 ps
CPU time 211.5 seconds
Started Jan 24 05:47:52 PM PST 24
Finished Jan 24 05:51:26 PM PST 24
Peak memory 201964 kb
Host smart-b6e663e0-b5b5-476f-be1b-625eab606eb1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125108039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.2125108039
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.3642058688
Short name T434
Test name
Test status
Simulation time 95847270 ps
CPU time 0.85 seconds
Started Jan 24 05:48:28 PM PST 24
Finished Jan 24 05:48:30 PM PST 24
Peak memory 201960 kb
Host smart-98671027-d6d6-4430-b3b5-8d8327107143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642058688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3642058688
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.342325201
Short name T910
Test name
Test status
Simulation time 2716038470 ps
CPU time 1134.32 seconds
Started Jan 24 05:48:25 PM PST 24
Finished Jan 24 06:07:21 PM PST 24
Peak memory 364448 kb
Host smart-e129d71a-c94e-4468-a07c-fd082fb8dd00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342325201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.342325201
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.873265188
Short name T426
Test name
Test status
Simulation time 83542138 ps
CPU time 24.45 seconds
Started Jan 24 05:48:09 PM PST 24
Finished Jan 24 05:48:37 PM PST 24
Peak memory 266300 kb
Host smart-ca813afe-30c6-439a-a6cb-77a2e6885f74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873265188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.873265188
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.1958221067
Short name T796
Test name
Test status
Simulation time 19773197476 ps
CPU time 1490.08 seconds
Started Jan 24 05:48:30 PM PST 24
Finished Jan 24 06:13:22 PM PST 24
Peak memory 381892 kb
Host smart-553d7db9-62a8-4048-8397-06e8f83ae61c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958221067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.1958221067
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1411924754
Short name T588
Test name
Test status
Simulation time 3143046129 ps
CPU time 1098.33 seconds
Started Jan 24 06:07:08 PM PST 24
Finished Jan 24 06:25:27 PM PST 24
Peak memory 382420 kb
Host smart-d4f33b17-cccc-4ded-b8f5-926f9402fed2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1411924754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1411924754
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.149276333
Short name T260
Test name
Test status
Simulation time 2554428488 ps
CPU time 224.27 seconds
Started Jan 24 05:54:00 PM PST 24
Finished Jan 24 05:57:45 PM PST 24
Peak memory 201952 kb
Host smart-ae622143-9528-4673-9003-c9f1c3596594
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149276333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
sram_ctrl_stress_pipeline.149276333
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2745974169
Short name T755
Test name
Test status
Simulation time 247803800 ps
CPU time 10 seconds
Started Jan 24 05:56:05 PM PST 24
Finished Jan 24 05:56:15 PM PST 24
Peak memory 237608 kb
Host smart-79ee2a50-4055-4c3d-b456-2ea3b768f07b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745974169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2745974169
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.65177691
Short name T956
Test name
Test status
Simulation time 4111219778 ps
CPU time 1714.17 seconds
Started Jan 24 05:49:24 PM PST 24
Finished Jan 24 06:17:59 PM PST 24
Peak memory 374796 kb
Host smart-9ba3344b-8ae5-412f-918d-1c7437062317
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65177691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.sram_ctrl_access_during_key_req.65177691
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.2439493469
Short name T877
Test name
Test status
Simulation time 18249239 ps
CPU time 0.65 seconds
Started Jan 24 05:49:33 PM PST 24
Finished Jan 24 05:49:34 PM PST 24
Peak memory 201708 kb
Host smart-ea75c803-409a-46b7-b4f3-16b33d50a8ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439493469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.2439493469
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.914068500
Short name T650
Test name
Test status
Simulation time 1091000035 ps
CPU time 20.67 seconds
Started Jan 24 05:48:30 PM PST 24
Finished Jan 24 05:48:51 PM PST 24
Peak memory 201876 kb
Host smart-a2ef25a5-8879-40da-9ae1-495008664d89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914068500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.914068500
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.2358861669
Short name T393
Test name
Test status
Simulation time 35607147601 ps
CPU time 1139.64 seconds
Started Jan 24 05:49:24 PM PST 24
Finished Jan 24 06:08:24 PM PST 24
Peak memory 368260 kb
Host smart-257eea7b-28e5-4c66-9a6c-e4d0be2839dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358861669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.2358861669
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.4188202874
Short name T483
Test name
Test status
Simulation time 326716538 ps
CPU time 9.63 seconds
Started Jan 24 05:49:01 PM PST 24
Finished Jan 24 05:49:11 PM PST 24
Peak memory 210048 kb
Host smart-c263e366-219a-42ad-b4b8-4c1a743f08f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188202874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.4188202874
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.4029412878
Short name T735
Test name
Test status
Simulation time 67227895 ps
CPU time 11.13 seconds
Started Jan 24 05:48:49 PM PST 24
Finished Jan 24 05:49:01 PM PST 24
Peak memory 250584 kb
Host smart-802977d1-be2c-4b2e-b6f0-e5339b362367
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029412878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.4029412878
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.249763791
Short name T597
Test name
Test status
Simulation time 372136851 ps
CPU time 5.29 seconds
Started Jan 24 05:49:33 PM PST 24
Finished Jan 24 05:49:39 PM PST 24
Peak memory 210084 kb
Host smart-44ed258a-f530-48eb-b045-81d6d3fbd9f3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249763791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
sram_ctrl_mem_partial_access.249763791
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3086683350
Short name T270
Test name
Test status
Simulation time 1242504477 ps
CPU time 5.71 seconds
Started Jan 24 05:49:30 PM PST 24
Finished Jan 24 05:49:36 PM PST 24
Peak memory 201848 kb
Host smart-e8743853-3426-4b6e-8a84-bf513f631b46
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086683350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3086683350
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.4262360673
Short name T115
Test name
Test status
Simulation time 2738299897 ps
CPU time 1367.26 seconds
Started Jan 24 05:48:30 PM PST 24
Finished Jan 24 06:11:19 PM PST 24
Peak memory 372512 kb
Host smart-010e52b0-dcf0-4b70-9ba8-c959e6ffc5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262360673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.4262360673
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.2790601282
Short name T905
Test name
Test status
Simulation time 229099345 ps
CPU time 6.75 seconds
Started Jan 24 05:48:41 PM PST 24
Finished Jan 24 05:48:48 PM PST 24
Peak memory 231324 kb
Host smart-89a63786-953e-4c9a-a597-fb66f8c6a2d1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790601282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.2790601282
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2619844
Short name T611
Test name
Test status
Simulation time 23713707800 ps
CPU time 426.67 seconds
Started Jan 24 05:48:53 PM PST 24
Finished Jan 24 05:56:00 PM PST 24
Peak memory 201912 kb
Host smart-2f892b46-d91a-46c3-b410-33cd4d3b69e4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_partial_access_b2b.2619844
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.1273204450
Short name T30
Test name
Test status
Simulation time 46138583 ps
CPU time 1.15 seconds
Started Jan 24 05:49:26 PM PST 24
Finished Jan 24 05:49:28 PM PST 24
Peak memory 202256 kb
Host smart-5706a7c0-34b3-476f-a9cc-2002408680b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273204450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1273204450
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.188929200
Short name T416
Test name
Test status
Simulation time 11303148665 ps
CPU time 1822.36 seconds
Started Jan 24 05:49:27 PM PST 24
Finished Jan 24 06:19:50 PM PST 24
Peak memory 371656 kb
Host smart-fca16f5d-6afd-4082-b250-2e77bee20938
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188929200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.188929200
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.1787705448
Short name T251
Test name
Test status
Simulation time 65981461 ps
CPU time 2.03 seconds
Started Jan 24 05:48:29 PM PST 24
Finished Jan 24 05:48:32 PM PST 24
Peak memory 201808 kb
Host smart-5c166211-9610-4d48-a182-3677f86b2074
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787705448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1787705448
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.1042904915
Short name T616
Test name
Test status
Simulation time 238740093627 ps
CPU time 1448.9 seconds
Started Jan 24 07:16:54 PM PST 24
Finished Jan 24 07:41:07 PM PST 24
Peak memory 374584 kb
Host smart-be5af3a4-49da-471f-8038-6df6539e7319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042904915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.1042904915
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3553143671
Short name T385
Test name
Test status
Simulation time 4575708227 ps
CPU time 1113.5 seconds
Started Jan 24 06:08:51 PM PST 24
Finished Jan 24 06:27:26 PM PST 24
Peak memory 429272 kb
Host smart-4cd7537c-0d3f-4fdf-b908-b8fb6ca44ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3553143671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3553143671
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2852849499
Short name T222
Test name
Test status
Simulation time 1368611834 ps
CPU time 129.98 seconds
Started Jan 24 05:48:40 PM PST 24
Finished Jan 24 05:50:51 PM PST 24
Peak memory 201720 kb
Host smart-dd257a77-ec30-467c-8f1d-1cb0e3b87efd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852849499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.2852849499
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.966988525
Short name T479
Test name
Test status
Simulation time 121533471 ps
CPU time 63 seconds
Started Jan 24 05:48:49 PM PST 24
Finished Jan 24 05:49:53 PM PST 24
Peak memory 315144 kb
Host smart-e43ee5ec-0581-4c22-bcbf-715388082b94
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966988525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.966988525
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2463515381
Short name T400
Test name
Test status
Simulation time 372147999 ps
CPU time 144.27 seconds
Started Jan 24 05:49:46 PM PST 24
Finished Jan 24 05:52:11 PM PST 24
Peak memory 368416 kb
Host smart-cd914a10-c5ae-4b35-b488-48959da486fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463515381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.2463515381
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.144699812
Short name T377
Test name
Test status
Simulation time 18558608 ps
CPU time 0.7 seconds
Started Jan 24 05:50:10 PM PST 24
Finished Jan 24 05:50:14 PM PST 24
Peak memory 200748 kb
Host smart-0aa19b32-d534-4526-ac28-f11f7d1023f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144699812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.144699812
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.82827642
Short name T415
Test name
Test status
Simulation time 15290210048 ps
CPU time 63.19 seconds
Started Jan 24 05:49:34 PM PST 24
Finished Jan 24 05:50:37 PM PST 24
Peak memory 201928 kb
Host smart-db11ef40-36ae-4bed-b68f-648d7d7ac40b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82827642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.82827642
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.3759967674
Short name T585
Test name
Test status
Simulation time 33394587331 ps
CPU time 2030.79 seconds
Started Jan 24 05:49:46 PM PST 24
Finished Jan 24 06:23:38 PM PST 24
Peak memory 369660 kb
Host smart-f792aa69-dfae-4198-9b78-695e31156618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759967674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl
e.3759967674
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.1556972471
Short name T325
Test name
Test status
Simulation time 670486288 ps
CPU time 8.7 seconds
Started Jan 24 05:49:48 PM PST 24
Finished Jan 24 05:49:57 PM PST 24
Peak memory 212568 kb
Host smart-109e2749-eee0-4005-9703-c101a8d61b3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556972471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.1556972471
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.2608331422
Short name T695
Test name
Test status
Simulation time 568745485 ps
CPU time 54.69 seconds
Started Jan 24 05:49:41 PM PST 24
Finished Jan 24 05:50:36 PM PST 24
Peak memory 308680 kb
Host smart-e2c21779-c77a-4a5b-bffd-769fab9b0b56
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608331422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.2608331422
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3614198051
Short name T759
Test name
Test status
Simulation time 579568739 ps
CPU time 5.27 seconds
Started Jan 24 07:08:34 PM PST 24
Finished Jan 24 07:08:44 PM PST 24
Peak memory 210136 kb
Host smart-fb264120-f3d4-428c-ab59-6df9c3155928
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614198051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.3614198051
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.2629259523
Short name T766
Test name
Test status
Simulation time 77770671 ps
CPU time 4.35 seconds
Started Jan 24 05:49:51 PM PST 24
Finished Jan 24 05:49:56 PM PST 24
Peak memory 201904 kb
Host smart-74ce370f-3bd8-4db0-adf6-47cb76899bc4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629259523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.2629259523
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.1328948150
Short name T499
Test name
Test status
Simulation time 44826129791 ps
CPU time 709.59 seconds
Started Jan 24 06:53:28 PM PST 24
Finished Jan 24 07:05:18 PM PST 24
Peak memory 364004 kb
Host smart-681f3962-290d-43d9-9e6c-9de928fe6852
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328948150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.1328948150
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.323911111
Short name T568
Test name
Test status
Simulation time 1028978130 ps
CPU time 91.96 seconds
Started Jan 24 06:17:24 PM PST 24
Finished Jan 24 06:18:57 PM PST 24
Peak memory 325384 kb
Host smart-278c86ca-2ee6-4713-8fc2-9ef581d2408a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323911111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sr
am_ctrl_partial_access.323911111
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.882781365
Short name T725
Test name
Test status
Simulation time 15574371677 ps
CPU time 269.54 seconds
Started Jan 24 05:49:41 PM PST 24
Finished Jan 24 05:54:11 PM PST 24
Peak memory 201700 kb
Host smart-180b7424-a81b-4bbf-ae6f-afe37adec9e1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882781365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.sram_ctrl_partial_access_b2b.882781365
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.2935569717
Short name T459
Test name
Test status
Simulation time 50299806 ps
CPU time 0.85 seconds
Started Jan 24 06:05:25 PM PST 24
Finished Jan 24 06:05:28 PM PST 24
Peak memory 201968 kb
Host smart-a7dde32a-3a22-455f-98e2-e833b7838876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935569717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2935569717
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.3487689169
Short name T809
Test name
Test status
Simulation time 10725809754 ps
CPU time 921.98 seconds
Started Jan 24 05:49:54 PM PST 24
Finished Jan 24 06:05:16 PM PST 24
Peak memory 372152 kb
Host smart-382e33f2-8974-4251-a90a-b6689e91c1bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487689169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3487689169
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.575323713
Short name T687
Test name
Test status
Simulation time 420172927 ps
CPU time 13.69 seconds
Started Jan 24 05:49:34 PM PST 24
Finished Jan 24 05:49:48 PM PST 24
Peak memory 201848 kb
Host smart-18b0398e-7f45-43dd-8ff5-d45d70e3e82d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575323713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.575323713
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.522228258
Short name T424
Test name
Test status
Simulation time 57059890547 ps
CPU time 2775.79 seconds
Started Jan 24 05:50:11 PM PST 24
Finished Jan 24 06:36:29 PM PST 24
Peak memory 374640 kb
Host smart-d048a873-0c0d-4bda-8f39-ac6e37aa401a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522228258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_stress_all.522228258
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1956853404
Short name T842
Test name
Test status
Simulation time 7860553298 ps
CPU time 386.96 seconds
Started Jan 24 05:49:36 PM PST 24
Finished Jan 24 05:56:04 PM PST 24
Peak memory 201944 kb
Host smart-a2e826b8-2660-40dd-abc0-cc652a204315
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956853404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.1956853404
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3182795788
Short name T123
Test name
Test status
Simulation time 376490726 ps
CPU time 39.09 seconds
Started Jan 24 05:49:50 PM PST 24
Finished Jan 24 05:50:30 PM PST 24
Peak memory 283540 kb
Host smart-1c36221d-2e7e-4d0a-be05-31711fc2c7c2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182795788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.3182795788
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3335174440
Short name T240
Test name
Test status
Simulation time 6466171768 ps
CPU time 589.85 seconds
Started Jan 24 05:50:35 PM PST 24
Finished Jan 24 06:00:26 PM PST 24
Peak memory 366492 kb
Host smart-8c549d86-b2a5-43d7-93c2-d2a24f3328ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335174440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.3335174440
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.1571026845
Short name T23
Test name
Test status
Simulation time 28520375 ps
CPU time 0.64 seconds
Started Jan 24 05:50:41 PM PST 24
Finished Jan 24 05:50:43 PM PST 24
Peak memory 200748 kb
Host smart-2ffe394e-389f-4320-af02-871ec8223609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571026845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.1571026845
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.957239814
Short name T301
Test name
Test status
Simulation time 1799523809 ps
CPU time 38.56 seconds
Started Jan 24 05:50:19 PM PST 24
Finished Jan 24 05:51:02 PM PST 24
Peak memory 201852 kb
Host smart-7518eabe-a93f-4781-a88d-bdb18e52b83c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957239814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.957239814
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.2754352478
Short name T408
Test name
Test status
Simulation time 13984679207 ps
CPU time 1749.39 seconds
Started Jan 24 06:07:46 PM PST 24
Finished Jan 24 06:37:04 PM PST 24
Peak memory 373680 kb
Host smart-d9372ec6-9201-4ed0-90d8-feac1824d688
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754352478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.2754352478
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.1812853400
Short name T473
Test name
Test status
Simulation time 829989667 ps
CPU time 106.03 seconds
Started Jan 24 05:50:26 PM PST 24
Finished Jan 24 05:52:14 PM PST 24
Peak memory 350716 kb
Host smart-75f1bfe6-a441-481d-bcaa-be9280d1d60e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812853400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.1812853400
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.993621983
Short name T71
Test name
Test status
Simulation time 68600567 ps
CPU time 4.65 seconds
Started Jan 24 07:34:28 PM PST 24
Finished Jan 24 07:34:34 PM PST 24
Peak memory 210176 kb
Host smart-b2e3d0c5-c1a7-41a0-b342-784ab73cadb8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993621983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
sram_ctrl_mem_partial_access.993621983
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.3028607853
Short name T691
Test name
Test status
Simulation time 923386759 ps
CPU time 5.14 seconds
Started Jan 24 05:50:36 PM PST 24
Finished Jan 24 05:50:42 PM PST 24
Peak memory 201904 kb
Host smart-7ab7cf3d-9eb2-4bd0-83a2-dcd50123b3b8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028607853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.3028607853
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.180104823
Short name T405
Test name
Test status
Simulation time 19754576329 ps
CPU time 1191.6 seconds
Started Jan 24 06:24:59 PM PST 24
Finished Jan 24 06:44:51 PM PST 24
Peak memory 372648 kb
Host smart-28d4bb01-6792-4e6f-b2f9-9c487f768dc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180104823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl
e_keys.180104823
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.1009526516
Short name T895
Test name
Test status
Simulation time 1888358698 ps
CPU time 13.79 seconds
Started Jan 24 05:50:20 PM PST 24
Finished Jan 24 05:50:37 PM PST 24
Peak memory 201928 kb
Host smart-f126bdfe-ebb2-48f3-b666-c58eb11235d5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009526516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.1009526516
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.500437154
Short name T555
Test name
Test status
Simulation time 5470822720 ps
CPU time 394.96 seconds
Started Jan 24 05:50:20 PM PST 24
Finished Jan 24 05:56:58 PM PST 24
Peak memory 202004 kb
Host smart-29db0d81-00a1-43a2-a56a-1f77db8a774f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500437154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.sram_ctrl_partial_access_b2b.500437154
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.112179284
Short name T704
Test name
Test status
Simulation time 38661459 ps
CPU time 1.09 seconds
Started Jan 24 06:34:58 PM PST 24
Finished Jan 24 06:35:01 PM PST 24
Peak memory 202196 kb
Host smart-883b8f8e-901a-4fbc-8f8c-b9f6b1006b27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112179284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.112179284
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.3573772475
Short name T339
Test name
Test status
Simulation time 1027700221 ps
CPU time 131.99 seconds
Started Jan 24 05:50:32 PM PST 24
Finished Jan 24 05:52:44 PM PST 24
Peak memory 317152 kb
Host smart-0e1f0e2c-839d-4268-ad54-de98107814c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573772475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3573772475
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.1286985046
Short name T112
Test name
Test status
Simulation time 277984002 ps
CPU time 2.75 seconds
Started Jan 24 05:50:20 PM PST 24
Finished Jan 24 05:50:26 PM PST 24
Peak memory 205208 kb
Host smart-7c8cce57-4a3f-456e-bd42-4f83463e5094
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286985046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1286985046
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.3736221944
Short name T558
Test name
Test status
Simulation time 10471537740 ps
CPU time 2795.05 seconds
Started Jan 24 05:50:45 PM PST 24
Finished Jan 24 06:37:22 PM PST 24
Peak memory 373644 kb
Host smart-46fd835e-ac26-4a2f-9712-1d64c71202fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736221944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.3736221944
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2466524586
Short name T386
Test name
Test status
Simulation time 1899510613 ps
CPU time 2870.34 seconds
Started Jan 24 05:50:41 PM PST 24
Finished Jan 24 06:38:32 PM PST 24
Peak memory 415176 kb
Host smart-c6606691-3b9a-42b4-84a8-d37f708162b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2466524586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2466524586
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1677622796
Short name T480
Test name
Test status
Simulation time 3927896740 ps
CPU time 250.13 seconds
Started Jan 24 05:50:19 PM PST 24
Finished Jan 24 05:54:33 PM PST 24
Peak memory 201928 kb
Host smart-f328eb12-f40a-414e-b8f7-855efc523253
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677622796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.1677622796
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2449829547
Short name T437
Test name
Test status
Simulation time 223184661 ps
CPU time 52.96 seconds
Started Jan 24 05:50:26 PM PST 24
Finished Jan 24 05:51:21 PM PST 24
Peak memory 308500 kb
Host smart-b820d0b7-fd7d-4e64-a6a4-b7a451a90d3f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449829547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2449829547
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3776329635
Short name T647
Test name
Test status
Simulation time 18372665742 ps
CPU time 1173.02 seconds
Started Jan 24 05:51:45 PM PST 24
Finished Jan 24 06:11:19 PM PST 24
Peak memory 346128 kb
Host smart-8f6ef7f3-daef-4777-bf9d-4f80a3ce4545
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776329635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.3776329635
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.1274156327
Short name T860
Test name
Test status
Simulation time 133360011 ps
CPU time 0.65 seconds
Started Jan 24 05:52:13 PM PST 24
Finished Jan 24 05:52:14 PM PST 24
Peak memory 201736 kb
Host smart-e9dcc7c2-5852-4de8-8315-b81d12287d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274156327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.1274156327
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.1061326962
Short name T688
Test name
Test status
Simulation time 9449423807 ps
CPU time 28.47 seconds
Started Jan 24 05:50:55 PM PST 24
Finished Jan 24 05:51:26 PM PST 24
Peak memory 201924 kb
Host smart-c79f163b-c869-4d0e-a5ca-67b037a2c258
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061326962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
1061326962
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.2786284936
Short name T423
Test name
Test status
Simulation time 11573922983 ps
CPU time 593.8 seconds
Started Jan 24 05:51:49 PM PST 24
Finished Jan 24 06:01:43 PM PST 24
Peak memory 370664 kb
Host smart-6df4001e-1e3e-46a3-a46a-ef0198fb18ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786284936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.2786284936
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.2666293868
Short name T835
Test name
Test status
Simulation time 322165118 ps
CPU time 1.56 seconds
Started Jan 24 05:51:49 PM PST 24
Finished Jan 24 05:51:51 PM PST 24
Peak memory 212228 kb
Host smart-f34db768-ee0e-4e73-a41f-03ba6311ec92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666293868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.2666293868
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.439673305
Short name T440
Test name
Test status
Simulation time 44379254 ps
CPU time 3.04 seconds
Started Jan 24 05:51:18 PM PST 24
Finished Jan 24 05:51:21 PM PST 24
Peak memory 215768 kb
Host smart-2839f937-adb3-43b9-a410-738be02e17f6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439673305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.sram_ctrl_max_throughput.439673305
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1629162534
Short name T954
Test name
Test status
Simulation time 180629671 ps
CPU time 5.28 seconds
Started Jan 24 05:52:13 PM PST 24
Finished Jan 24 05:52:19 PM PST 24
Peak memory 210088 kb
Host smart-70f3dbdf-8f54-4b85-b1f3-f15616708383
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629162534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.1629162534
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.1995908786
Short name T824
Test name
Test status
Simulation time 145617184 ps
CPU time 4.5 seconds
Started Jan 24 05:52:11 PM PST 24
Finished Jan 24 05:52:16 PM PST 24
Peak memory 201876 kb
Host smart-ecdf74a3-3233-4421-8985-8c5672d7e707
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995908786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.1995908786
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.1424108333
Short name T497
Test name
Test status
Simulation time 12119946719 ps
CPU time 1002.78 seconds
Started Jan 24 05:50:43 PM PST 24
Finished Jan 24 06:07:26 PM PST 24
Peak memory 371648 kb
Host smart-e3d75cbe-4cfd-4676-81bb-53ce6123e9a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424108333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.1424108333
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.3262677303
Short name T898
Test name
Test status
Simulation time 73283232 ps
CPU time 2.19 seconds
Started Jan 24 05:51:07 PM PST 24
Finished Jan 24 05:51:09 PM PST 24
Peak memory 201896 kb
Host smart-ad40df48-be7c-4139-8793-1912769b48ba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262677303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.3262677303
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.504802957
Short name T883
Test name
Test status
Simulation time 12219564109 ps
CPU time 324.44 seconds
Started Jan 24 05:51:12 PM PST 24
Finished Jan 24 05:56:37 PM PST 24
Peak memory 201904 kb
Host smart-068da185-baed-4a69-b4c0-87e18854fc10
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504802957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.sram_ctrl_partial_access_b2b.504802957
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.269255506
Short name T248
Test name
Test status
Simulation time 40980566 ps
CPU time 0.96 seconds
Started Jan 24 05:51:46 PM PST 24
Finished Jan 24 05:51:47 PM PST 24
Peak memory 201772 kb
Host smart-cd70c6ce-2596-4f49-b543-96c001c9cc08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269255506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.269255506
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.2523356477
Short name T911
Test name
Test status
Simulation time 1639829599 ps
CPU time 27.62 seconds
Started Jan 24 05:51:49 PM PST 24
Finished Jan 24 05:52:17 PM PST 24
Peak memory 227420 kb
Host smart-21224b2e-a7a1-495f-acb7-07316a9a6b4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523356477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2523356477
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.1576108932
Short name T593
Test name
Test status
Simulation time 382438996 ps
CPU time 6.65 seconds
Started Jan 24 05:50:45 PM PST 24
Finished Jan 24 05:50:52 PM PST 24
Peak memory 201864 kb
Host smart-b27d08be-6265-420a-996e-02d1c20894f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576108932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1576108932
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.1838560006
Short name T344
Test name
Test status
Simulation time 20380860924 ps
CPU time 1864.97 seconds
Started Jan 24 05:51:41 PM PST 24
Finished Jan 24 06:22:47 PM PST 24
Peak memory 370620 kb
Host smart-db612138-1715-4b42-ba6c-587ad779153b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838560006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.1838560006
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1694013795
Short name T216
Test name
Test status
Simulation time 4696004776 ps
CPU time 2858.51 seconds
Started Jan 24 05:52:14 PM PST 24
Finished Jan 24 06:39:53 PM PST 24
Peak memory 418912 kb
Host smart-f4393eef-9a7e-4177-8fb7-63f7a7da4879
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1694013795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1694013795
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.768699528
Short name T215
Test name
Test status
Simulation time 2494573134 ps
CPU time 247.62 seconds
Started Jan 24 05:51:04 PM PST 24
Finished Jan 24 05:55:12 PM PST 24
Peak memory 201848 kb
Host smart-8f76e693-7a63-4442-a7aa-a7dfb6eee025
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768699528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_stress_pipeline.768699528
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2669228797
Short name T839
Test name
Test status
Simulation time 159843825 ps
CPU time 158.24 seconds
Started Jan 24 05:51:21 PM PST 24
Finished Jan 24 05:54:00 PM PST 24
Peak memory 364348 kb
Host smart-637ecc5d-0fbc-4943-ab17-708cb37d680c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669228797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2669228797
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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