Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14546603	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58751339

1

T1

47440

T2

233104

T3

12288

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36546425	1			T1	130382		T2	128603		T3	6144
values[0x0]	16915997	1			T1	44125		T2	61518		T3	3107
values[0x1]	19835520	1			T1	86752		T2	66010		T3	3037

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7243488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66054454

1

T1

154814

T2

244513

T3

12288

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	248864	1			T1	923		T2	1049		T3	57
valid_sources[0x01]	264569	1			T1	1040		T2	1035		T3	43
valid_sources[0x02]	244093	1			T1	1022		T2	927		T3	51
valid_sources[0x03]	330182	1			T1	1228		T2	1053		T3	53
valid_sources[0x04]	276656	1			T1	1074		T2	1004		T3	37
valid_sources[0x05]	247495	1			T1	1215		T2	1048		T3	40
valid_sources[0x06]	263773	1			T1	925		T2	926		T3	38
valid_sources[0x07]	256487	1			T1	1082		T2	1153		T3	46
valid_sources[0x08]	281282	1			T1	1035		T2	1175		T3	47
valid_sources[0x09]	276944	1			T1	997		T2	976		T3	54
valid_sources[0x0a]	339219	1			T1	1009		T2	842		T3	47
valid_sources[0x0b]	298874	1			T1	1181		T2	918		T3	47
valid_sources[0x0c]	319750	1			T1	1095		T2	1127		T3	50
valid_sources[0x0d]	252505	1			T1	966		T2	1068		T3	40
valid_sources[0x0e]	306371	1			T1	1032		T2	920		T3	50
valid_sources[0x0f]	273986	1			T1	1005		T2	817		T3	45
valid_sources[0x10]	303093	1			T1	1181		T2	855		T3	37
valid_sources[0x11]	353244	1			T1	876		T2	954		T3	43
valid_sources[0x12]	259361	1			T1	1139		T2	819		T3	42
valid_sources[0x13]	293028	1			T1	1132		T2	1145		T3	50
valid_sources[0x14]	253739	1			T1	976		T2	913		T3	54
valid_sources[0x15]	267872	1			T1	918		T2	887		T3	48
valid_sources[0x16]	320814	1			T1	948		T2	979		T3	51
valid_sources[0x17]	272504	1			T1	1272		T2	1123		T3	50
valid_sources[0x18]	357596	1			T1	1007		T2	1080		T3	40
valid_sources[0x19]	255494	1			T1	1020		T2	818		T3	39
valid_sources[0x1a]	293550	1			T1	1035		T2	1199		T3	66
valid_sources[0x1b]	274409	1			T1	922		T2	948		T3	52
valid_sources[0x1c]	253213	1			T1	986		T2	1154		T3	45
valid_sources[0x1d]	355104	1			T1	1246		T2	847		T3	62
valid_sources[0x1e]	332179	1			T1	1035		T2	844		T3	60
valid_sources[0x1f]	311735	1			T1	940		T2	830		T3	50
valid_sources[0x20]	252608	1			T1	1066		T2	705		T3	50
valid_sources[0x21]	283495	1			T1	894		T2	879		T3	46
valid_sources[0x22]	306177	1			T1	916		T2	857		T3	56
valid_sources[0x23]	266907	1			T1	1021		T2	836		T3	45
valid_sources[0x24]	330521	1			T1	888		T2	952		T3	57
valid_sources[0x25]	250599	1			T1	1137		T2	959		T3	56
valid_sources[0x26]	301712	1			T1	1013		T2	967		T3	44
valid_sources[0x27]	247589	1			T1	1052		T2	1037		T3	54
valid_sources[0x28]	319855	1			T1	1168		T2	1035		T3	57
valid_sources[0x29]	285394	1			T1	965		T2	899		T3	43
valid_sources[0x2a]	260182	1			T1	987		T2	848		T3	43
valid_sources[0x2b]	250860	1			T1	1220		T2	914		T3	40
valid_sources[0x2c]	319198	1			T1	1223		T2	1202		T3	34
valid_sources[0x2d]	289014	1			T1	895		T2	1024		T3	52
valid_sources[0x2e]	310276	1			T1	1027		T2	1151		T3	47
valid_sources[0x2f]	251636	1			T1	1092		T2	1015		T3	54
valid_sources[0x30]	248897	1			T1	1132		T2	1115		T3	55
valid_sources[0x31]	277724	1			T1	897		T2	1200		T3	41
valid_sources[0x32]	272487	1			T1	912		T2	1080		T3	42
valid_sources[0x33]	311586	1			T1	1144		T2	923		T3	54
valid_sources[0x34]	273399	1			T1	1125		T2	1115		T3	49
valid_sources[0x35]	324309	1			T1	929		T2	1086		T3	42
valid_sources[0x36]	251556	1			T1	1030		T2	864		T3	42
valid_sources[0x37]	269093	1			T1	1134		T2	1123		T3	58
valid_sources[0x38]	274508	1			T1	982		T2	1145		T3	43
valid_sources[0x39]	310685	1			T1	998		T2	983		T3	61
valid_sources[0x3a]	293326	1			T1	1102		T2	808		T3	37
valid_sources[0x3b]	251648	1			T1	980		T2	709		T3	51
valid_sources[0x3c]	268036	1			T1	836		T2	881		T3	48
valid_sources[0x3d]	282535	1			T1	847		T2	1230		T3	45
valid_sources[0x3e]	303483	1			T1	891		T2	959		T3	55
valid_sources[0x3f]	272887	1			T1	983		T2	983		T3	53
valid_sources[0x40]	282536	1			T1	985		T2	985		T3	48
valid_sources[0x41]	264048	1			T1	1008		T2	1182		T3	41
valid_sources[0x42]	262495	1			T1	1023		T2	862		T3	44
valid_sources[0x43]	252499	1			T1	985		T2	877		T3	62
valid_sources[0x44]	243461	1			T1	987		T2	957		T3	46
valid_sources[0x45]	271471	1			T1	1087		T2	1068		T3	62
valid_sources[0x46]	308971	1			T1	1064		T2	1173		T3	43
valid_sources[0x47]	369847	1			T1	997		T2	835		T3	39
valid_sources[0x48]	271480	1			T1	1160		T2	1397		T3	58
valid_sources[0x49]	274002	1			T1	1023		T2	1385		T3	44
valid_sources[0x4a]	242907	1			T1	1084		T2	772		T3	48
valid_sources[0x4b]	307762	1			T1	960		T2	870		T3	60
valid_sources[0x4c]	251253	1			T1	987		T2	849		T3	46
valid_sources[0x4d]	272840	1			T1	1033		T2	1124		T3	42
valid_sources[0x4e]	271350	1			T1	1025		T2	835		T3	45
valid_sources[0x4f]	258552	1			T1	1025		T2	1109		T3	40
valid_sources[0x50]	412884	1			T1	843		T2	991		T3	42
valid_sources[0x51]	296342	1			T1	1098		T2	1062		T3	46
valid_sources[0x52]	301342	1			T1	981		T2	1104		T3	61
valid_sources[0x53]	279861	1			T1	903		T2	757		T3	50
valid_sources[0x54]	245526	1			T1	1034		T2	979		T3	40
valid_sources[0x55]	245177	1			T1	997		T2	1341		T3	53
valid_sources[0x56]	261232	1			T1	961		T2	901		T3	46
valid_sources[0x57]	259663	1			T1	951		T2	1128		T3	47
valid_sources[0x58]	247431	1			T1	1137		T2	1070		T3	49
valid_sources[0x59]	283437	1			T1	786		T2	695		T3	50
valid_sources[0x5a]	301200	1			T1	1092		T2	851		T3	43
valid_sources[0x5b]	290816	1			T1	955		T2	829		T3	36
valid_sources[0x5c]	300753	1			T1	1027		T2	1014		T3	42
valid_sources[0x5d]	269522	1			T1	988		T2	1168		T3	60
valid_sources[0x5e]	251579	1			T1	948		T2	1120		T3	57
valid_sources[0x5f]	300278	1			T1	848		T2	797		T3	46
valid_sources[0x60]	275477	1			T1	1206		T2	981		T3	38
valid_sources[0x61]	258599	1			T1	1201		T2	1181		T3	45
valid_sources[0x62]	346752	1			T1	1015		T2	1231		T3	38
valid_sources[0x63]	257367	1			T1	1067		T2	1002		T3	35
valid_sources[0x64]	315690	1			T1	988		T2	977		T3	51
valid_sources[0x65]	356221	1			T1	941		T2	1030		T3	52
valid_sources[0x66]	270091	1			T1	1112		T2	914		T3	39
valid_sources[0x67]	323728	1			T1	1239		T2	991		T3	47
valid_sources[0x68]	255063	1			T1	1189		T2	869		T3	71
valid_sources[0x69]	268014	1			T1	969		T2	725		T3	53
valid_sources[0x6a]	276475	1			T1	1290		T2	899		T3	51
valid_sources[0x6b]	276689	1			T1	996		T2	735		T3	47
valid_sources[0x6c]	288655	1			T1	1032		T2	775		T3	40
valid_sources[0x6d]	296683	1			T1	1079		T2	971		T3	46
valid_sources[0x6e]	268396	1			T1	885		T2	958		T3	43
valid_sources[0x6f]	243289	1			T1	979		T2	1105		T3	38
valid_sources[0x70]	284645	1			T1	1083		T2	827		T3	42
valid_sources[0x71]	309150	1			T1	1054		T2	1013		T3	41
valid_sources[0x72]	265504	1			T1	976		T2	831		T3	44
valid_sources[0x73]	256086	1			T1	912		T2	1107		T3	40
valid_sources[0x74]	256992	1			T1	863		T2	986		T3	48
valid_sources[0x75]	245898	1			T1	1072		T2	836		T3	41
valid_sources[0x76]	272977	1			T1	915		T2	1039		T3	62
valid_sources[0x77]	267730	1			T1	973		T2	988		T3	45
valid_sources[0x78]	258154	1			T1	944		T2	757		T3	51
valid_sources[0x79]	296419	1			T1	794		T2	904		T3	43
valid_sources[0x7a]	245550	1			T1	1112		T2	1039		T3	53
valid_sources[0x7b]	325276	1			T1	1152		T2	892		T3	40
valid_sources[0x7c]	265698	1			T1	989		T2	1171		T3	49
valid_sources[0x7d]	344415	1			T1	1003		T2	1051		T3	47
valid_sources[0x7e]	292072	1			T1	1090		T2	1260		T3	56
valid_sources[0x7f]	326119	1			T1	1075		T2	1115		T3	50
valid_sources[0x80]	271899	1			T1	1046		T2	1186		T3	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29275561

1

T1

23644

T2

117070

T3

6144

values[0x0]

all_enables

biggest_size

14735157

1

T1

11969

T2

58063

T3

3107

values[0x1]

all_enables

biggest_size

14740621

1

T1

11827

T2

57971

T3

3037

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2024252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

127683

1

T1

2

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2040196	1			T1	2722		T2	2608		T3	115
values[0x0]	54269	1			T1	3		T2	2		T3	3
values[0x1]	57470	1			T1	2		T2	3		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1352828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

799107

1

T1

849

T2

861

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6503	1			T3	1		T8	16		T9	1
valid_sources[0x01]	6350	1			T8	14		T9	1		T10	1
valid_sources[0x02]	6444	1			T5	2		T8	19		T9	5
valid_sources[0x03]	7135	1			T5	1		T8	22		T9	1
valid_sources[0x04]	11340	1			T5	2		T8	24		T9	2
valid_sources[0x05]	6591	1			T8	24		T9	1		T10	2
valid_sources[0x06]	7469	1			T8	29		T9	2		T10	5
valid_sources[0x07]	8215	1			T2	7		T3	1		T5	1
valid_sources[0x08]	15462	1			T3	1		T5	2		T8	14
valid_sources[0x09]	7212	1			T5	1		T8	16		T9	3
valid_sources[0x0a]	9150	1			T2	6		T5	3		T8	28
valid_sources[0x0b]	6919	1			T2	44		T8	17		T10	1
valid_sources[0x0c]	6188	1			T2	8		T5	2		T8	13
valid_sources[0x0d]	8328	1			T3	2		T8	21		T9	1
valid_sources[0x0e]	6328	1			T5	1		T8	16		T9	1
valid_sources[0x0f]	7154	1			T3	1		T5	3		T8	30
valid_sources[0x10]	6224	1			T2	72		T8	18		T10	1
valid_sources[0x11]	9044	1			T2	17		T8	22		T9	2
valid_sources[0x12]	6665	1			T2	3		T5	3		T8	29
valid_sources[0x13]	9952	1			T2	21		T3	1		T8	23
valid_sources[0x14]	7539	1			T2	3		T5	1		T8	13
valid_sources[0x15]	7651	1			T2	7		T5	1		T8	24
valid_sources[0x16]	6749	1			T5	2		T8	22		T9	3
valid_sources[0x17]	6344	1			T2	28		T3	1		T5	2
valid_sources[0x18]	6543	1			T2	28		T3	1		T8	13
valid_sources[0x19]	5952	1			T2	31		T8	20		T9	1
valid_sources[0x1a]	10365	1			T3	1		T5	1		T8	23
valid_sources[0x1b]	16626	1			T3	1		T5	2		T8	36
valid_sources[0x1c]	9512	1			T2	50		T3	2		T8	26
valid_sources[0x1d]	6016	1			T2	57		T5	1		T8	21
valid_sources[0x1e]	10266	1			T2	49		T3	1		T8	11
valid_sources[0x1f]	6973	1			T2	9		T5	2		T8	22
valid_sources[0x20]	6099	1			T8	17		T9	2		T10	2
valid_sources[0x21]	7499	1			T3	1		T8	19		T9	3
valid_sources[0x22]	8009	1			T2	3		T5	2		T8	15
valid_sources[0x23]	6345	1			T2	21		T8	19		T9	9
valid_sources[0x24]	6513	1			T2	18		T3	1		T8	27
valid_sources[0x25]	7219	1			T3	1		T8	19		T9	1
valid_sources[0x26]	7916	1			T2	1		T3	2		T5	2
valid_sources[0x27]	7048	1			T8	22		T9	6		T10	2
valid_sources[0x28]	12296	1			T2	21		T5	1		T8	18
valid_sources[0x29]	9449	1			T8	19		T9	5		T10	3
valid_sources[0x2a]	10516	1			T8	18		T9	6		T10	5
valid_sources[0x2b]	14044	1			T8	18		T10	7		T12	8
valid_sources[0x2c]	6848	1			T2	31		T3	1		T5	2
valid_sources[0x2d]	7792	1			T8	18		T9	3		T10	1
valid_sources[0x2e]	6252	1			T2	7		T8	20		T9	1
valid_sources[0x2f]	9611	1			T2	31		T3	2		T5	2
valid_sources[0x30]	10097	1			T2	6		T5	1		T8	20
valid_sources[0x31]	6336	1			T5	1		T8	19		T9	2
valid_sources[0x32]	7508	1			T2	43		T5	1		T8	16
valid_sources[0x33]	6425	1			T3	1		T8	26		T9	5
valid_sources[0x34]	6485	1			T2	1		T5	2		T8	23
valid_sources[0x35]	7312	1			T2	8		T8	21		T9	1
valid_sources[0x36]	7292	1			T2	26		T5	3		T8	18
valid_sources[0x37]	6517	1			T8	24		T9	1		T10	4
valid_sources[0x38]	6602	1			T8	16		T9	2		T10	1
valid_sources[0x39]	7025	1			T5	1		T8	20		T9	4
valid_sources[0x3a]	6680	1			T2	42		T3	1		T5	1
valid_sources[0x3b]	6582	1			T2	17		T8	15		T9	3
valid_sources[0x3c]	6624	1			T8	28		T12	4		T15	20
valid_sources[0x3d]	6349	1			T2	3		T5	2		T8	14
valid_sources[0x3e]	7526	1			T5	2		T8	24		T9	1
valid_sources[0x3f]	7234	1			T8	25		T9	1		T10	2
valid_sources[0x40]	6123	1			T5	1		T8	23		T9	1
valid_sources[0x41]	6942	1			T2	6		T8	19		T9	4
valid_sources[0x42]	7484	1			T3	1		T5	2		T8	17
valid_sources[0x43]	7659	1			T2	26		T3	2		T5	3
valid_sources[0x44]	5851	1			T2	5		T5	1		T8	22
valid_sources[0x45]	7323	1			T2	2		T5	2		T8	24
valid_sources[0x46]	7794	1			T5	1		T8	11		T9	3
valid_sources[0x47]	7464	1			T3	1		T5	1		T8	20
valid_sources[0x48]	6930	1			T3	4		T5	2		T8	24
valid_sources[0x49]	19703	1			T2	25		T3	1		T8	17
valid_sources[0x4a]	8282	1			T3	1		T8	20		T9	4
valid_sources[0x4b]	6807	1			T5	1		T8	14		T9	3
valid_sources[0x4c]	7021	1			T2	4		T5	1		T8	21
valid_sources[0x4d]	6533	1			T2	16		T5	3		T8	14
valid_sources[0x4e]	6480	1			T2	5		T8	15		T9	1
valid_sources[0x4f]	6227	1			T3	2		T5	1		T8	27
valid_sources[0x50]	8896	1			T3	1		T5	1		T8	18
valid_sources[0x51]	6590	1			T5	1		T8	22		T9	1
valid_sources[0x52]	6491	1			T3	1		T5	2		T8	26
valid_sources[0x53]	8240	1			T3	1		T5	2		T8	18
valid_sources[0x54]	8071	1			T2	49		T5	2		T8	15
valid_sources[0x55]	6527	1			T5	1		T8	15		T10	1
valid_sources[0x56]	8840	1			T2	21		T5	1		T8	21
valid_sources[0x57]	6334	1			T2	89		T5	1		T8	16
valid_sources[0x58]	6651	1			T2	3		T8	19		T9	1
valid_sources[0x59]	8182	1			T2	28		T5	1		T8	19
valid_sources[0x5a]	6713	1			T2	10		T8	14		T10	2
valid_sources[0x5b]	6072	1			T2	17		T8	10		T10	2
valid_sources[0x5c]	7392	1			T2	2		T3	1		T5	1
valid_sources[0x5d]	6456	1			T2	10		T3	1		T8	16
valid_sources[0x5e]	7863	1			T2	44		T8	24		T10	2
valid_sources[0x5f]	6468	1			T3	1		T8	22		T9	6
valid_sources[0x60]	9129	1			T2	10		T5	1		T8	16
valid_sources[0x61]	6597	1			T5	1		T8	17		T9	4
valid_sources[0x62]	6496	1			T2	34		T3	1		T5	1
valid_sources[0x63]	7754	1			T3	3		T5	2		T8	20
valid_sources[0x64]	8435	1			T8	12		T10	7		T12	5
valid_sources[0x65]	7450	1			T2	5		T5	1		T8	24
valid_sources[0x66]	8462	1			T8	16		T10	3		T12	1
valid_sources[0x67]	28343	1			T2	37		T5	1		T8	17
valid_sources[0x68]	9689	1			T2	13		T3	1		T5	1
valid_sources[0x69]	6476	1			T3	2		T5	3		T8	22
valid_sources[0x6a]	8856	1			T2	22		T3	1		T5	1
valid_sources[0x6b]	7099	1			T2	20		T3	1		T8	19
valid_sources[0x6c]	6015	1			T3	2		T5	1		T8	23
valid_sources[0x6d]	6360	1			T8	22		T9	2		T10	2
valid_sources[0x6e]	6175	1			T2	1		T8	25		T9	1
valid_sources[0x6f]	6873	1			T8	12		T10	6		T12	1
valid_sources[0x70]	7114	1			T3	1		T5	1		T8	30
valid_sources[0x71]	6172	1			T3	3		T5	1		T8	18
valid_sources[0x72]	6684	1			T5	4		T8	18		T9	2
valid_sources[0x73]	6335	1			T5	2		T8	26		T10	1
valid_sources[0x74]	6324	1			T2	10		T3	1		T5	1
valid_sources[0x75]	6459	1			T8	11		T10	4		T12	3
valid_sources[0x76]	6571	1			T3	1		T5	2		T8	21
valid_sources[0x77]	6459	1			T8	23		T9	4		T10	2
valid_sources[0x78]	13962	1			T2	30		T5	1		T8	9
valid_sources[0x79]	6251	1			T5	2		T8	19		T9	6
valid_sources[0x7a]	17980	1			T3	1		T5	2		T8	15
valid_sources[0x7b]	18601	1			T3	1		T8	16		T9	1
valid_sources[0x7c]	7364	1			T3	1		T8	27		T9	3
valid_sources[0x7d]	6790	1			T2	20		T3	1		T8	13
valid_sources[0x7e]	7419	1			T5	1		T8	19		T9	3
valid_sources[0x7f]	6333	1			T3	1		T8	21		T10	2
valid_sources[0x80]	6592	1			T3	1		T5	1		T8	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35203

1

T4

17

T15

696

T6

14

values[0x0]

all_enables

biggest_size

47223

1

T1

2

T3

1

T4

5

values[0x1]

all_enables

biggest_size

45257

1

T2

1

T4

3

T5

2