Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14237928

1

T1

213819

T2

23027

T4

23

full_word

53859437

1

T1

47440

T2

233104

T3

12288

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68097055	1			T1	261259		T2	256131		T3	12288
auto[TlIntgErrCmd]	111	1			T42	5		T43	5		T44	3
auto[TlIntgErrData]	92	1			T42	1		T43	2		T44	6
auto[TlIntgErrBoth]	107	1			T42	4		T43	3		T44	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31269972

1

T1

130382

T2

128603

T3

6144

auto[1]

36827393

1

T1

130877

T2

127528

T3

6144

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6824244	1			T1	106738		T2	11533		T4	12
auto[TlIntgErrNone]	partial	auto[1]	7413401	1			T1	107081		T2	11494		T4	11
auto[TlIntgErrNone]	full_word	auto[0]	24445584	1			T1	23644		T2	117070		T3	6144
auto[TlIntgErrNone]	full_word	auto[1]	29413826	1			T1	23796		T2	116034		T3	6144
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T43	2		T44	1		T120	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T42	5		T43	3		T44	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T92	2		T95	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T92	1		T79	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T42	1		T43	1		T44	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T43	1		T44	3		T120	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T44	2		T120	1		T96	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T96	1		T117	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T42	2		T43	1		T120	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T42	2		T43	2		T44	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T118	1		T125	1		T126	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T92	1		T95	2		-	-