Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	676212	1			T4	9		T13	1030		T14	10
auto[1]	10660149	1			T1	109629		T2	108120		T4	7
auto[2]	564288	1			T4	5		T13	936		T14	1
auto[3]	10558778	1			T1	110010		T2	107057		T4	7

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13929291	1			T1	7281		T2	178320		T4	23
auto[1]	2216122	1			T1	32555		T2	17488		T4	1
auto[2]	2211938	1			T1	32886		T2	17572		T4	4
auto[3]	4102076	1			T1	146917		T2	1797		T8	236

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8165327

1

T2

28

T4

28

T8

30653

auto[1]

14294100

1

T1

219639

T2

215149

T8

27

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	303260	1			T4	9		T13	851		T14	10
auto[0]	auto[0]	auto[1]	30993	1			T13	86		T139	110		T140	88
auto[0]	auto[0]	auto[2]	30567	1			T13	86		T136	1		T139	105
auto[0]	auto[0]	auto[3]	6874	1			T13	7		T136	6		T139	8
auto[0]	auto[1]	auto[0]	3039756	1			T2	15		T4	5		T8	12648
auto[0]	auto[1]	auto[1]	329427	1			T8	1223		T9	1		T10	487
auto[0]	auto[1]	auto[2]	309467	1			T2	4		T4	2		T8	1235
auto[0]	auto[1]	auto[3]	78980	1			T8	113		T9	638		T10	35
auto[0]	auto[2]	auto[0]	265961	1			T4	5		T13	770		T14	1
auto[0]	auto[2]	auto[1]	26955	1			T13	94		T139	83		T140	85
auto[0]	auto[2]	auto[2]	24019	1			T13	63		T136	1		T139	71
auto[0]	auto[2]	auto[3]	5457	1			T13	8		T136	4		T139	1
auto[0]	auto[3]	auto[0]	3002749	1			T2	9		T4	4		T8	12829
auto[0]	auto[3]	auto[1]	304261	1			T4	1		T8	1248		T9	90
auto[0]	auto[3]	auto[2]	324483	1			T4	2		T8	1234		T9	79
auto[0]	auto[3]	auto[3]	82118	1			T8	123		T9	805		T10	43
auto[1]	auto[0]	auto[0]	10407	1			T136	1221		T139	1		T21	20
auto[1]	auto[0]	auto[1]	45443	1			T136	5238		T131	1		T34	1
auto[1]	auto[0]	auto[2]	45237	1			T136	5238		T139	1		T34	2
auto[1]	auto[0]	auto[3]	203431	1			T136	23756		T131	1		T137	7274
auto[1]	auto[1]	auto[0]	3648454	1			T1	3633		T2	89600		T8	15
auto[1]	auto[1]	auto[1]	729342	1			T1	16246		T2	8759		T8	1
auto[1]	auto[1]	auto[2]	722367	1			T1	16513		T2	8826		T8	1
auto[1]	auto[1]	auto[3]	1802356	1			T1	73237		T2	916		T9	2
auto[1]	auto[2]	auto[0]	8740	1			T13	1		T136	1095		T139	1
auto[1]	auto[2]	auto[1]	37873	1			T136	4699		T131	2		T141	1
auto[1]	auto[2]	auto[2]	35374	1			T136	3560		T21	1		T131	3
auto[1]	auto[2]	auto[3]	159909	1			T136	15726		T137	7093		T138	5365
auto[1]	auto[3]	auto[0]	3649964	1			T1	3648		T2	88696		T8	9
auto[1]	auto[3]	auto[1]	711828	1			T1	16309		T2	8729		T8	1
auto[1]	auto[3]	auto[2]	720424	1			T1	16373		T2	8742		T10	1
auto[1]	auto[3]	auto[3]	1762951	1			T1	73680		T2	881		T11	52876