Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	334854457	115175	0	0
ctrl_regwen_rd_A	334854457	6470	0	0
exec_rd_A	334854457	5807	0	0
exec_regwen_rd_A	334854457	6545	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334854457	115175	0	0
T6	35453	0	0	0
T7	30878	0	0	0
T13	89342	927	0	0
T14	0	2537	0	0
T15	78841	2464	0	0
T16	234532	0	0	0
T22	1144	0	0	0
T29	2747	0	0	0
T42	0	3	0	0
T45	0	4375	0	0
T46	0	735	0	0
T47	0	711	0	0
T48	0	927	0	0
T49	0	412	0	0
T50	0	11	0	0
T52	181183	0	0	0
T53	8925	0	0	0
T54	11972	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334854457	6470	0	0
T7	30878	0	0	0
T13	89342	253	0	0
T14	67735	465	0	0
T46	0	425	0	0
T51	0	139	0	0
T53	8925	0	0	0
T54	11972	0	0	0
T55	0	2	0	0
T56	0	3	0	0
T60	0	35	0	0
T64	107153	0	0	0
T103	0	6	0	0
T104	131556	0	0	0
T112	0	72	0	0
T113	0	25	0	0
T114	58815	0	0	0
T115	99063	0	0	0
T116	7168	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334854457	5807	0	0
T7	30878	0	0	0
T13	89342	250	0	0
T14	67735	352	0	0
T46	0	392	0	0
T51	0	83	0	0
T53	8925	0	0	0
T54	11972	0	0	0
T55	0	8	0	0
T56	0	6	0	0
T60	0	7	0	0
T64	107153	0	0	0
T103	0	3	0	0
T104	131556	0	0	0
T112	0	62	0	0
T113	0	39	0	0
T114	58815	0	0	0
T115	99063	0	0	0
T116	7168	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334854457	6545	0	0
T7	30878	0	0	0
T13	89342	259	0	0
T14	67735	362	0	0
T46	0	429	0	0
T51	0	78	0	0
T53	8925	0	0	0
T54	11972	0	0	0
T55	0	3	0	0
T56	0	10	0	0
T60	0	24	0	0
T64	107153	0	0	0
T67	0	18	0	0
T104	131556	0	0	0
T112	0	109	0	0
T113	0	42	0	0
T114	58815	0	0	0
T115	99063	0	0	0
T116	7168	0	0	0