Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13642283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57468904

1

T1

4592

T2

129

T3

136512

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35446124	1			T1	2838		T2	877		T3	75135
values[0x0]	16469044	1			T1	1257		T2	383		T3	36045
values[0x1]	19196019	1			T1	1554		T2	769		T3	39087

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6796339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64314848

1

T1

5151

T2

928

T3

143411

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	287274	1			T1	23		T2	12		T3	586
valid_sources[0x01]	301691	1			T1	20		T2	11		T3	597
valid_sources[0x02]	325258	1			T1	30		T2	9		T3	576
valid_sources[0x03]	265147	1			T1	15		T2	10		T3	629
valid_sources[0x04]	240671	1			T1	31		T2	18		T3	641
valid_sources[0x05]	256044	1			T1	18		T2	5		T3	534
valid_sources[0x06]	280816	1			T1	23		T2	5		T3	542
valid_sources[0x07]	247380	1			T1	21		T2	4		T3	599
valid_sources[0x08]	251603	1			T1	19		T2	6		T3	534
valid_sources[0x09]	250137	1			T1	25		T2	9		T3	578
valid_sources[0x0a]	302836	1			T1	24		T2	4		T3	561
valid_sources[0x0b]	268462	1			T1	23		T2	6		T3	613
valid_sources[0x0c]	318962	1			T1	15		T2	21		T3	585
valid_sources[0x0d]	302094	1			T1	16		T2	4		T3	589
valid_sources[0x0e]	303072	1			T1	18		T2	4		T3	611
valid_sources[0x0f]	271496	1			T1	25		T2	1		T3	596
valid_sources[0x10]	256038	1			T1	23		T2	5		T3	630
valid_sources[0x11]	249271	1			T1	25		T2	5		T3	586
valid_sources[0x12]	292450	1			T1	19		T2	14		T3	636
valid_sources[0x13]	270443	1			T1	23		T2	7		T3	560
valid_sources[0x14]	261254	1			T1	24		T2	11		T3	591
valid_sources[0x15]	273784	1			T1	30		T2	4		T3	598
valid_sources[0x16]	249960	1			T1	23		T2	3		T3	566
valid_sources[0x17]	338517	1			T1	15		T2	12		T3	587
valid_sources[0x18]	231243	1			T1	19		T2	6		T3	635
valid_sources[0x19]	264056	1			T1	23		T2	1		T3	614
valid_sources[0x1a]	253118	1			T1	22		T2	16		T3	570
valid_sources[0x1b]	294693	1			T1	17		T2	10		T3	576
valid_sources[0x1c]	345187	1			T1	21		T2	6		T3	564
valid_sources[0x1d]	274121	1			T1	22		T2	12		T3	549
valid_sources[0x1e]	262865	1			T1	15		T2	9		T3	553
valid_sources[0x1f]	274154	1			T1	26		T2	7		T3	588
valid_sources[0x20]	253969	1			T1	25		T2	2		T3	558
valid_sources[0x21]	266832	1			T1	24		T2	4		T3	560
valid_sources[0x22]	289564	1			T1	17		T2	5		T3	563
valid_sources[0x23]	275510	1			T1	17		T2	10		T3	590
valid_sources[0x24]	321625	1			T1	28		T2	8		T3	597
valid_sources[0x25]	359457	1			T1	18		T2	10		T3	599
valid_sources[0x26]	234788	1			T1	22		T2	6		T3	585
valid_sources[0x27]	278620	1			T1	24		T2	12		T3	615
valid_sources[0x28]	274294	1			T1	21		T2	10		T3	597
valid_sources[0x29]	249251	1			T1	22		T2	5		T3	562
valid_sources[0x2a]	320416	1			T1	24		T2	13		T3	610
valid_sources[0x2b]	343272	1			T1	25		T2	4		T3	545
valid_sources[0x2c]	278244	1			T1	19		T2	2		T3	619
valid_sources[0x2d]	273343	1			T1	22		T2	9		T3	626
valid_sources[0x2e]	266026	1			T1	25		T2	15		T3	605
valid_sources[0x2f]	303459	1			T1	29		T2	1		T3	559
valid_sources[0x30]	260052	1			T1	21		T2	5		T3	620
valid_sources[0x31]	281935	1			T1	19		T2	7		T3	620
valid_sources[0x32]	252101	1			T1	22		T2	15		T3	585
valid_sources[0x33]	240775	1			T1	22		T2	14		T3	587
valid_sources[0x34]	237910	1			T1	19		T2	4		T3	595
valid_sources[0x35]	270695	1			T1	12		T2	9		T3	548
valid_sources[0x36]	241172	1			T1	18		T2	7		T3	583
valid_sources[0x37]	234312	1			T1	18		T2	7		T3	571
valid_sources[0x38]	261514	1			T1	11		T2	3		T3	565
valid_sources[0x39]	346614	1			T1	21		T2	7		T3	612
valid_sources[0x3a]	250710	1			T1	19		T2	9		T3	613
valid_sources[0x3b]	237468	1			T1	19		T2	10		T3	570
valid_sources[0x3c]	277744	1			T1	23		T2	12		T3	564
valid_sources[0x3d]	297050	1			T1	13		T2	10		T3	620
valid_sources[0x3e]	282498	1			T1	27		T2	7		T3	622
valid_sources[0x3f]	317511	1			T1	23		T2	5		T3	527
valid_sources[0x40]	300207	1			T1	24		T2	5		T3	587
valid_sources[0x41]	256913	1			T1	23		T2	6		T3	623
valid_sources[0x42]	261537	1			T1	16		T2	13		T3	628
valid_sources[0x43]	268703	1			T1	20		T2	3		T3	594
valid_sources[0x44]	263840	1			T1	25		T2	5		T3	557
valid_sources[0x45]	277664	1			T1	16		T2	5		T3	575
valid_sources[0x46]	278290	1			T1	20		T2	6		T3	581
valid_sources[0x47]	261516	1			T1	26		T2	4		T3	556
valid_sources[0x48]	354049	1			T1	19		T2	20		T3	596
valid_sources[0x49]	280080	1			T1	23		T2	10		T3	602
valid_sources[0x4a]	271178	1			T1	22		T2	11		T3	556
valid_sources[0x4b]	248918	1			T1	30		T2	2		T3	591
valid_sources[0x4c]	298208	1			T1	23		T2	6		T3	584
valid_sources[0x4d]	262713	1			T1	18		T2	8		T3	564
valid_sources[0x4e]	280181	1			T1	14		T2	6		T3	558
valid_sources[0x4f]	256680	1			T1	16		T2	10		T3	576
valid_sources[0x50]	308440	1			T1	26		T2	9		T3	584
valid_sources[0x51]	238442	1			T1	21		T2	9		T3	609
valid_sources[0x52]	246889	1			T1	12		T2	7		T3	577
valid_sources[0x53]	260568	1			T1	20		T2	10		T3	643
valid_sources[0x54]	285618	1			T1	25		T2	9		T3	535
valid_sources[0x55]	245879	1			T1	24		T2	11		T3	583
valid_sources[0x56]	251364	1			T1	23		T2	5		T3	586
valid_sources[0x57]	274244	1			T1	17		T2	3		T3	566
valid_sources[0x58]	271712	1			T1	16		T2	6		T3	580
valid_sources[0x59]	314463	1			T1	23		T2	14		T3	597
valid_sources[0x5a]	313917	1			T1	29		T2	8		T3	579
valid_sources[0x5b]	266256	1			T1	10		T2	12		T3	610
valid_sources[0x5c]	268800	1			T1	16		T2	18		T3	621
valid_sources[0x5d]	276661	1			T1	21		T2	1		T3	545
valid_sources[0x5e]	249494	1			T1	21		T2	7		T3	605
valid_sources[0x5f]	324012	1			T1	27		T2	6		T3	612
valid_sources[0x60]	284761	1			T1	30		T2	9		T3	587
valid_sources[0x61]	272293	1			T1	18		T2	7		T3	580
valid_sources[0x62]	259493	1			T1	24		T2	14		T3	638
valid_sources[0x63]	334272	1			T1	20		T2	10		T3	586
valid_sources[0x64]	259651	1			T1	30		T2	6		T3	547
valid_sources[0x65]	302297	1			T1	22		T2	14		T3	587
valid_sources[0x66]	289285	1			T1	30		T2	7		T3	588
valid_sources[0x67]	315871	1			T1	14		T2	9		T3	564
valid_sources[0x68]	281933	1			T1	22		T2	8		T3	635
valid_sources[0x69]	244346	1			T1	20		T3	604		T7	28
valid_sources[0x6a]	263527	1			T1	23		T2	3		T3	587
valid_sources[0x6b]	254937	1			T1	23		T2	6		T3	582
valid_sources[0x6c]	247191	1			T1	19		T2	12		T3	622
valid_sources[0x6d]	246494	1			T1	24		T2	6		T3	576
valid_sources[0x6e]	267488	1			T1	25		T2	6		T3	567
valid_sources[0x6f]	280174	1			T1	17		T2	14		T3	594
valid_sources[0x70]	243986	1			T1	24		T2	12		T3	581
valid_sources[0x71]	294616	1			T1	20		T2	10		T3	574
valid_sources[0x72]	250572	1			T1	27		T2	16		T3	559
valid_sources[0x73]	244142	1			T1	19		T2	6		T3	568
valid_sources[0x74]	313228	1			T1	24		T2	6		T3	579
valid_sources[0x75]	274027	1			T1	25		T2	17		T3	618
valid_sources[0x76]	355469	1			T1	23		T2	6		T3	587
valid_sources[0x77]	263400	1			T1	11		T2	6		T3	586
valid_sources[0x78]	245730	1			T1	19		T2	6		T3	582
valid_sources[0x79]	247518	1			T1	17		T2	3		T3	622
valid_sources[0x7a]	256092	1			T1	24		T2	5		T3	617
valid_sources[0x7b]	300778	1			T1	21		T2	15		T3	574
valid_sources[0x7c]	260357	1			T1	24		T2	2		T3	610
valid_sources[0x7d]	261634	1			T1	24		T2	9		T3	563
valid_sources[0x7e]	266144	1			T1	26		T2	1		T3	558
valid_sources[0x7f]	301462	1			T1	24		T2	3		T3	552
valid_sources[0x80]	293305	1			T1	17		T2	11		T3	576

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28629877

1

T1

2321

T2

8

T3

68190

values[0x0]

all_enables

biggest_size

14420265

1

T1

1111

T2

70

T3

34020

values[0x1]

all_enables

biggest_size

14418762

1

T1

1160

T2

51

T3

34302

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2133609	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140655

1

T1

1

T3

5

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2152781	1			T1	1073		T2	148		T3	6244
values[0x0]	58585	1			T1	1		T3	10		T7	1
values[0x1]	62898	1			T1	1		T2	1		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1425546	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

848718

1

T1

335

T2

43

T3

2039

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7853	1			T1	2		T2	2		T3	54
valid_sources[0x01]	6781	1			T1	3		T2	1		T3	92
valid_sources[0x02]	6734	1			T1	1		T8	2		T4	8
valid_sources[0x03]	6848	1			T2	1		T3	2		T8	1
valid_sources[0x04]	10227	1			T1	3		T2	2		T8	4
valid_sources[0x05]	17816	1			T1	1		T2	1		T3	18
valid_sources[0x06]	10229	1			T1	5		T8	3		T9	6
valid_sources[0x07]	6744	1			T2	1		T8	5		T9	2
valid_sources[0x08]	14171	1			T1	3		T2	1		T3	32
valid_sources[0x09]	7051	1			T8	4		T9	3		T4	2
valid_sources[0x0a]	6863	1			T1	5		T2	1		T3	39
valid_sources[0x0b]	8441	1			T1	15		T2	3		T8	4
valid_sources[0x0c]	6705	1			T1	2		T8	1		T11	3
valid_sources[0x0d]	6846	1			T1	7		T2	1		T3	31
valid_sources[0x0e]	7330	1			T2	1		T8	4		T4	2
valid_sources[0x0f]	8614	1			T1	10		T2	1		T3	4
valid_sources[0x10]	7769	1			T1	10		T3	76		T8	8
valid_sources[0x11]	6699	1			T1	1		T2	2		T8	2
valid_sources[0x12]	7137	1			T1	9		T2	1		T8	2
valid_sources[0x13]	6834	1			T1	9		T2	2		T3	46
valid_sources[0x14]	15997	1			T1	8		T9	8		T4	2
valid_sources[0x15]	6277	1			T1	4		T2	1		T8	7
valid_sources[0x16]	6808	1			T2	5		T8	2		T9	7
valid_sources[0x17]	8737	1			T1	1		T2	1		T3	58
valid_sources[0x18]	14447	1			T1	1		T8	5		T9	8
valid_sources[0x19]	8887	1			T1	7		T3	17		T8	2
valid_sources[0x1a]	6816	1			T1	5		T8	8		T11	4
valid_sources[0x1b]	8237	1			T8	1		T9	4		T4	2
valid_sources[0x1c]	6794	1			T1	7		T2	1		T8	2
valid_sources[0x1d]	7426	1			T2	1		T8	9		T9	5
valid_sources[0x1e]	7144	1			T1	2		T8	3		T9	2
valid_sources[0x1f]	48636	1			T1	2		T3	36		T8	6
valid_sources[0x20]	6888	1			T1	2		T8	4		T9	1
valid_sources[0x21]	6852	1			T3	13		T8	10		T9	6
valid_sources[0x22]	10122	1			T1	3		T2	2		T3	129
valid_sources[0x23]	7114	1			T1	3		T3	3		T8	4
valid_sources[0x24]	7088	1			T8	4		T9	7		T11	3
valid_sources[0x25]	7022	1			T1	7		T8	5		T9	1
valid_sources[0x26]	7004	1			T1	1		T2	1		T8	3
valid_sources[0x27]	6942	1			T1	1		T2	1		T3	81
valid_sources[0x28]	7648	1			T1	10		T2	2		T8	5
valid_sources[0x29]	9034	1			T1	8		T3	29		T8	5
valid_sources[0x2a]	7055	1			T1	7		T3	68		T8	3
valid_sources[0x2b]	6819	1			T3	73		T8	7		T4	2
valid_sources[0x2c]	15277	1			T3	36		T8	5		T9	9
valid_sources[0x2d]	6719	1			T1	2		T8	4		T9	5
valid_sources[0x2e]	9269	1			T1	7		T3	18		T8	7
valid_sources[0x2f]	18673	1			T1	4		T3	2		T8	7
valid_sources[0x30]	7251	1			T1	4		T8	2		T9	5
valid_sources[0x31]	6825	1			T1	7		T8	5		T9	7
valid_sources[0x32]	8519	1			T1	5		T8	5		T9	2
valid_sources[0x33]	7065	1			T8	1		T9	1		T4	3
valid_sources[0x34]	6941	1			T1	2		T3	7		T8	10
valid_sources[0x35]	7196	1			T1	9		T2	2		T8	1
valid_sources[0x36]	6983	1			T1	4		T3	28		T8	5
valid_sources[0x37]	7034	1			T1	3		T2	1		T3	155
valid_sources[0x38]	7584	1			T3	14		T8	2		T9	12
valid_sources[0x39]	8994	1			T1	2		T2	2		T8	10
valid_sources[0x3a]	7532	1			T1	5		T3	17		T8	5
valid_sources[0x3b]	6750	1			T1	4		T3	37		T8	3
valid_sources[0x3c]	9434	1			T1	1		T3	34		T8	7
valid_sources[0x3d]	8663	1			T1	19		T3	51		T8	3
valid_sources[0x3e]	6927	1			T1	2		T3	6		T8	4
valid_sources[0x3f]	7056	1			T1	1		T3	35		T8	3
valid_sources[0x40]	6920	1			T3	3		T8	6		T9	2
valid_sources[0x41]	7027	1			T1	9		T3	13		T8	4
valid_sources[0x42]	7252	1			T1	2		T8	6		T9	3
valid_sources[0x43]	6787	1			T3	11		T8	2		T4	1
valid_sources[0x44]	6305	1			T1	3		T2	1		T8	10
valid_sources[0x45]	6636	1			T1	2		T4	3		T11	6
valid_sources[0x46]	11051	1			T1	4		T8	12		T9	4
valid_sources[0x47]	6859	1			T1	5		T2	1		T3	54
valid_sources[0x48]	6634	1			T1	2		T8	4		T9	17
valid_sources[0x49]	6705	1			T1	3		T2	1		T3	31
valid_sources[0x4a]	7242	1			T2	1		T3	4		T8	2
valid_sources[0x4b]	7977	1			T1	3		T3	3		T8	2
valid_sources[0x4c]	9093	1			T1	14		T2	1		T8	4
valid_sources[0x4d]	18296	1			T1	2		T2	1		T8	4
valid_sources[0x4e]	9363	1			T1	11		T3	38		T8	4
valid_sources[0x4f]	6292	1			T1	1		T3	11		T8	10
valid_sources[0x50]	6977	1			T1	5		T2	1		T8	9
valid_sources[0x51]	17379	1			T1	8		T8	4		T9	1
valid_sources[0x52]	14608	1			T8	4		T4	1		T11	2
valid_sources[0x53]	6647	1			T1	1		T2	2		T3	17
valid_sources[0x54]	6848	1			T1	9		T8	5		T11	6
valid_sources[0x55]	9418	1			T1	3		T2	2		T3	43
valid_sources[0x56]	13540	1			T8	7		T9	7		T4	1
valid_sources[0x57]	9163	1			T1	3		T2	1		T8	6
valid_sources[0x58]	6864	1			T1	2		T2	1		T8	4
valid_sources[0x59]	9202	1			T1	5		T8	9		T11	4
valid_sources[0x5a]	6972	1			T2	3		T8	1		T9	2
valid_sources[0x5b]	6766	1			T1	4		T3	52		T8	5
valid_sources[0x5c]	8049	1			T1	2		T3	78		T8	6
valid_sources[0x5d]	9185	1			T2	3		T3	16		T8	3
valid_sources[0x5e]	6853	1			T2	1		T3	7		T8	2
valid_sources[0x5f]	7235	1			T3	5		T8	6		T9	20
valid_sources[0x60]	8754	1			T1	5		T3	92		T8	7
valid_sources[0x61]	6489	1			T2	1		T8	2		T9	9
valid_sources[0x62]	17663	1			T1	21		T3	25		T8	5
valid_sources[0x63]	9033	1			T1	13		T8	5		T9	4
valid_sources[0x64]	6549	1			T1	3		T8	5		T9	12
valid_sources[0x65]	7071	1			T2	1		T3	41		T8	3
valid_sources[0x66]	6819	1			T1	7		T2	1		T8	9
valid_sources[0x67]	6870	1			T1	8		T3	43		T8	2
valid_sources[0x68]	6907	1			T2	3		T3	8		T8	6
valid_sources[0x69]	7113	1			T1	6		T2	2		T3	120
valid_sources[0x6a]	8183	1			T1	6		T8	1		T9	7
valid_sources[0x6b]	10088	1			T1	4		T2	2		T3	59
valid_sources[0x6c]	6887	1			T1	6		T2	2		T3	26
valid_sources[0x6d]	6778	1			T1	6		T3	118		T8	3
valid_sources[0x6e]	8516	1			T1	3		T3	53		T8	2
valid_sources[0x6f]	8344	1			T1	10		T8	4		T4	2
valid_sources[0x70]	7163	1			T1	1		T2	2		T3	125
valid_sources[0x71]	6440	1			T1	8		T2	3		T3	33
valid_sources[0x72]	7055	1			T1	12		T3	10		T8	2
valid_sources[0x73]	7610	1			T1	6		T3	135		T8	4
valid_sources[0x74]	7118	1			T1	3		T8	5		T9	4
valid_sources[0x75]	7837	1			T1	1		T2	1		T3	33
valid_sources[0x76]	7000	1			T1	1		T8	10		T9	1
valid_sources[0x77]	11341	1			T1	9		T3	39		T8	2
valid_sources[0x78]	7176	1			T1	1		T8	2		T9	7
valid_sources[0x79]	7065	1			T1	2		T8	6		T11	3
valid_sources[0x7a]	9990	1			T1	2		T8	2		T9	1
valid_sources[0x7b]	6998	1			T1	4		T2	1		T3	11
valid_sources[0x7c]	8405	1			T1	4		T2	1		T8	4
valid_sources[0x7d]	28609	1			T1	2		T8	4		T4	2
valid_sources[0x7e]	13382	1			T1	16		T3	48		T8	3
valid_sources[0x7f]	6530	1			T1	8		T2	1		T8	4
valid_sources[0x80]	6687	1			T1	6		T2	1		T8	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38304

1

T10

4

T4

3

T13

433

values[0x0]

all_enables

biggest_size

51801

1

T1

1

T3

4

T8

1

values[0x1]

all_enables

biggest_size

50550

1

T3

1

T10

3

T11

1