Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13380654

1

T1

1057

T2

1900

T3

13755

full_word

52860039

1

T1

4592

T2

129

T3

136512

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66240433	1			T1	5649		T2	2029		T3	150267
auto[TlIntgErrCmd]	94	1			T42	2		T43	3		T69	4
auto[TlIntgErrData]	68	1			T42	4		T43	2		T69	3
auto[TlIntgErrBoth]	98	1			T42	4		T43	5		T69	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30501482

1

T1

2838

T2

877

T3

75135

auto[1]

35739211

1

T1

2811

T2

1152

T3

75132

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6403315	1			T1	517		T2	869		T3	6945
auto[TlIntgErrNone]	partial	auto[1]	6977094	1			T1	540		T2	1031		T3	6810
auto[TlIntgErrNone]	full_word	auto[0]	24098040	1			T1	2321		T2	8		T3	68190
auto[TlIntgErrNone]	full_word	auto[1]	28761984	1			T1	2271		T2	121		T3	68322
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T42	1		T43	1		T69	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T42	1		T43	2		T69	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T69	1		T83	1		T117	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T118	1		T91	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	30	1			T42	2		T43	1		T69	2
auto[TlIntgErrData]	partial	auto[1]	36	1			T42	2		T43	1		T69	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T81	1		T120	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T42	2		T43	2		T69	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T42	2		T43	3		T69	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T118	1		T109	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T83	1		T121	1		-	-