Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	559467	1			T4	1		T13	13		T14	1335
auto[1]	11261906	1			T1	2838		T2	88		T3	37002
auto[2]	463330	1			T4	4		T13	13		T14	936
auto[3]	11172085	1			T1	2810		T2	186		T3	36795

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14613212	1			T1	3687		T2	1		T3	61132
auto[1]	2330147	1			T1	904		T2	4		T3	5894
auto[2]	2321100	1			T1	869		T2	18		T3	6168
auto[3]	4192329	1			T1	188		T2	251		T3	603

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8837896

1

T1

5640

T2

274

T3

73730

auto[1]

14618892

1

T1

8

T3

67

T7

14

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	253004	1			T4	1		T13	12		T14	47
auto[0]	auto[0]	auto[1]	25903	1			T14	170		T137	142		T138	381
auto[0]	auto[0]	auto[2]	25620	1			T13	1		T14	171		T137	148
auto[0]	auto[0]	auto[3]	9147	1			T14	947		T137	17		T138	53
auto[0]	auto[1]	auto[0]	3361917	1			T1	1865		T3	30663		T7	2976
auto[0]	auto[1]	auto[1]	358639	1			T1	450		T3	2864		T7	834
auto[0]	auto[1]	auto[2]	344081	1			T1	417		T2	4		T3	3142
auto[0]	auto[1]	auto[3]	84629	1			T1	100		T2	84		T3	299
auto[0]	auto[2]	auto[0]	214891	1			T4	3		T13	10		T14	44
auto[0]	auto[2]	auto[1]	22311	1			T4	1		T13	3		T14	188
auto[0]	auto[2]	auto[2]	21008	1			T14	136		T137	94		T138	275
auto[0]	auto[2]	auto[3]	6515	1			T14	567		T137	7		T138	29
auto[0]	auto[3]	auto[0]	3327717	1			T1	1817		T2	1		T3	30417
auto[0]	auto[3]	auto[1]	340644	1			T1	451		T2	4		T3	3023
auto[0]	auto[3]	auto[2]	355508	1			T1	452		T2	14		T3	3019
auto[0]	auto[3]	auto[3]	86362	1			T1	88		T2	167		T3	303
auto[1]	auto[0]	auto[0]	8318	1			T137	1		T138	2		T105	655
auto[1]	auto[0]	auto[1]	36632	1			T138	1		T105	2973		T139	1
auto[1]	auto[0]	auto[2]	36679	1			T138	1		T105	3051		T140	1
auto[1]	auto[0]	auto[3]	164164	1			T40	3		T105	13479		T141	17555
auto[1]	auto[1]	auto[0]	3722229	1			T1	4		T3	24		T7	5
auto[1]	auto[1]	auto[1]	759888	1			T1	2		T3	3		T7	3
auto[1]	auto[1]	auto[2]	757270	1			T3	6		T62	16723		T51	15689
auto[1]	auto[1]	auto[3]	1873253	1			T3	1		T62	69467		T51	62357
auto[1]	auto[2]	auto[0]	7223	1			T137	5		T138	3		T105	609
auto[1]	auto[2]	auto[1]	31997	1			T137	1		T105	2810		T142	1
auto[1]	auto[2]	auto[2]	28822	1			T105	2471		T140	1		T129	1
auto[1]	auto[2]	auto[3]	130563	1			T14	1		T105	11273		T141	14876
auto[1]	auto[3]	auto[0]	3717913	1			T1	1		T3	28		T7	6
auto[1]	auto[3]	auto[1]	754133	1			T1	1		T3	4		T15	1
auto[1]	auto[3]	auto[2]	752112	1			T3	1		T9	1		T15	1
auto[1]	auto[3]	auto[3]	1837696	1			T62	69575		T51	62218		T53	879