Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	303356605	128626	0	0
ctrl_regwen_rd_A	303356605	6888	0	0
exec_rd_A	303356605	6082	0	0
exec_regwen_rd_A	303356605	6375	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303356605	128626	0	0
T5	40635	0	0	0
T13	42716	1571	0	0
T14	75799	0	0	0
T29	130961	2252	0	0
T30	0	3625	0	0
T31	2723	0	0	0
T32	2531	0	0	0
T44	0	7567	0	0
T45	0	1519	0	0
T46	0	279	0	0
T47	0	403	0	0
T48	0	56	0	0
T49	0	745	0	0
T50	0	522	0	0
T51	483246	0	0	0
T52	19117	0	0	0
T53	296853	0	0	0
T54	599428	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303356605	6888	0	0
T30	175798	618	0	0
T42	8672	25	0	0
T43	0	38	0	0
T45	62722	387	0	0
T46	6146	40	0	0
T49	0	34	0	0
T56	746	5	0	0
T60	0	2	0	0
T68	0	18	0	0
T109	0	94	0	0
T110	13129	0	0	0
T111	10713	0	0	0
T112	63762	0	0	0
T113	345319	0	0	0
T114	28165	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303356605	6082	0	0
T30	175798	758	0	0
T42	8672	28	0	0
T43	0	38	0	0
T45	62722	353	0	0
T46	6146	20	0	0
T49	0	30	0	0
T56	746	3	0	0
T60	0	4	0	0
T68	0	4	0	0
T109	0	80	0	0
T110	13129	0	0	0
T111	10713	0	0	0
T112	63762	0	0	0
T113	345319	0	0	0
T114	28165	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303356605	6375	0	0
T30	175798	693	0	0
T42	8672	54	0	0
T43	0	45	0	0
T45	62722	359	0	0
T46	6146	60	0	0
T49	0	41	0	0
T56	746	2	0	0
T68	0	11	0	0
T109	0	61	0	0
T110	13129	0	0	0
T111	10713	0	0	0
T112	63762	0	0	0
T113	345319	0	0	0
T114	28165	0	0	0
T115	0	22	0	0