Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.46	100.00	95.65	100.00		100.00	91.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.89	100.00	97.78	100.00		100.00	91.67

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	97.78	100.00		100.00	91.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.39	100.00	97.48	100.00	100.00	99.14	99.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sram_ctrl_regs_csr_assert	100.00						100.00
tlul_assert_device_ram	100.00	100.00				100.00	100.00
tlul_assert_device_regs	95.24	100.00				85.71	100.00
u_lfsr	100.00			100.00
u_prim_alert_sender_parity	100.00			100.00
u_prim_count	100.00			100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_prim_ram_1p_scr	98.40	100.00	92.00	100.00		100.00	100.00
u_prim_sync_reqack_data	100.00	100.00	100.00			100.00	100.00
u_reg_regs	99.92	100.00	99.58	100.00		100.00	100.00
u_tlul_adapter_sram	99.25	100.00	96.28	100.00	100.00	99.22	100.00
u_tlul_data_integ_enc	100.00	100.00
u_tlul_lc_gate	96.85	100.00	100.00		100.00	96.77	87.50

Line Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
TOTAL		48	48	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
ALWAYS	216	3	3	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
ALWAYS	284	11	11	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	491	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
134	1	1
137	1	1
141	1	1
144	1	1
176	1	1
178	1	1
186	1	1
192	1	1
200	1	1
209	1	1
212	1	1
216	1	1
217	1	1
219	1	1
228	1	1
229	1	1
253	1	1
254	1	1
265	1	1
266	1	1
270	1	1
271	1	1
275	1	1
276	1	1
280	1	1
281	1	1
284	1	1
285	1	1
288	1	1
289	1	1
291	1	1
292	1	1
293	1	1
294	1	1
			MISSING_ELSE
299	1	1
300	1	1
301	1	1
			MISSING_ELSE
328	1	1
371	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
478	1	1
479	1	1
491	1	1

---

Cond Coverage for Module : sram_ctrl

	Total	Covered	Percent
Conditions	92	88	95.65
Logical	92	88	95.65
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T26,T27

 LINE       144
 EXPRESSION (((|bus_integ_error)) | init_error)
             ----------1---------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       186
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q)
             ------------1------------   -------------2------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T20,T21,T22
0	1	0	Covered	T20,T21,T22
1	0	0	Covered	T4,T5,T6

 LINE       192
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | local_esc_reg)
             ----1---   -----2----   ----------3---------   ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T4,T5,T6
0	0	1	0	Covered	T20,T21,T22
0	1	0	0	Covered	T20,T21,T22
1	0	0	0	Covered	T4,T5,T6

 LINE       209
 EXPRESSION (reg2hw.ctrl.init.q & reg2hw.ctrl.init.qe)
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       228
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       229
 EXPRESSION ((init_cnt == 10'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       229
 SUB-EXPRESSION (init_cnt == 10'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       265
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q & reg2hw.ctrl.renew_scr_key.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       266
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       270
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       275
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       275
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       276
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       280
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       281
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       473
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (sram_gnt & ((~init_req)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T20,T21,T22

 LINE       477
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       478
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       479
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       491
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       491
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       491
 SUB-EXPRESSION (tl_gate_resp_pending & tlul_we)
                 ----------1---------   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T31,T32,T33

---

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	60	60	100.00
Total Bits	1226	1226	100.00
Total Bits 0->1	613	613	100.00
Total Bits 1->0	613	613	100.00

Ports	60	60	100.00
Port Bits	1226	1226	100.00
Port Bits 0->1	613	613	100.00
Port Bits 1->0	613	613	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T10,T5	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T4,T10,T5	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T8,T10	Yes	T3,T8,T10	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T10	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T34,T35,T36	Yes	T34,T35,T37	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T10,T6,T38	Yes	T3,T10,T6	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T3,T10,T6	Yes	T3,T10,T6	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T4,T7	Yes	T1,T3,T4	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	212	3	3	100.00
TERNARY	266	3	3	100.00
TERNARY	275	2	2	100.00
TERNARY	477	2	2	100.00
TERNARY	478	2	2	100.00
TERNARY	479	2	2	100.00
TERNARY	491	3	3	100.00
IF	216	2	2	100.00
IF	284	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(init_done) ? 
-2-:	212	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	(key_req) ? 
-2-:	266	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	275	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	477	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	478	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	479	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	491	(key_req_pending_q) ? 
-2-:	491	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	216	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	292	if (key_ack)
-3-:	299	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T4,T5,T6
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : sram_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	11	91.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	11	91.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	332391075	332279714	0	0
FpvSecCmCntCheck_A	332391075	70	0	0
FpvSecCmFifoRptrCheck_A	332391075	70	0	0
FpvSecCmFifoWptrCheck_A	332391075	70	0	0
FpvSecCmLcGateFsmCheck_A	332391075	0	0	0
FpvSecCmRegWeOnehotCheck_A	332391075	70	0	0
NonceWidthsLessThanSource_A	843	843	0	0
RamTlOutKnown_A	332391075	332279714	0	0
RamTlOutPayLoadKnown_A	332391075	136781406	0	0
RamTlOutPayLoadKnown_AKnownEnable	332391075	332279714	0	0
RegsTlOutKnown_A	332391075	332279714	0	0
SramOtpKeyKnown_A	332391075	332279714	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	70	0	0
T20	10600	10	0	0
T21	16352	20	0	0
T22	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	313756	0	0	0
T45	7420	0	0	0
T46	139605	0	0	0
T47	2255	0	0	0
T48	50667	0	0	0
T49	1425	0	0	0
T50	132417	0	0	0
T51	168882	0	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	70	0	0
T20	10600	10	0	0
T21	16352	20	0	0
T22	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	313756	0	0	0
T45	7420	0	0	0
T46	139605	0	0	0
T47	2255	0	0	0
T48	50667	0	0	0
T49	1425	0	0	0
T50	132417	0	0	0
T51	168882	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	70	0	0
T20	10600	10	0	0
T21	16352	20	0	0
T22	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	313756	0	0	0
T45	7420	0	0	0
T46	139605	0	0	0
T47	2255	0	0	0
T48	50667	0	0	0
T49	1425	0	0	0
T50	132417	0	0	0
T51	168882	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	70	0	0
T20	10600	10	0	0
T21	16352	20	0	0
T22	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	313756	0	0	0
T45	7420	0	0	0
T46	139605	0	0	0
T47	2255	0	0	0
T48	50667	0	0	0
T49	1425	0	0	0
T50	132417	0	0	0
T51	168882	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	843	843	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	136781406	0	0
T1	80237	38912	0	0
T2	9597	5029	0	0
T3	228275	36297	0	0
T4	88065	4689	0	0
T7	13613	10000	0	0
T8	320907	267812	0	0
T9	4638	1815	0	0
T10	758046	455707	0	0
T11	30392	14336	0	0
T12	165299	113418	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		48	48	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
ALWAYS	216	3	3	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
ALWAYS	284	11	11	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	491	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
134	1	1
137	1	1
141	1	1
144	1	1
176	1	1
178	1	1
186	1	1
192	1	1
200	1	1
209	1	1
212	1	1
216	1	1
217	1	1
219	1	1
228	1	1
229	1	1
253	1	1
254	1	1
265	1	1
266	1	1
270	1	1
271	1	1
275	1	1
276	1	1
280	1	1
281	1	1
284	1	1
285	1	1
288	1	1
289	1	1
291	1	1
292	1	1
293	1	1
294	1	1
			MISSING_ELSE
299	1	1
300	1	1
301	1	1
			MISSING_ELSE
328	1	1
371	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
478	1	1
479	1	1
491	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	90	88	97.78
Logical	90	88	97.78
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T26,T27

 LINE       144
 EXPRESSION (((|bus_integ_error)) | init_error)
             ----------1---------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       186
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q)
             ------------1------------   -------------2------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T20,T21,T22
0	1	0	Covered	T20,T21,T22
1	0	0	Covered	T4,T5,T6

 LINE       192
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | local_esc_reg)
             ----1---   -----2----   ----------3---------   ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T4,T5,T6
0	0	1	0	Covered	T20,T21,T22
0	1	0	0	Covered	T20,T21,T22
1	0	0	0	Covered	T4,T5,T6

 LINE       209
 EXPRESSION (reg2hw.ctrl.init.q & reg2hw.ctrl.init.qe)
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       228
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       229
 EXPRESSION ((init_cnt == 10'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       229
 SUB-EXPRESSION (init_cnt == 10'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[LOWRISK] we don't issue a new init when there is a unfinished init
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       265
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q & reg2hw.ctrl.renew_scr_key.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       266
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       270
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[UNSUPPORTED] ACK can't come without REQ
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       275
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       275
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       276
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       280
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       281
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       473
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (sram_gnt & ((~init_req)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T20,T21,T22

 LINE       477
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       478
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       479
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       491
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       491
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & tlul_we) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       491
 SUB-EXPRESSION (tl_gate_resp_pending & tlul_we)
                 ----------1---------   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T31,T32,T33

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	60	60	100.00
Total Bits	1226	1226	100.00
Total Bits 0->1	613	613	100.00
Total Bits 1->0	613	613	100.00

Ports	60	60	100.00
Port Bits	1226	1226	100.00
Port Bits 0->1	613	613	100.00
Port Bits 1->0	613	613	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T10,T5	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T4,T10,T5	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T8,T10	Yes	T3,T8,T10	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T10	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T34,T35,T36	Yes	T34,T35,T37	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T10,T6,T38	Yes	T3,T10,T6	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T3,T10,T6	Yes	T3,T10,T6	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T4,T7	Yes	T1,T3,T4	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	212	3	3	100.00
TERNARY	266	3	3	100.00
TERNARY	275	2	2	100.00
TERNARY	477	2	2	100.00
TERNARY	478	2	2	100.00
TERNARY	479	2	2	100.00
TERNARY	491	3	3	100.00
IF	216	2	2	100.00
IF	284	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(init_done) ? 
-2-:	212	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	(key_req) ? 
-2-:	266	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	275	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	477	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	478	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	479	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	491	(key_req_pending_q) ? 
-2-:	491	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	216	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	292	if (key_ack)
-3-:	299	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T4,T5,T6
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	11	91.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	11	91.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	332391075	332279714	0	0
FpvSecCmCntCheck_A	332391075	70	0	0
FpvSecCmFifoRptrCheck_A	332391075	70	0	0
FpvSecCmFifoWptrCheck_A	332391075	70	0	0
FpvSecCmLcGateFsmCheck_A	332391075	0	0	0
FpvSecCmRegWeOnehotCheck_A	332391075	70	0	0
NonceWidthsLessThanSource_A	843	843	0	0
RamTlOutKnown_A	332391075	332279714	0	0
RamTlOutPayLoadKnown_A	332391075	136781406	0	0
RamTlOutPayLoadKnown_AKnownEnable	332391075	332279714	0	0
RegsTlOutKnown_A	332391075	332279714	0	0
SramOtpKeyKnown_A	332391075	332279714	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	70	0	0
T20	10600	10	0	0
T21	16352	20	0	0
T22	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	313756	0	0	0
T45	7420	0	0	0
T46	139605	0	0	0
T47	2255	0	0	0
T48	50667	0	0	0
T49	1425	0	0	0
T50	132417	0	0	0
T51	168882	0	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	70	0	0
T20	10600	10	0	0
T21	16352	20	0	0
T22	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	313756	0	0	0
T45	7420	0	0	0
T46	139605	0	0	0
T47	2255	0	0	0
T48	50667	0	0	0
T49	1425	0	0	0
T50	132417	0	0	0
T51	168882	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	70	0	0
T20	10600	10	0	0
T21	16352	20	0	0
T22	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	313756	0	0	0
T45	7420	0	0	0
T46	139605	0	0	0
T47	2255	0	0	0
T48	50667	0	0	0
T49	1425	0	0	0
T50	132417	0	0	0
T51	168882	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	70	0	0
T20	10600	10	0	0
T21	16352	20	0	0
T22	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	313756	0	0	0
T45	7420	0	0	0
T46	139605	0	0	0
T47	2255	0	0	0
T48	50667	0	0	0
T49	1425	0	0	0
T50	132417	0	0	0
T51	168882	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	843	843	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	136781406	0	0
T1	80237	38912	0	0
T2	9597	5029	0	0
T3	228275	36297	0	0
T4	88065	4689	0	0
T7	13613	10000	0	0
T8	320907	267812	0	0
T9	4638	1815	0	0
T10	758046	455707	0	0
T11	30392	14336	0	0
T12	165299	113418	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332391075	332279714	0	0
T1	80237	80147	0	0
T2	9597	9530	0	0
T3	228275	228208	0	0
T4	88065	84506	0	0
T7	13613	13552	0	0
T8	320907	320848	0	0
T9	4638	4574	0	0
T10	758046	757734	0	0
T11	30392	30326	0	0
T12	165299	165292	0	0