Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	333653914	7212	0	0
ctrl_regwen_rd_A	333653914	1666	0	0
exec_rd_A	333653914	1547	0	0
exec_regwen_rd_A	333653914	1668	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333653914	7212	0	0
T35	8674	2	0	0
T36	25672	4	0	0
T37	3991	506	0	0
T52	5361	222	0	0
T53	3523	326	0	0
T54	4331	626	0	0
T55	10124	3	0	0
T56	3031	162	0	0
T57	10853	397	0	0
T58	11853	409	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333653914	1666	0	0
T59	13383	65	0	0
T61	23024	58	0	0
T63	57486	49	0	0
T66	27079	13	0	0
T68	1558	5	0	0
T69	1278	15	0	0
T70	1164	5	0	0
T104	2131	52	0	0
T105	9228	44	0	0
T106	9556	22	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333653914	1547	0	0
T59	13383	104	0	0
T61	23024	79	0	0
T63	57486	33	0	0
T68	1558	6	0	0
T69	1278	12	0	0
T70	1164	1	0	0
T95	1095	6	0	0
T104	2131	33	0	0
T105	9228	54	0	0
T106	9556	24	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333653914	1668	0	0
T59	13383	126	0	0
T61	23024	87	0	0
T63	57486	33	0	0
T66	27079	28	0	0
T68	1558	10	0	0
T69	1278	3	0	0
T95	1095	4	0	0
T104	2131	41	0	0
T105	9228	75	0	0
T106	9556	4	0	0