Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12571127	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

45390267

1

T1

36864

T2

1068

T3

144055

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28874961	1			T1	18432		T2	576		T3	79190
values[0x0]	13286390	1			T1	9220		T2	288		T3	38160
values[0x1]	15800043	1			T1	9212		T2	306		T3	41123

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6265935	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51695459

1

T1

36864

T2

1125

T3

151281

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	302999	1			T2	9		T3	707		T4	18657
valid_sources[0x01]	220025	1			T2	6		T3	454		T9	25
valid_sources[0x02]	225120	1			T2	1		T3	469		T9	29
valid_sources[0x03]	217517	1			T2	4		T3	644		T4	66
valid_sources[0x04]	205471	1			T2	5		T3	548		T9	27
valid_sources[0x05]	250123	1			T1	36864		T2	5		T3	867
valid_sources[0x06]	205069	1			T2	3		T3	502		T5	86
valid_sources[0x07]	251778	1			T2	5		T3	657		T4	36473
valid_sources[0x08]	222467	1			T2	3		T3	632		T5	13
valid_sources[0x09]	200240	1			T2	6		T3	699		T9	38
valid_sources[0x0a]	216683	1			T2	1		T3	606		T5	32
valid_sources[0x0b]	208660	1			T2	7		T3	759		T9	19
valid_sources[0x0c]	227985	1			T2	3		T3	586		T5	7
valid_sources[0x0d]	218478	1			T2	5		T3	673		T4	5183
valid_sources[0x0e]	208362	1			T2	6		T3	624		T9	18
valid_sources[0x0f]	256121	1			T2	7		T3	581		T5	32
valid_sources[0x10]	204287	1			T2	5		T3	706		T5	21
valid_sources[0x11]	253933	1			T2	5		T3	635		T5	59
valid_sources[0x12]	247865	1			T2	8		T3	621		T9	35
valid_sources[0x13]	199026	1			T2	6		T3	472		T5	25
valid_sources[0x14]	244020	1			T2	4		T3	527		T5	31
valid_sources[0x15]	231754	1			T2	6		T3	701		T9	22
valid_sources[0x16]	200407	1			T2	3		T3	803		T9	27
valid_sources[0x17]	209827	1			T2	7		T3	732		T5	6
valid_sources[0x18]	221832	1			T2	4		T3	644		T9	26
valid_sources[0x19]	199460	1			T2	2		T3	623		T5	28
valid_sources[0x1a]	199138	1			T2	7		T3	664		T5	74
valid_sources[0x1b]	217989	1			T2	2		T3	500		T4	4198
valid_sources[0x1c]	210250	1			T2	3		T3	722		T9	22
valid_sources[0x1d]	287107	1			T2	6		T3	684		T9	20
valid_sources[0x1e]	235363	1			T2	7		T3	668		T9	24
valid_sources[0x1f]	203130	1			T2	6		T3	630		T9	31
valid_sources[0x20]	277039	1			T2	5		T3	508		T5	15
valid_sources[0x21]	198821	1			T2	7		T3	615		T9	15
valid_sources[0x22]	216940	1			T2	2		T3	659		T5	9
valid_sources[0x23]	200844	1			T2	2		T3	530		T4	34
valid_sources[0x24]	242112	1			T2	5		T3	578		T5	68
valid_sources[0x25]	202421	1			T2	3		T3	590		T5	3
valid_sources[0x26]	213735	1			T2	7		T3	625		T9	20
valid_sources[0x27]	196133	1			T2	11		T3	534		T5	88
valid_sources[0x28]	223635	1			T2	4		T3	728		T4	8734
valid_sources[0x29]	220139	1			T2	2		T3	765		T4	14
valid_sources[0x2a]	202671	1			T2	5		T3	649		T9	29
valid_sources[0x2b]	250598	1			T3	701		T5	25		T9	19
valid_sources[0x2c]	222448	1			T2	8		T3	753		T5	5
valid_sources[0x2d]	200405	1			T2	7		T3	708		T4	2788
valid_sources[0x2e]	255378	1			T2	3		T3	792		T5	4
valid_sources[0x2f]	237026	1			T2	3		T3	690		T9	19
valid_sources[0x30]	200058	1			T2	2		T3	490		T9	31
valid_sources[0x31]	255462	1			T2	8		T3	450		T4	148
valid_sources[0x32]	232504	1			T2	4		T3	576		T9	20
valid_sources[0x33]	198987	1			T2	9		T3	458		T4	990
valid_sources[0x34]	209114	1			T2	3		T3	679		T5	2
valid_sources[0x35]	227309	1			T2	5		T3	715		T9	15
valid_sources[0x36]	233962	1			T2	7		T3	682		T9	26
valid_sources[0x37]	234123	1			T3	563		T5	9		T9	15
valid_sources[0x38]	201522	1			T2	6		T3	532		T9	23
valid_sources[0x39]	228027	1			T2	4		T3	843		T4	650
valid_sources[0x3a]	234707	1			T2	2		T3	465		T4	6089
valid_sources[0x3b]	249094	1			T2	1		T3	646		T5	4
valid_sources[0x3c]	262105	1			T2	1		T3	574		T9	26
valid_sources[0x3d]	208150	1			T2	1		T3	706		T5	70
valid_sources[0x3e]	234050	1			T2	3		T3	598		T4	5052
valid_sources[0x3f]	211992	1			T2	5		T3	609		T5	21
valid_sources[0x40]	201931	1			T2	6		T3	606		T5	124
valid_sources[0x41]	198037	1			T2	1		T3	539		T9	14
valid_sources[0x42]	235928	1			T2	3		T3	722		T5	14
valid_sources[0x43]	204223	1			T2	2		T3	420		T9	20
valid_sources[0x44]	240700	1			T2	6		T3	654		T9	24
valid_sources[0x45]	220073	1			T2	7		T3	541		T4	66
valid_sources[0x46]	266123	1			T2	5		T3	775		T4	2772
valid_sources[0x47]	249550	1			T2	6		T3	654		T5	25
valid_sources[0x48]	263095	1			T2	4		T3	677		T9	23
valid_sources[0x49]	216770	1			T3	672		T9	32		T14	1
valid_sources[0x4a]	248043	1			T2	7		T3	558		T9	30
valid_sources[0x4b]	223962	1			T2	6		T3	555		T4	23737
valid_sources[0x4c]	197028	1			T2	8		T3	608		T9	28
valid_sources[0x4d]	200089	1			T2	4		T3	662		T5	14
valid_sources[0x4e]	225388	1			T2	11		T3	546		T5	5
valid_sources[0x4f]	249527	1			T2	1		T3	475		T9	29
valid_sources[0x50]	305600	1			T2	4		T3	566		T9	16
valid_sources[0x51]	207624	1			T2	6		T3	532		T9	20
valid_sources[0x52]	220501	1			T2	3		T3	547		T9	28
valid_sources[0x53]	275178	1			T2	6		T3	612		T5	3
valid_sources[0x54]	276584	1			T2	3		T3	738		T4	59985
valid_sources[0x55]	197582	1			T2	9		T3	660		T5	14
valid_sources[0x56]	210437	1			T2	5		T3	550		T5	39
valid_sources[0x57]	207696	1			T2	6		T3	732		T5	24
valid_sources[0x58]	211372	1			T2	3		T3	615		T9	17
valid_sources[0x59]	225070	1			T2	3		T3	669		T4	1054
valid_sources[0x5a]	197091	1			T2	4		T3	698		T4	80
valid_sources[0x5b]	202477	1			T2	1		T3	623		T7	900
valid_sources[0x5c]	212169	1			T2	6		T3	612		T4	6850
valid_sources[0x5d]	219734	1			T2	5		T3	551		T5	66
valid_sources[0x5e]	277635	1			T2	7		T3	632		T9	22
valid_sources[0x5f]	230182	1			T2	3		T3	665		T5	22
valid_sources[0x60]	216714	1			T2	9		T3	643		T4	161
valid_sources[0x61]	233081	1			T2	5		T3	447		T9	24
valid_sources[0x62]	202243	1			T2	5		T3	496		T9	15
valid_sources[0x63]	213352	1			T2	3		T3	564		T5	2
valid_sources[0x64]	211079	1			T2	5		T3	756		T5	53
valid_sources[0x65]	200094	1			T2	8		T3	715		T5	18
valid_sources[0x66]	235286	1			T2	2		T3	644		T5	35
valid_sources[0x67]	223488	1			T2	3		T3	463		T5	6
valid_sources[0x68]	227683	1			T2	2		T3	548		T8	6142
valid_sources[0x69]	243208	1			T2	3		T3	551		T4	7378
valid_sources[0x6a]	218746	1			T2	8		T3	614		T5	11
valid_sources[0x6b]	223650	1			T2	6		T3	692		T5	20
valid_sources[0x6c]	243518	1			T2	3		T3	533		T9	18
valid_sources[0x6d]	201404	1			T2	7		T3	691		T9	18
valid_sources[0x6e]	249257	1			T2	7		T3	740		T9	25
valid_sources[0x6f]	230110	1			T2	8		T3	465		T5	6
valid_sources[0x70]	209634	1			T3	514		T9	23		T14	1
valid_sources[0x71]	264160	1			T2	3		T3	512		T9	31
valid_sources[0x72]	215034	1			T2	7		T3	551		T5	13
valid_sources[0x73]	268186	1			T2	5		T3	491		T5	70
valid_sources[0x74]	233425	1			T2	2		T3	802		T4	54
valid_sources[0x75]	199018	1			T2	5		T3	575		T4	44
valid_sources[0x76]	208249	1			T2	4		T3	826		T5	5
valid_sources[0x77]	199119	1			T2	3		T3	621		T4	17
valid_sources[0x78]	236352	1			T2	7		T3	559		T9	22
valid_sources[0x79]	204406	1			T2	3		T3	738		T5	2
valid_sources[0x7a]	214448	1			T2	4		T3	555		T4	68
valid_sources[0x7b]	200285	1			T2	6		T3	709		T5	8
valid_sources[0x7c]	281345	1			T2	3		T3	577		T4	26
valid_sources[0x7d]	246154	1			T2	6		T3	709		T5	10
valid_sources[0x7e]	205497	1			T2	2		T3	603		T5	28
valid_sources[0x7f]	199016	1			T2	6		T3	602		T9	26
valid_sources[0x80]	223766	1			T2	3		T3	613		T4	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22590964

1

T1

18432

T2

524

T3

71963

values[0x0]

all_enables

biggest_size

11399165

1

T1

9220

T2

274

T3

36004

values[0x1]

all_enables

biggest_size

11400138

1

T1

9212

T2

270

T3

36088

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

129284

1

T1

4

T2

12

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47187	1			T2	11		T4	23		T5	34
values[0x0]	54329	1			T1	6		T2	6		T3	1
values[0x1]	58258	1			T1	12		T2	7		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23088	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136686

1

T1

4

T2

13

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	800	1			T15	1		T28	4		T31	16
valid_sources[0x01]	900	1			T31	11		T24	8		T57	1
valid_sources[0x02]	487	1			T1	2		T23	3		T28	1
valid_sources[0x03]	665	1			T5	1		T17	177		T28	3
valid_sources[0x04]	600	1			T5	1		T17	15		T139	1
valid_sources[0x05]	567	1			T5	1		T31	16		T24	1
valid_sources[0x06]	536	1			T1	3		T17	3		T26	1
valid_sources[0x07]	656	1			T5	4		T69	1		T17	167
valid_sources[0x08]	466	1			T1	1		T4	1		T17	2
valid_sources[0x09]	679	1			T1	1		T4	2		T5	2
valid_sources[0x0a]	574	1			T31	21		T24	9		T43	20
valid_sources[0x0b]	527	1			T4	1		T139	1		T28	1
valid_sources[0x0c]	587	1			T140	1		T31	18		T24	7
valid_sources[0x0d]	711	1			T23	4		T28	4		T31	18
valid_sources[0x0e]	652	1			T4	1		T5	1		T69	1
valid_sources[0x0f]	451	1			T4	2		T31	20		T24	6
valid_sources[0x10]	441	1			T17	4		T31	16		T24	4
valid_sources[0x11]	396	1			T5	1		T28	1		T31	20
valid_sources[0x12]	421	1			T28	1		T31	28		T141	1
valid_sources[0x13]	719	1			T5	1		T18	144		T31	22
valid_sources[0x14]	639	1			T4	2		T17	1		T18	116
valid_sources[0x15]	445	1			T5	1		T31	15		T24	7
valid_sources[0x16]	483	1			T17	1		T31	20		T24	1
valid_sources[0x17]	616	1			T17	2		T137	1		T31	11
valid_sources[0x18]	568	1			T4	1		T31	19		T24	5
valid_sources[0x19]	805	1			T4	1		T18	107		T142	1
valid_sources[0x1a]	1001	1			T18	160		T31	14		T24	3
valid_sources[0x1b]	550	1			T12	1		T17	1		T31	14
valid_sources[0x1c]	649	1			T4	2		T5	1		T17	77
valid_sources[0x1d]	611	1			T5	1		T23	4		T31	13
valid_sources[0x1e]	529	1			T5	2		T31	20		T24	16
valid_sources[0x1f]	483	1			T13	7		T17	2		T23	1
valid_sources[0x20]	668	1			T17	1		T140	1		T31	20
valid_sources[0x21]	817	1			T17	117		T28	2		T31	20
valid_sources[0x22]	691	1			T15	1		T17	5		T23	1
valid_sources[0x23]	499	1			T3	1		T17	3		T28	2
valid_sources[0x24]	740	1			T5	2		T31	19		T143	2
valid_sources[0x25]	604	1			T4	1		T17	2		T18	3
valid_sources[0x26]	532	1			T5	1		T17	38		T31	18
valid_sources[0x27]	486	1			T4	1		T31	13		T24	5
valid_sources[0x28]	758	1			T4	1		T17	106		T31	23
valid_sources[0x29]	599	1			T4	2		T11	1		T17	3
valid_sources[0x2a]	669	1			T4	3		T23	2		T31	21
valid_sources[0x2b]	597	1			T31	17		T24	4		T43	10
valid_sources[0x2c]	966	1			T4	1		T17	1		T23	3
valid_sources[0x2d]	479	1			T137	1		T31	16		T24	2
valid_sources[0x2e]	655	1			T18	216		T31	16		T24	5
valid_sources[0x2f]	517	1			T5	2		T69	1		T17	2
valid_sources[0x30]	610	1			T69	1		T17	2		T140	2
valid_sources[0x31]	608	1			T5	1		T17	4		T28	1
valid_sources[0x32]	470	1			T28	1		T56	4		T31	14
valid_sources[0x33]	548	1			T5	1		T31	17		T24	6
valid_sources[0x34]	883	1			T5	1		T16	1		T69	1
valid_sources[0x35]	574	1			T17	3		T23	2		T31	18
valid_sources[0x36]	655	1			T4	1		T5	1		T17	1
valid_sources[0x37]	607	1			T3	1		T4	1		T17	1
valid_sources[0x38]	495	1			T17	1		T31	17		T24	3
valid_sources[0x39]	605	1			T4	1		T18	5		T99	2
valid_sources[0x3a]	549	1			T17	3		T28	1		T31	15
valid_sources[0x3b]	636	1			T1	1		T17	150		T140	1
valid_sources[0x3c]	707	1			T5	1		T17	1		T31	18
valid_sources[0x3d]	443	1			T4	1		T17	1		T31	20
valid_sources[0x3e]	510	1			T4	2		T5	2		T31	13
valid_sources[0x3f]	672	1			T31	12		T24	1		T43	4
valid_sources[0x40]	559	1			T5	2		T31	17		T24	3
valid_sources[0x41]	692	1			T31	23		T24	1		T57	2
valid_sources[0x42]	791	1			T17	357		T139	1		T31	20
valid_sources[0x43]	809	1			T18	169		T31	17		T144	1
valid_sources[0x44]	518	1			T5	1		T23	1		T28	3
valid_sources[0x45]	634	1			T4	1		T31	25		T24	7
valid_sources[0x46]	636	1			T4	1		T17	1		T139	1
valid_sources[0x47]	405	1			T1	1		T28	1		T56	4
valid_sources[0x48]	492	1			T4	1		T28	2		T31	25
valid_sources[0x49]	513	1			T4	2		T17	1		T31	23
valid_sources[0x4a]	456	1			T4	1		T5	1		T31	16
valid_sources[0x4b]	445	1			T28	1		T31	15		T24	4
valid_sources[0x4c]	445	1			T15	1		T17	1		T31	18
valid_sources[0x4d]	647	1			T1	1		T23	1		T31	12
valid_sources[0x4e]	854	1			T18	204		T28	1		T31	23
valid_sources[0x4f]	456	1			T69	1		T17	3		T28	1
valid_sources[0x50]	435	1			T17	2		T31	15		T143	1
valid_sources[0x51]	488	1			T17	3		T31	5		T24	6
valid_sources[0x52]	682	1			T17	5		T31	16		T24	2
valid_sources[0x53]	671	1			T4	2		T17	47		T137	1
valid_sources[0x54]	549	1			T4	1		T5	1		T28	1
valid_sources[0x55]	713	1			T4	2		T17	160		T18	48
valid_sources[0x56]	554	1			T4	1		T28	1		T31	21
valid_sources[0x57]	656	1			T5	1		T54	1		T23	2
valid_sources[0x58]	587	1			T99	1		T31	17		T24	3
valid_sources[0x59]	679	1			T17	59		T18	1		T28	1
valid_sources[0x5a]	691	1			T4	1		T5	1		T139	2
valid_sources[0x5b]	834	1			T28	1		T31	22		T24	1
valid_sources[0x5c]	591	1			T2	1		T145	15		T139	1
valid_sources[0x5d]	627	1			T17	10		T18	3		T31	17
valid_sources[0x5e]	500	1			T55	23		T17	1		T31	12
valid_sources[0x5f]	1116	1			T2	2		T3	1		T4	1
valid_sources[0x60]	506	1			T31	22		T141	3		T43	13
valid_sources[0x61]	478	1			T17	4		T28	1		T137	1
valid_sources[0x62]	644	1			T18	5		T23	7		T28	1
valid_sources[0x63]	519	1			T4	1		T17	1		T23	1
valid_sources[0x64]	666	1			T17	168		T31	23		T24	9
valid_sources[0x65]	676	1			T4	1		T136	2		T28	1
valid_sources[0x66]	617	1			T17	60		T18	3		T31	19
valid_sources[0x67]	630	1			T51	1		T31	21		T24	7
valid_sources[0x68]	1397	1			T139	1		T31	29		T141	1
valid_sources[0x69]	425	1			T18	3		T31	15		T43	4
valid_sources[0x6a]	507	1			T4	1		T28	1		T31	26
valid_sources[0x6b]	402	1			T5	1		T17	1		T31	13
valid_sources[0x6c]	530	1			T31	23		T24	6		T57	1
valid_sources[0x6d]	819	1			T4	1		T31	15		T57	2
valid_sources[0x6e]	682	1			T2	1		T17	46		T31	16
valid_sources[0x6f]	778	1			T4	1		T28	1		T31	15
valid_sources[0x70]	432	1			T4	2		T19	1		T28	1
valid_sources[0x71]	571	1			T4	2		T5	1		T28	1
valid_sources[0x72]	618	1			T17	111		T31	25		T146	8
valid_sources[0x73]	501	1			T18	3		T28	1		T31	18
valid_sources[0x74]	503	1			T18	6		T28	2		T31	18
valid_sources[0x75]	645	1			T1	1		T4	1		T5	1
valid_sources[0x76]	771	1			T17	2		T28	1		T31	16
valid_sources[0x77]	904	1			T4	1		T5	1		T69	1
valid_sources[0x78]	510	1			T4	1		T17	1		T28	2
valid_sources[0x79]	651	1			T17	1		T23	4		T28	2
valid_sources[0x7a]	647	1			T4	2		T31	18		T24	1
valid_sources[0x7b]	593	1			T5	1		T18	3		T31	14
valid_sources[0x7c]	405	1			T4	3		T5	1		T31	20
valid_sources[0x7d]	788	1			T69	2		T17	3		T31	17
valid_sources[0x7e]	739	1			T5	1		T17	102		T31	15
valid_sources[0x7f]	487	1			T4	2		T5	1		T12	1
valid_sources[0x80]	622	1			T17	4		T28	1		T31	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35674

1

T2

8

T4

12

T5

19

values[0x0]

all_enables

biggest_size

47507

1

T1

3

T2

2

T4

16

values[0x1]

all_enables

biggest_size

46103

1

T1

1

T2

2

T3

1