Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

12326225

1

T2

5

T3

14418

T4

24537

full_word

41062999

1

T1

36864

T2

66

T3

144055

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	53388934	1			T1	36864		T2	71		T3	158473
auto[TlIntgErrCmd]	95	1			T108	10		T109	4		T110	6
auto[TlIntgErrData]	91	1			T108	3		T109	9		T110	10
auto[TlIntgErrBoth]	104	1			T108	7		T109	7		T110	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24211728

1

T1

18432

T2

44

T3

79190

auto[1]

29177496

1

T1

18432

T2

27

T3

79283

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5895122	1			T2	2		T3	7227		T4	9491
auto[TlIntgErrNone]	partial	auto[1]	6430836	1			T2	3		T3	7191		T4	15046
auto[TlIntgErrNone]	full_word	auto[0]	18316490	1			T1	18432		T2	42		T3	71963
auto[TlIntgErrNone]	full_word	auto[1]	22746486	1			T1	18432		T2	24		T3	72092
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T108	4		T109	3		T110	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T108	6		T109	1		T110	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T123	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T110	1		T128	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T108	2		T109	3		T110	4
auto[TlIntgErrData]	partial	auto[1]	43	1			T108	1		T109	5		T110	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T109	1		T129	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T110	2		T121	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T108	3		T109	3		T110	3
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T108	3		T109	4		T110	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T121	1		T123	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T108	1		T120	1		T124	2