Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	666576	1			T2	12		T11	57		T12	1947
auto[1]	8080353	1			T2	2		T3	65737		T4	11371
auto[2]	553979	1			T2	6		T5	1		T10	1
auto[3]	7982477	1			T3	66064		T4	11234		T7	2

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10060622	1			T2	15		T3	109905		T4	18892
auto[1]	1754492	1			T2	2		T3	10464		T4	1757
auto[2]	1748219	1			T2	3		T3	10459		T4	1774
auto[3]	3720052	1			T3	973		T4	182		T7	5

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3554083

1

T2

20

T3

39

T4

22585

auto[1]

13729302

1

T3

131762

T4

20

T15

178051

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	272566	1			T2	11		T12	1625		T17	294
auto[0]	auto[0]	auto[1]	27834	1			T11	1		T12	152		T17	33
auto[0]	auto[0]	auto[2]	27748	1			T2	1		T11	1		T12	159
auto[0]	auto[0]	auto[3]	8132	1			T11	55		T12	11		T17	3
auto[0]	auto[1]	auto[0]	1170107	1			T2	1		T3	20		T4	9531
auto[0]	auto[1]	auto[1]	142497	1			T2	1		T3	1		T4	838
auto[0]	auto[1]	auto[2]	122577	1			T3	2		T4	900		T5	2
auto[0]	auto[1]	auto[3]	48766	1			T4	93		T7	3		T16	96
auto[0]	auto[2]	auto[0]	234787	1			T2	3		T5	1		T10	1
auto[0]	auto[2]	auto[1]	24253	1			T2	1		T11	1		T12	166
auto[0]	auto[2]	auto[2]	22723	1			T2	2		T11	1		T12	137
auto[0]	auto[2]	auto[3]	6550	1			T11	39		T12	13		T17	2
auto[0]	auto[3]	auto[0]	1135002	1			T3	10		T4	9342		T5	7
auto[0]	auto[3]	auto[1]	118461	1			T3	3		T4	919		T16	8
auto[0]	auto[3]	auto[2]	139772	1			T3	3		T4	873		T5	2
auto[0]	auto[3]	auto[3]	52308	1			T4	89		T7	2		T16	149
auto[1]	auto[0]	auto[0]	11274	1			T17	1		T136	2		T23	1
auto[1]	auto[0]	auto[1]	48806	1			T103	2415		T30	1		T105	3863
auto[1]	auto[0]	auto[2]	48982	1			T17	1		T137	1		T29	2
auto[1]	auto[0]	auto[3]	221234	1			T54	1		T103	11094		T105	17372
auto[1]	auto[1]	auto[0]	3613710	1			T3	54765		T4	8		T15	74571
auto[1]	auto[1]	auto[1]	688102	1			T3	4955		T15	6614		T69	3
auto[1]	auto[1]	auto[2]	668167	1			T3	5529		T4	1		T15	7406
auto[1]	auto[1]	auto[3]	1626427	1			T3	465		T15	700		T69	1
auto[1]	auto[2]	auto[0]	9614	1			T12	5		T136	1		T23	1
auto[1]	auto[2]	auto[1]	42489	1			T136	1		T29	1		T103	1485
auto[1]	auto[2]	auto[2]	38677	1			T137	4		T29	1		T103	2686
auto[1]	auto[2]	auto[3]	174886	1			T103	11859		T105	11452		T138	16278
auto[1]	auto[3]	auto[0]	3613562	1			T3	55110		T4	11		T15	74039
auto[1]	auto[3]	auto[1]	662050	1			T3	5505		T15	7430		T69	2
auto[1]	auto[3]	auto[2]	679573	1			T3	4925		T15	6601		T69	1
auto[1]	auto[3]	auto[3]	1581749	1			T3	508		T15	690		T69	1