Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	272373270	124082	0	0
ctrl_regwen_rd_A	272373270	5210	0	0
exec_rd_A	272373270	4973	0	0
exec_regwen_rd_A	272373270	5189	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272373270	124082	0	0
T17	218219	4162	0	0
T18	109865	2688	0	0
T24	0	959	0	0
T26	1423	0	0	0
T31	0	5047	0	0
T32	1908	0	0	0
T43	0	2078	0	0
T44	0	3733	0	0
T45	0	5555	0	0
T46	0	742	0	0
T47	0	1795	0	0
T48	0	4849	0	0
T49	107984	0	0	0
T50	15742	0	0	0
T51	89085	0	0	0
T52	6054	0	0	0
T53	249446	0	0	0
T54	16894	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272373270	5210	0	0
T17	218219	878	0	0
T18	109865	0	0	0
T24	0	249	0	0
T26	1423	0	0	0
T32	1908	0	0	0
T49	107984	0	0	0
T50	15742	0	0	0
T51	89085	0	0	0
T52	6054	0	0	0
T53	249446	0	0	0
T54	16894	0	0	0
T111	0	429	0	0
T112	0	196	0	0
T113	0	204	0	0
T114	0	224	0	0
T115	0	421	0	0
T116	0	627	0	0
T117	0	373	0	0
T118	0	4	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272373270	4973	0	0
T17	218219	866	0	0
T18	109865	0	0	0
T24	0	175	0	0
T26	1423	0	0	0
T32	1908	0	0	0
T49	107984	0	0	0
T50	15742	0	0	0
T51	89085	0	0	0
T52	6054	0	0	0
T53	249446	0	0	0
T54	16894	0	0	0
T111	0	505	0	0
T112	0	132	0	0
T113	0	252	0	0
T114	0	242	0	0
T115	0	293	0	0
T116	0	562	0	0
T117	0	382	0	0
T118	0	6	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272373270	5189	0	0
T17	218219	791	0	0
T18	109865	0	0	0
T24	0	164	0	0
T26	1423	0	0	0
T32	1908	0	0	0
T49	107984	0	0	0
T50	15742	0	0	0
T51	89085	0	0	0
T52	6054	0	0	0
T53	249446	0	0	0
T54	16894	0	0	0
T111	0	488	0	0
T112	0	184	0	0
T113	0	254	0	0
T114	0	251	0	0
T115	0	296	0	0
T116	0	576	0	0
T117	0	380	0	0
T118	0	1	0	0