Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	120798174	1			T1	390698		T2	381906		T3	17450
instr_valid_dis	91979576	1			T1	201496		T2	381906		T3	17450
instr_en	19231416	1			T1	189146		T9	354902		T16	310536

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	8795430	1			T1	18754		T9	84258		T16	225398
sram_ifetch_valid_disable	93553488	1			T1	271598		T2	381906		T3	17450
sram_ifetch_enable	18449256	1			T1	100346		T9	136848		T16	365066

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	120798174	1			T1	390698		T2	381906		T3	17450
hw_debug_en_valid_off	93696366	1			T1	249616		T2	381906		T3	17450
hw_debug_en_on	16916924	1			T1	95694		T9	247424		T16	382978

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	93553488	1			T1	271598		T2	381906		T3	17450
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	81974489	1			T1	147656		T2	381906		T3	17450
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7926225	1			T1	123942		T9	133796		T16	104596
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3507628	1			T1	18754		T9	19150		T16	73242
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1598878	1			T27	20000		T141	30764		T140	27024
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1387260	1			T1	18754		T9	19150		T16	69818
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3362464	1			T9	65108		T16	96376		T27	89010
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1139958	1			T16	26904		T27	89010		T141	18586
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1567462	1			T9	65108		T16	20532		T28	91890
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6765710	1			T1	42858		T9	65924		T16	125768
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2528064	1			T1	9940		T16	27104		T27	3478
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2949152	1			T1	32918		T9	65924		T16	72070

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7642633	1			T1	46450		T9	136848		T16	115590
lc_exec_en	6788750	1			T1	52836		T9	116392		T16	160834
valid_exec_dis	89277581	1			T1	237192		T2	381906		T3	17450
invalid_exec_dis	27244686	1			T1	119100		T9	221106		T16	590464